##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

Update and debug UART
martin -
r99:fb73d940a921 martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,41
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef ADC_DRIVER_H
23 #define ADC_DRIVER_H
24
25 #include "apb_fifo_Driver.h"
26 #include "apb_uart_Driver.h"
27 #include "apb_gpio_Driver.h"
28
29 #define samplecnt 4096
30 #define Mask 0x0000FFFF
31
32 /*===================================================
33 F U N C T I O N S
34 ====================================================*/
35
36 void flushFIFO(FIFO_Device*,GPIO_Device*);
37 void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
38 void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
39 void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
40
41 #endif
Show file before | Show file after | Hide comments
@@ -0,0 +1,93
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #include "ADC_Driver.h"
23 #include <stdio.h>
24
25 unsigned char packetNumber = 0;
26
27 void flushFIFO(FIFO_Device*fifo,GPIO_Device* adcResetPin)
28 {
29 adcResetPin->Dout = 0x0;
30 int trash;
31 while((fifo->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS
32 trash = fifo->FIFOreg[(2*0)+FIFO_RWdata];
33 trash = fifo->FIFOreg[(2*1)+FIFO_RWdata];
34 trash = fifo->FIFOreg[(2*2)+FIFO_RWdata];
35 trash = fifo->FIFOreg[(2*3)+FIFO_RWdata];
36 trash = fifo->FIFOreg[(2*4)+FIFO_RWdata];
37 }
38
39 adcResetPin->Dout = 0x1;
40 }
41
42 void getPacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize)
43 {
44 int i=0;
45 for(i=0;i<packetSize;i++)
46 {
47 while((fifo->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty);
48 CH1[i] = (fifo->FIFOreg[(2*0)+FIFO_RWdata] & Mask);
49 CH2[i] = (fifo->FIFOreg[(2*1)+FIFO_RWdata] & Mask);
50 CH3[i] = (fifo->FIFOreg[(2*2)+FIFO_RWdata] & Mask);
51 CH4[i] = (fifo->FIFOreg[(2*3)+FIFO_RWdata] & Mask);
52 CH5[i] = (fifo->FIFOreg[(2*4)+FIFO_RWdata] & Mask);
53 }
54 }
55
56 void mkfakePacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize)
57 {
58 int i=0;
59 for(i=0;i<packetSize;i++)
60 {
61 CH1[i] = (unsigned short)(i);
62 CH2[i] = (unsigned short)(i+10);
63 CH3[i] = (unsigned short)(i+20);
64 CH4[i] = (unsigned short)(i+30);
65 CH5[i] = (unsigned short)(i+40);
66 }
67 }
68
69
70 void sendPacket(UART_Device* uart0,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize)
71 {
72 int i=0;
73
74 for(i=0;i<packetSize;i++)
75 {
76 uartputc(uart0,0xa5);
77 uartputc(uart0,0x0f);
78 uartputc(uart0,packetNumber++);
79 uartputc(uart0,(char)(CH1[i]>>8));
80 uartputc(uart0,(char)CH1[i]);
81 uartputc(uart0,(char)(CH2[i]>>8));
82 uartputc(uart0,(char)CH2[i]);
83 uartputc(uart0,(char)(CH3[i]>>8));
84 uartputc(uart0,(char)CH3[i]);
85 uartputc(uart0,(char)(CH4[i]>>8));
86 uartputc(uart0,(char)CH4[i]);
87 uartputc(uart0,(char)(CH5[i]>>8));
88 uartputc(uart0,(char)CH5[i]);
89 uartputc(uart0,0xf0);
90 uartputc(uart0,0x5a);
91 }
92
93 }
Show file before | Show file after | Hide comments
@@ -0,0 +1,41
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef ADC_DRIVER_H
23 #define ADC_DRIVER_H
24
25 #include "apb_fifo_Driver.h"
26 #include "apb_uart_Driver.h"
27 #include "apb_gpio_Driver.h"
28
29 #define samplecnt 4096
30 #define Mask 0x0000FFFF
31
32 /*===================================================
33 F U N C T I O N S
34 ====================================================*/
35
36 void flushFIFO(FIFO_Device*,GPIO_Device*);
37 void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
38 void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
39 void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int);
40
41 #endif
Show file before | Show file after | Hide comments
@@ -0,0 +1,25
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = adc_Driver
20 LIB = liblpp_adc_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
Show file before | Show file after | Hide comments
@@ -7,13 +7,8 int main()
7 7 {
8 8 printf("Debut Main\n\n");
9 9 UART_Device* dev = openUART(0);
10 printf("addr: %x\n",(unsigned int)dev);
11 printf("cfg: %x\n",dev->ConfigReg);
12 char* a = "hello world\n";
13 uartputs(dev,a);
14 printf("Try #1 done\n");
15 uartputs(dev,"salut monde\n");
16 printf("Try #2 done\n");
10 while(1){
11 uartputc(dev,uartgetc(dev));
12 }
17 13 return 0;
18 14 }
19
Show file before | Show file after | Hide comments
@@ -30,6 +30,7 all:
30 30 make all -C FFT
31 31 make all -C DELAY
32 32 make all -C GPIO
33 make all -C ADC
33 34 make all -C MATRIX
34 35
35 36
@@ -42,5 +43,6 cleanall:
42 43 make clean -C FFT
43 44 make clean -C DELAY
44 45 make clean -C GPIO
46 make clean -C ADC
45 47 make clean -C MATRIX
46 48
Show file before | Show file after | Hide comments
@@ -38,7 +38,6 void uartputc(UART_Device* dev,char c)
38 38 //while (!(dev->ConfigReg & (1<<5)));
39 39 while (!((dev->ConfigReg & DataSended) == DataSended));
40 40 dev->DataWReg = c;
41 printf(" ");
42 41 }
43 42
44 43 void uartputs(UART_Device* dev,char* s)
Show file before | Show file after | Hide comments
@@ -93,15 +93,9 Rec.UART_Cfg(2) <= NwData;
93 93 begin
94 94 if(rst='0')then
95 95 Rec.UART_Wdata <= (others => '0');
96
96 Send <= '0';
97 97
98 98 elsif(clk'event and clk='1')then
99 temp_ND <= NwData;
100 if(NwData='1' and temp_ND='1')then
101 ACK <= '1';
102 else
103 ACK <= '0';
104 end if;
105 99
106 100 --APB Write OP
107 101 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
@@ -109,13 +103,13 Rec.UART_Cfg(2) <= NwData;
109 103 when "000000" =>
110 104 Rec.UART_Cfg(0) <= apbi.pwdata(0);
111 105 when "000001" =>
112 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
113 Send <= '1';
106 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
107 Send <= '1';
114 108 when others =>
115 109 null;
116 110 end case;
117 else
118 Send <= '0';
111 elsif(Sended = '0')then
112 Send <= '0';
119 113 end if;
120 114
121 115 --APB READ OP
@@ -133,9 +127,12 Rec.UART_Cfg(2) <= NwData;
133 127 when "000010" =>
134 128 Rdata(31 downto 8) <= X"EEEEEE";
135 129 Rdata(7 downto 0) <= Rec.UART_Rdata;
130 ACK <= '1';
136 131 when others =>
137 132 Rdata <= (others => '0');
138 133 end case;
134 else
135 ACK <= '0';
139 136 end if;
140 137
141 138 end if;
Show file before | Show file after | Hide comments
@@ -28,14 +28,12 use IEEE.std_logic_1164.all;
28 28 --! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
29 29 --! \todo move to general purpose library, explain more in detail the code and add some schematic in doc.
30 30
31 entity Shift_REG is
31 entity Shift_Reg is
32 32 generic(
33 33 Data_sz : integer := 10 --! Width of the shift register
34 34 );
35 35 port(
36 clk : in std_logic; --! System clock
37 36 Sclk : in std_logic; --! Serial clock
38 reset : in std_logic; --! System reset
39 37 SIN : in std_logic; --! Serial data in
40 38 SOUT : out std_logic; --! Serial data out
41 39 Serialize : in std_logic; --! Launch serialization
@@ -46,72 +44,49 port(
46 44 end entity;
47 45
48 46
49 architecture ar_Shift_REG of Shift_REG is
47 architecture ar_Shift_Reg of Shift_Reg is
50 48
51 49 signal REG : std_logic_vector(Data_sz-1 downto 0);
52 signal Serialized_int : std_logic;
53 signal Serialize_reg : std_logic;
54 signal Serial_reg : std_logic;
55 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
50 signal CptBits : std_logic_vector(Data_sz-1 downto 0) := (others => '0');
56 51 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
57 signal CptBits_flag : std_logic;
58 signal CptBits_flag_reg : std_logic;
52 signal CptBits_flag : std_logic :='0';
53 signal Serialized_int : std_logic :='1';
59 54
60 55 begin
61 56
62 Serialized <= Serialized_int;
63 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
64
65 process(reset,clk)
57 CptBits_flag <= '1' when CptBits=CptBits_trig else '0';
58 Serialized <= Serialized_int;
59 process(Serialize,Sclk,D)
66 60 begin
67 if reset = '0' then
68 Serialized_int <= '1';
69 CptBits_flag_reg <= '0';
70 Serial_reg <= '0';
71 Q <= (others => '0');
72 elsif clk'event and clk = '1' then
73 CptBits_flag_reg <= CptBits_flag;
74 Serial_reg <= Serialize;
75
76 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
77 Serialized_int <= '1';
78 Q <= REG;
79 elsif(Serial_reg='0' and Serialize='1')then
80 Serialized_int <= '0';
61 if(Serialize = '1') then
62 REG <= D;
63 CptBits <= (others => '0');
64 Serialized_int <= '0';
65 Q <= REG;
66 SOUT <= '1';
67 elsif Sclk'event and Sclk = '1' then
68 if(Serialized_int='0') then
69 REG <= SIN & REG(Data_sz-1 downto 1);
70 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
71 SOUT <= REG(0);
72 if(CptBits_flag = '1') then
73 Serialized_int <= '1';
74 Q <= REG;
75 end if;
76 else
77 SOUT <= '1';
78 Serialized_int <= '1';
79 -- Q <= REG;
81 80 end if;
82 81 end if;
83 82 end process;
84 83
84 end architecture;
85 85
86 process(reset,Sclk)
87 begin
88 if reset = '0' then
89 CptBits <= (others => '0');
90 REG <= (others => '0');
91 SOUT <= '1';
92 Serialize_reg <= '0';
93 elsif Sclk'event and Sclk = '1' then
94 Serialize_reg <= Serialized_int;
95 if (Serialized_int = '0' and Serialize_reg ='1') then
96 REG <= SIN & D(Data_sz-1 downto 1);
97 SOUT <= D(0);
98 elsif Serialized_int = '0' then
99 REG <= SIN & REG(Data_sz-1 downto 1);
100 SOUT <= REG(0);
101 else
102 SOUT <= '1';
103 end if;
104 if Serialized_int = '0' then
105 if CptBits_flag = '1' then
106 CptBits <= (others => '0');
107 else
108 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
109 end if;
110 else
111 CptBits <= (others => '0');
112 end if;
113
114 end if;
115 end process;
86
87
88
116 89
117 end ar_Shift_REG;
90
91
92
Show file before | Show file after | Hide comments
@@ -51,56 +51,52 end entity;
51 51 architecture ar_UART of UART is
52 52 signal Bclk : std_logic;
53 53
54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
56 56
57 signal TXD_Dummy : std_logic;
58 signal NwDat_int : std_logic;
59 signal NwDat_int_reg : std_logic;
60 signal receive : std_logic;
61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
57 signal Take : std_logic;
58 signal Taken : std_logic;
59 signal Taken_reg : std_logic;
60
61 constant Dummy : std_logic_vector(Data_sz+1 downto 0) := (others => '1');
62 62
63 63 begin
64 64
65
65 NwDat <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1');
66 WDATA_int <= '1' & WDATA & '0';
66 67
67 WDATA_int <= '1' & WDATA & '0';
68
69 BaudGenerator : entity work.BaudGen
68 BaudGenerator : BaudGen
70 69 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
71 70
72
73 RX_REG : entity work.Shift_REG
71 RX_REG : Shift_Reg
74 72 generic map(Data_sz+2)
75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
73 port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int);
76 74
77 TX_REG : entity work.Shift_REG
75 TX_REG : Shift_Reg
78 76 generic map(Data_sz+2)
79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
80
81
77 port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open);
82 78
83 79 process(clk,reset)
84 80 begin
85 if reset = '0' then
86 NwDat <= '0';
87 elsif clk'event and clk = '1' then
88 NwDat_int_reg <= NwDat_int;
89 if RXD = '1' and NwDat_int = '1' then
90 receive <= '0';
91 elsif RXD = '0' then
92 receive <= '1';
81 if(reset ='0')then
82 Take <= '0';
83
84 elsif(clk'event and clk ='1')then
85 Taken_reg <= Taken;
86
87 if(RXD ='0' and Taken ='1')then
88 Take <= '1';
89 elsif(Taken ='0')then
90 Take <= '0';
93 91 end if;
94 if NwDat_int_reg = '0' and NwDat_int = '1' then
95 NwDat <= '1';
96 RDATA <= RDATA_int(8 downto 1);
97 elsif ack = '1' then
98 NwDat <= '0';
92
93 if (Taken_reg ='0' and Taken ='1') then
94 RDATA <= RDATA_int(8 downto 1);
99 95 end if;
96
100 97 end if;
101 98 end process;
102 99
103 end ar_UART;
100 end architecture;
104 101
105 102
106
Show file before | Show file after | Hide comments
@@ -41,25 +41,24 port(
41 41 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
42 42 Sended : out std_logic; --! Flag, Envoi termine
43 43 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
44 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
44 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word
45 45 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
46 46 );
47 47 end component;
48 48
49 49
50 component Shift_REG is
51 generic(Data_sz : integer := 10);
50 component Shift_Reg is
51 generic(
52 Data_sz : integer := 10 --! Width of the shift register
53 );
52 54 port(
53 clk : in std_logic;
54 Sclk : in std_logic;
55 reset : in std_logic;
56 SIN : in std_logic;
57 SOUT : out std_logic;
58 Serialize : in std_logic;
59 Serialized : out std_logic;
60 D : in std_logic_vector(Data_sz-1 downto 0);
61 Q : out std_logic_vector(Data_sz-1 downto 0)
62
55 Sclk : in std_logic; --! Serial clock
56 SIN : in std_logic; --! Serial data in
57 SOUT : out std_logic; --! Serial data out
58 Serialize : in std_logic; --! Launch serialization
59 Serialized : out std_logic; --! Serialization complete
60 D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out
61 Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data
63 62 );
64 63 end component;
65 64
General Comments 0
You need to be logged in to leave comments. Login now