diff --git a/LPP_drivers/exemples/BenchUART/main.c b/LPP_drivers/exemples/BenchUART/main.c --- a/LPP_drivers/exemples/BenchUART/main.c +++ b/LPP_drivers/exemples/BenchUART/main.c @@ -7,13 +7,8 @@ int main() { printf("Debut Main\n\n"); UART_Device* dev = openUART(0); - printf("addr: %x\n",(unsigned int)dev); - printf("cfg: %x\n",dev->ConfigReg); - char* a = "hello world\n"; - uartputs(dev,a); - printf("Try #1 done\n"); - uartputs(dev,"salut monde\n"); - printf("Try #2 done\n"); + while(1){ + uartputc(dev,uartgetc(dev)); + } return 0; } - diff --git a/LPP_drivers/includes/ADC_Driver.h b/LPP_drivers/includes/ADC_Driver.h new file mode 100644 --- /dev/null +++ b/LPP_drivers/includes/ADC_Driver.h @@ -0,0 +1,41 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#ifndef ADC_DRIVER_H +#define ADC_DRIVER_H + +#include "apb_fifo_Driver.h" +#include "apb_uart_Driver.h" +#include "apb_gpio_Driver.h" + +#define samplecnt 4096 +#define Mask 0x0000FFFF + +/*=================================================== + F U N C T I O N S +====================================================*/ + +void flushFIFO(FIFO_Device*,GPIO_Device*); +void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); +void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); +void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); + +#endif diff --git a/LPP_drivers/libsrc/ADC/ADC_Driver.c b/LPP_drivers/libsrc/ADC/ADC_Driver.c new file mode 100644 --- /dev/null +++ b/LPP_drivers/libsrc/ADC/ADC_Driver.c @@ -0,0 +1,93 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#include "ADC_Driver.h" +#include + +unsigned char packetNumber = 0; + +void flushFIFO(FIFO_Device*fifo,GPIO_Device* adcResetPin) +{ + adcResetPin->Dout = 0x0; + int trash; + while((fifo->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS + trash = fifo->FIFOreg[(2*0)+FIFO_RWdata]; + trash = fifo->FIFOreg[(2*1)+FIFO_RWdata]; + trash = fifo->FIFOreg[(2*2)+FIFO_RWdata]; + trash = fifo->FIFOreg[(2*3)+FIFO_RWdata]; + trash = fifo->FIFOreg[(2*4)+FIFO_RWdata]; + } + + adcResetPin->Dout = 0x1; +} + +void getPacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize) +{ + int i=0; + for(i=0;iFIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); + CH1[i] = (fifo->FIFOreg[(2*0)+FIFO_RWdata] & Mask); + CH2[i] = (fifo->FIFOreg[(2*1)+FIFO_RWdata] & Mask); + CH3[i] = (fifo->FIFOreg[(2*2)+FIFO_RWdata] & Mask); + CH4[i] = (fifo->FIFOreg[(2*3)+FIFO_RWdata] & Mask); + CH5[i] = (fifo->FIFOreg[(2*4)+FIFO_RWdata] & Mask); + } +} + +void mkfakePacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize) +{ + int i=0; + for(i=0;i>8)); + uartputc(uart0,(char)CH1[i]); + uartputc(uart0,(char)(CH2[i]>>8)); + uartputc(uart0,(char)CH2[i]); + uartputc(uart0,(char)(CH3[i]>>8)); + uartputc(uart0,(char)CH3[i]); + uartputc(uart0,(char)(CH4[i]>>8)); + uartputc(uart0,(char)CH4[i]); + uartputc(uart0,(char)(CH5[i]>>8)); + uartputc(uart0,(char)CH5[i]); + uartputc(uart0,0xf0); + uartputc(uart0,0x5a); + } + +} diff --git a/LPP_drivers/libsrc/ADC/ADC_Driver.h b/LPP_drivers/libsrc/ADC/ADC_Driver.h new file mode 100644 --- /dev/null +++ b/LPP_drivers/libsrc/ADC/ADC_Driver.h @@ -0,0 +1,41 @@ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ +#ifndef ADC_DRIVER_H +#define ADC_DRIVER_H + +#include "apb_fifo_Driver.h" +#include "apb_uart_Driver.h" +#include "apb_gpio_Driver.h" + +#define samplecnt 4096 +#define Mask 0x0000FFFF + +/*=================================================== + F U N C T I O N S +====================================================*/ + +void flushFIFO(FIFO_Device*,GPIO_Device*); +void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); +void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); +void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); + +#endif diff --git a/LPP_drivers/libsrc/ADC/Makefile b/LPP_drivers/libsrc/ADC/Makefile new file mode 100644 --- /dev/null +++ b/LPP_drivers/libsrc/ADC/Makefile @@ -0,0 +1,25 @@ +#------------------------------------------------------------------------------ +#-- This file is a part of the LPP VHDL IP LIBRARY +#-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +#-- +#-- This program is free software; you can redistribute it and/or modify +#-- it under the terms of the GNU General Public License as published by +#-- the Free Software Foundation; either version 3 of the License, or +#-- (at your option) any later version. +#-- +#-- This program is distributed in the hope that it will be useful, +#-- but WITHOUT ANY WARRANTY; without even the implied warranty of +#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +#-- GNU General Public License for more details. +#-- +#-- You should have received a copy of the GNU General Public License +#-- along with this program; if not, write to the Free Software +#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +#------------------------------------------------------------------------------ +FILE = adc_Driver +LIB = liblpp_adc_Driver.a + +include ../../rules.mk + +all: $(FILE).a + @echo $(FILE)".a created" diff --git a/LPP_drivers/libsrc/Makefile b/LPP_drivers/libsrc/Makefile --- a/LPP_drivers/libsrc/Makefile +++ b/LPP_drivers/libsrc/Makefile @@ -30,6 +30,7 @@ all: make all -C FFT make all -C DELAY make all -C GPIO + make all -C ADC make all -C MATRIX @@ -42,5 +43,6 @@ cleanall: make clean -C FFT make clean -C DELAY make clean -C GPIO + make clean -C ADC make clean -C MATRIX diff --git a/LPP_drivers/libsrc/UART/apb_uart_Driver.c b/LPP_drivers/libsrc/UART/apb_uart_Driver.c --- a/LPP_drivers/libsrc/UART/apb_uart_Driver.c +++ b/LPP_drivers/libsrc/UART/apb_uart_Driver.c @@ -38,7 +38,6 @@ void uartputc(UART_Device* dev,char c) //while (!(dev->ConfigReg & (1<<5))); while (!((dev->ConfigReg & DataSended) == DataSended)); dev->DataWReg = c; - printf(" "); } void uartputs(UART_Device* dev,char* s) diff --git a/lib/lpp/lpp_uart/APB_UART.vhd b/lib/lpp/lpp_uart/APB_UART.vhd --- a/lib/lpp/lpp_uart/APB_UART.vhd +++ b/lib/lpp/lpp_uart/APB_UART.vhd @@ -93,15 +93,9 @@ Rec.UART_Cfg(2) <= NwData; begin if(rst='0')then Rec.UART_Wdata <= (others => '0'); - + Send <= '0'; elsif(clk'event and clk='1')then - temp_ND <= NwData; - if(NwData='1' and temp_ND='1')then - ACK <= '1'; - else - ACK <= '0'; - end if; --APB Write OP if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then @@ -109,13 +103,13 @@ Rec.UART_Cfg(2) <= NwData; when "000000" => Rec.UART_Cfg(0) <= apbi.pwdata(0); when "000001" => - Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); - Send <= '1'; + Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); + Send <= '1'; when others => null; end case; - else - Send <= '0'; + elsif(Sended = '0')then + Send <= '0'; end if; --APB READ OP @@ -133,9 +127,12 @@ Rec.UART_Cfg(2) <= NwData; when "000010" => Rdata(31 downto 8) <= X"EEEEEE"; Rdata(7 downto 0) <= Rec.UART_Rdata; + ACK <= '1'; when others => Rdata <= (others => '0'); end case; + else + ACK <= '0'; end if; end if; diff --git a/lib/lpp/lpp_uart/Shift_REG.vhd b/lib/lpp/lpp_uart/Shift_REG.vhd --- a/lib/lpp/lpp_uart/Shift_REG.vhd +++ b/lib/lpp/lpp_uart/Shift_REG.vhd @@ -28,14 +28,12 @@ use IEEE.std_logic_1164.all; --! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr --! \todo move to general purpose library, explain more in detail the code and add some schematic in doc. -entity Shift_REG is +entity Shift_Reg is generic( Data_sz : integer := 10 --! Width of the shift register ); port( - clk : in std_logic; --! System clock Sclk : in std_logic; --! Serial clock - reset : in std_logic; --! System reset SIN : in std_logic; --! Serial data in SOUT : out std_logic; --! Serial data out Serialize : in std_logic; --! Launch serialization @@ -46,72 +44,49 @@ port( end entity; -architecture ar_Shift_REG of Shift_REG is +architecture ar_Shift_Reg of Shift_Reg is signal REG : std_logic_vector(Data_sz-1 downto 0); -signal Serialized_int : std_logic; -signal Serialize_reg : std_logic; -signal Serial_reg : std_logic; -signal CptBits : std_logic_vector(Data_sz-1 downto 0); +signal CptBits : std_logic_vector(Data_sz-1 downto 0) := (others => '0'); constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); -signal CptBits_flag : std_logic; -signal CptBits_flag_reg : std_logic; +signal CptBits_flag : std_logic :='0'; +signal Serialized_int : std_logic :='1'; begin -Serialized <= Serialized_int; -CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; - -process(reset,clk) +CptBits_flag <= '1' when CptBits=CptBits_trig else '0'; +Serialized <= Serialized_int; +process(Serialize,Sclk,D) begin - if reset = '0' then - Serialized_int <= '1'; - CptBits_flag_reg <= '0'; - Serial_reg <= '0'; - Q <= (others => '0'); - elsif clk'event and clk = '1' then - CptBits_flag_reg <= CptBits_flag; - Serial_reg <= Serialize; - - if CptBits_flag = '1' and CptBits_flag_reg = '0' then - Serialized_int <= '1'; - Q <= REG; - elsif(Serial_reg='0' and Serialize='1')then - Serialized_int <= '0'; + if(Serialize = '1') then + REG <= D; + CptBits <= (others => '0'); + Serialized_int <= '0'; + Q <= REG; + SOUT <= '1'; + elsif Sclk'event and Sclk = '1' then + if(Serialized_int='0') then + REG <= SIN & REG(Data_sz-1 downto 1); + CptBits <= '1' & CptBits(Data_sz-1 downto 1); + SOUT <= REG(0); + if(CptBits_flag = '1') then + Serialized_int <= '1'; + Q <= REG; + end if; + else + SOUT <= '1'; + Serialized_int <= '1'; +-- Q <= REG; end if; end if; end process; +end architecture; -process(reset,Sclk) -begin - if reset = '0' then - CptBits <= (others => '0'); - REG <= (others => '0'); - SOUT <= '1'; - Serialize_reg <= '0'; - elsif Sclk'event and Sclk = '1' then - Serialize_reg <= Serialized_int; - if (Serialized_int = '0' and Serialize_reg ='1') then - REG <= SIN & D(Data_sz-1 downto 1); - SOUT <= D(0); - elsif Serialized_int = '0' then - REG <= SIN & REG(Data_sz-1 downto 1); - SOUT <= REG(0); - else - SOUT <= '1'; - end if; - if Serialized_int = '0' then - if CptBits_flag = '1' then - CptBits <= (others => '0'); - else - CptBits <= '1' & CptBits(Data_sz-1 downto 1); - end if; - else - CptBits <= (others => '0'); - end if; - - end if; -end process; + + + -end ar_Shift_REG; + + + diff --git a/lib/lpp/lpp_uart/UART.vhd b/lib/lpp/lpp_uart/UART.vhd --- a/lib/lpp/lpp_uart/UART.vhd +++ b/lib/lpp/lpp_uart/UART.vhd @@ -51,56 +51,52 @@ end entity; architecture ar_UART of UART is signal Bclk : std_logic; -signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); -signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); +signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); +signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); -signal TXD_Dummy : std_logic; -signal NwDat_int : std_logic; -signal NwDat_int_reg : std_logic; -signal receive : std_logic; -constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0'); +signal Take : std_logic; +signal Taken : std_logic; +signal Taken_reg : std_logic; + +constant Dummy : std_logic_vector(Data_sz+1 downto 0) := (others => '1'); begin - +NwDat <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1'); +WDATA_int <= '1' & WDATA & '0'; -WDATA_int <= '1' & WDATA & '0'; - -BaudGenerator : entity work.BaudGen +BaudGenerator : BaudGen port map(clk,reset,Capture,Bclk,RXD,BTrigger); - -RX_REG : entity work.Shift_REG +RX_REG : Shift_Reg generic map(Data_sz+2) - port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int); + port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int); -TX_REG : entity work.Shift_REG +TX_REG : Shift_Reg generic map(Data_sz+2) - port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int); - - + port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open); process(clk,reset) begin - if reset = '0' then - NwDat <= '0'; - elsif clk'event and clk = '1' then - NwDat_int_reg <= NwDat_int; - if RXD = '1' and NwDat_int = '1' then - receive <= '0'; - elsif RXD = '0' then - receive <= '1'; + if(reset ='0')then + Take <= '0'; + + elsif(clk'event and clk ='1')then + Taken_reg <= Taken; + + if(RXD ='0' and Taken ='1')then + Take <= '1'; + elsif(Taken ='0')then + Take <= '0'; end if; - if NwDat_int_reg = '0' and NwDat_int = '1' then - NwDat <= '1'; - RDATA <= RDATA_int(8 downto 1); - elsif ack = '1' then - NwDat <= '0'; + + if (Taken_reg ='0' and Taken ='1') then + RDATA <= RDATA_int(8 downto 1); end if; + end if; end process; -end ar_UART; +end architecture; - diff --git a/lib/lpp/lpp_uart/lpp_uart.vhd b/lib/lpp/lpp_uart/lpp_uart.vhd --- a/lib/lpp/lpp_uart/lpp_uart.vhd +++ b/lib/lpp/lpp_uart/lpp_uart.vhd @@ -41,25 +41,24 @@ port( Send : in std_logic; --! Flag, Demande d'envoi sur le bus Sended : out std_logic; --! Flag, Envoi termine BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission - RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur + RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur ); end component; -component Shift_REG is -generic(Data_sz : integer := 10); +component Shift_Reg is +generic( + Data_sz : integer := 10 --! Width of the shift register +); port( - clk : in std_logic; - Sclk : in std_logic; - reset : in std_logic; - SIN : in std_logic; - SOUT : out std_logic; - Serialize : in std_logic; - Serialized : out std_logic; - D : in std_logic_vector(Data_sz-1 downto 0); - Q : out std_logic_vector(Data_sz-1 downto 0) - + Sclk : in std_logic; --! Serial clock + SIN : in std_logic; --! Serial data in + SOUT : out std_logic; --! Serial data out + Serialize : in std_logic; --! Launch serialization + Serialized : out std_logic; --! Serialization complete + D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out + Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data ); end component;