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APB_MATRIX, second version /!\ not stable /!\
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity GetResult is
27 generic(
28 Result_SZ : integer := 32);
29 port(
30 clk : in std_logic;
31 raz : in std_logic;
32 Valid : in std_logic;
33 Conjugate : in std_logic;
34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 Received : out std_logic;
36 Result : out std_logic_vector(Result_SZ-1 downto 0)
37 );
38 end GetResult;
39
40
41 architecture ar_GetResult of GetResult is
42
43 signal Valid_reg : std_logic;
44
45 type state is (st0,st1);
46 signal ect : state;
47
48 begin
49 process(clk,raz)
50 begin
51
52 if(raz='0')then
53 Received <= '0';
54 Valid_reg <= '0';
55 ect <= st0;
56 Result <= (others => '0');
57
58 elsif(clk'event and clk='1')then
59 Valid_reg <= Valid;
60
61 case ect is
62 when st0 =>
63 Received <= '0';
64 if(Valid_reg='0' and Valid='1')then
65 Result <= Res;
66 if(Conjugate='1')then
67 Received <= '1';
68 ect <= st0;
69 else
70 ect <= st1;
71 end if;
72 end if;
73
74 when st1 =>
75 Received <= '1';
76 if(Valid_reg='0' and Valid='1')then
77 Result <= Res;
78 ect <= st0;
79 end if;
80
81 end case;
82 end if;
83 end process;
84
85 end ar_GetResult;
86
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity SelectInputs is
27 generic(
28 Input_SZ : integer := 16);
29 port(
30 clk : in std_logic;
31 raz : in std_logic;
32 Read : in std_logic;
33 B1 : in std_logic_vector(Input_SZ-1 downto 0);
34 B2 : in std_logic_vector(Input_SZ-1 downto 0);
35 B3 : in std_logic_vector(Input_SZ-1 downto 0);
36 E1 : in std_logic_vector(Input_SZ-1 downto 0);
37 E2 : in std_logic_vector(Input_SZ-1 downto 0);
38 Conjugate : out std_logic;
39 Take : out std_logic;
40 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
41 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
42 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
43 );
44 end SelectInputs;
45
46
47 architecture ar_SelectInputs of SelectInputs is
48
49 signal Read_reg : std_logic;
50 signal i : integer range 1 to 15;
51
52 type state is (stX,st1a,st1b);
53 signal ect : state;
54
55 begin
56 process(clk,raz)
57 begin
58
59 if(raz='0')then
60 Take <= '0';
61 i <= 0;
62 Read_reg <= '0';
63 ect <= stX;
64
65 elsif(clk'event and clk='1')then
66 Read_reg <= Read;
67
68 case ect is
69 when stX =>
70 i <= 1;
71 if(Read_reg='0' and Read='1')then
72 ect <= st1a;
73 end if;
74 -------------------------------------------------------------------------------
75 when st1a =>
76 Take <= '1';
77 if(Read_reg='0' and Read='1')then
78 ect <= st1b;
79 end if;
80
81 when st1b =>
82 Take <= '0';
83 if(i=15)then
84 ect <= stX;
85 elsif(Read_reg='0' and Read='1')then
86 i <= i+1;
87 ect <= st1a;
88 end if;
89 -------------------------------------------------------------------------------
90 -- when st2a =>
91 -- Take <= '1';
92 -- if(Read_reg='0' and Read='1')then
93 -- ect <= st2b;
94 -- end if;
95 --
96 -- when st2b =>
97 -- Take <= '0';
98 -- if(Read_reg='0' and Read='1')then
99 -- ect <= st3a;
100 -- end if;
101 ---------------------------------------------------------------------------------
102 -- when st3a =>
103 -- Take <= '1';
104 -- if(Read_reg='0' and Read='1')then
105 -- ect <= st3b;
106 -- end if;
107 --
108 -- when st3b =>
109 -- Take <= '0';
110 -- if(Read_reg='0' and Read='1')then
111 -- ect <= st4a;
112 -- end if;
113 ---------------------------------------------------------------------------------
114 -- when st4a =>
115 -- Take <= '1';
116 -- if(Read_reg='0' and Read='1')then
117 -- ect <= st4b;
118 -- end if;
119 --
120 -- when st4b =>
121 -- Take <= '0';
122 -- if(Read_reg='0' and Read='1')then
123 -- ect <= st5a;
124 -- end if;
125 ---------------------------------------------------------------------------------
126 --
127 -- when st5a =>
128 -- Take <= '1';
129 -- if(Read_reg='0' and Read='1')then
130 -- ect <= st5b;
131 -- end if;
132 --
133 -- when st5b =>
134 -- Take <= '0';
135 -- if(Read_reg='0' and Read='1')then
136 -- ect <= st6a;
137 -- end if;
138 ---------------------------------------------------------------------------------
139 -- when st6a =>
140 -- Take <= '1';
141 -- if(Read_reg='0' and Read='1')then
142 -- ect <= st6b;
143 -- end if;
144 --
145 -- when st6b =>
146 -- Take <= '0';
147 -- if(Read_reg='0' and Read='1')then
148 -- ect <= st7a;
149 -- end if;
150 ---------------------------------------------------------------------------------
151 -- when st7a =>
152 -- Take <= '1';
153 -- if(Read_reg='0' and Read='1')then
154 -- ect <= st7b;
155 -- end if;
156 --
157 -- when st7b =>
158 -- Take <= '0';
159 -- if(Read_reg='0' and Read='1')then
160 -- ect <= st8a;
161 -- end if;
162 ---------------------------------------------------------------------------------
163 -- when st8a =>
164 -- Take <= '1';
165 -- if(Read_reg='0' and Read='1')then
166 -- ect <= st8b;
167 -- end if;
168 --
169 -- when st8b =>
170 -- Take <= '0';
171 -- if(Read_reg='0' and Read='1')then
172 -- ect <= st9a;
173 -- end if;
174 ---------------------------------------------------------------------------------
175 -- when st9a =>
176 -- Take <= '1';
177 -- if(Read_reg='0' and Read='1')then
178 -- ect <= st9b;
179 -- end if;
180 --
181 -- when st9b =>
182 -- Take <= '0';
183 -- if(Read_reg='0' and Read='1')then
184 -- ect <= st10a;
185 -- end if;
186 ---------------------------------------------------------------------------------
187 -- when st10a =>
188 -- Take <= '1';
189 -- if(Read_reg='0' and Read='1')then
190 -- ect <= st10b;
191 -- end if;
192 --
193 -- when st10b =>
194 -- Take <= '0';
195 -- if(Read_reg='0' and Read='1')then
196 -- ect <= st11a;
197 -- end if;
198 ---------------------------------------------------------------------------------
199 -- when st11a =>
200 -- Take <= '1';
201 -- if(Read_reg='0' and Read='1')then
202 -- ect <= st11b;
203 -- end if;
204 --
205 -- when st11b =>
206 -- Take <= '0';
207 -- if(Read_reg='0' and Read='1')then
208 -- ect <= st12a;
209 -- end if;
210 ---------------------------------------------------------------------------------
211 -- when st12a =>
212 -- Take <= '1';
213 -- if(Read_reg='0' and Read='1')then
214 -- ect <= st12b;
215 -- end if;
216 --
217 -- when st12b =>
218 -- Take <= '0';
219 -- if(Read_reg='0' and Read='1')then
220 -- ect <= st13a;
221 -- end if;
222 ---------------------------------------------------------------------------------
223 -- when st13a =>
224 -- Take <= '1';
225 -- if(Read_reg='0' and Read='1')then
226 -- ect <= st13b;
227 -- end if;
228 --
229 -- when st13b =>
230 -- Take <= '0';
231 -- if(Read_reg='0' and Read='1')then
232 -- ect <= st14a;
233 -- end if;
234 ---------------------------------------------------------------------------------
235 -- when st14a =>
236 -- Take <= '1';
237 -- if(Read_reg='0' and Read='1')then
238 -- ect <= st14b;
239 -- end if;
240 --
241 -- when st14b =>
242 -- Take <= '0';
243 -- if(Read_reg='0' and Read='1')then
244 -- ect <= st15a;
245 -- end if;
246 ---------------------------------------------------------------------------------
247 -- when st15a =>
248 -- Take <= '1';
249 -- if(Read_reg='0' and Read='1')then
250 -- ect <= st7_b;
251 -- end if;
252 --
253 -- when st15b =>
254 -- Take <= '0';
255 -- if(Read_reg='0' and Read='1')then
256 -- ect <= stX;
257 -- end if;
258 -------------------------------------------------------------------------------
259 end case;
260 end if;
261 end process;
262
263 with i select
264 ReadFIFO <= "10000" when 1,
265 "11000" when 2,
266 "01000" when 3,
267 "10100" when 4,
268 "01100" when 5,
269 "00100" when 6,
270 "10010" when 7,
271 "01010" when 8,
272 "00110" when 9,
273 "00010" when 10,
274 "10001" when 11,
275 "01001" when 12,
276 "00101" when 13,
277 "00011" when 14,
278 "00001" when 15,
279 "00000" when others;
280
281 --with ect select
282 -- ReadB2 <= Read when st1,
283 -- Read when st2,
284 -- Read when st4,
285 -- Read when st7,
286 -- Read when st11,
287 -- '0' when others;
288 --
289 --with ect select
290 -- ReadB3 <= Read when st3,
291 -- Read when st4,
292 -- Read when st5,
293 -- Read when st8,
294 -- Read when st12,
295 -- '0' when others;
296 --
297 --with ect select
298 -- ReadE1 <= Read when st6,
299 -- Read when st7,
300 -- Read when st8,
301 -- Read when st9,
302 -- Read when st13,
303 -- '0' when others;
304 --
305 --with ect select
306 -- ReadE2 <= Read when st10,
307 -- Read when st11,
308 -- Read when st12,
309 -- Read when st13,
310 -- Read when st14,
311 -- '0' when others;
312
313 with i select
314 OP1 <= B1 when 1,
315 B1 when 2,
316 B1 when 4,
317 B1 when 7,
318 B1 when 11,
319 B2 when 3,
320 B2 when 5,
321 B2 when 8,
322 B2 when 12,
323 B3 when 6,
324 B3 when 9,
325 B3 when 13,
326 E1 when 10,
327 E1 when 14,
328 E2 when 15,
329 X"FFFF" when others;
330
331 with i select
332 OP2 <= B1 when 1,
333 B2 when 2,
334 B2 when 3,
335 B3 when 4,
336 B3 when 5,
337 B3 when 6,
338 E1 when 7,
339 E1 when 8,
340 E1 when 9,
341 E1 when 10,
342 E2 when 11,
343 E2 when 12,
344 E2 when 13,
345 E2 when 14,
346 E2 when 15,
347 X"FFFF" when others;
348
349 with i select
350 Conjugate <= '1' when 1,
351 '1' when 3,
352 '1' when 6,
353 '1' when 10,
354 '1' when 15,
355 '0' when others;
356
357
358 --RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1;
359 end ar_SelectInputs; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity SpectralMatrix is
28 generic(
29 Input_SZ : integer := 16;
30 Result_SZ : integer := 32);
31 port(
32 clk : in std_logic;
33 reset : in std_logic;
34 B1 : in std_logic_vector(Input_SZ-1 downto 0);
35 B2 : in std_logic_vector(Input_SZ-1 downto 0);
36 B3 : in std_logic_vector(Input_SZ-1 downto 0);
37 E1 : in std_logic_vector(Input_SZ-1 downto 0);
38 E2 : in std_logic_vector(Input_SZ-1 downto 0);
39 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
40 Result : out std_logic_vector(Result_SZ-1 downto 0)
41 );
42 end SpectralMatrix;
43
44
45 architecture ar_SpectralMatrix of SpectralMatrix is
46
47 signal Read : std_logic;
48 signal Take : std_logic;
49 signal Received : std_logic;
50 signal Valid : std_logic;
51 signal Conjugate : std_logic;
52 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
53 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
54 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
55
56 begin
57
58
59 IN0 : SelectInputs
60 generic map(Input_SZ)
61 port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2);
62
63
64 CALC0 : Matrix
65 generic map(Input_SZ)
66 port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat);
67
68
69 RES0 : GetResult
70 generic map(Result_SZ)
71 port map(clk,reset,Valid,Conjugate,Resultat,Received,Result);
72
73
74 end ar_SpectralMatrix; No newline at end of file
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 --! Driver de l'ALU
26 --! Driver de l'ALU
27
27
28 entity ALU_Driver is
28 entity ALU_Driver is
29 generic(
29 generic(
30 Input_SZ_1 : integer := 16;
30 Input_SZ_1 : integer := 16;
31 Input_SZ_2 : integer := 16);
31 Input_SZ_2 : integer := 16);
32 port(
32 port(
33 clk : in std_logic; --! Horloge du composant
33 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
34 reset : in std_logic; --! Reset general du composant
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
35 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
36 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donn�e d'entr�e
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
37 Take : in std_logic; --! Flag, op�rande r�cup�r�
38 Received : in std_logic; --! Flag, R�sultat bien ressu
38 Received : in std_logic; --! Flag, R�sultat bien ressu
39 Valid : out std_logic; --! Flag, R�sultat disponible
39 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
40 Read : out std_logic; --! Flag, op�rande disponible
40 Valid : out std_logic; --! Flag, R�sultat disponible
41 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
41 Read : out std_logic; --! Flag, op�rande disponible
42 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
42 CTRL : out std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
43 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
43 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
44 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Op�rande
44 );
45 );
45 end ALU_Driver;
46 end ALU_Driver;
46
47
47 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
48 --! @details Les op�randes sont issue des donn�es d'entr�es et associ� aux bonnes valeurs sur CTRL, les diff�rentes op�rations sont effectu�es
48
49
49 architecture ar_ALU_Driver of ALU_Driver is
50 architecture ar_ALU_Driver of ALU_Driver is
50
51
51 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
52 signal OP1re : std_logic_vector(Input_SZ_1-1 downto 0);
52 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
53 signal OP1im : std_logic_vector(Input_SZ_1-1 downto 0);
53 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
54 signal OP2re : std_logic_vector(Input_SZ_2-1 downto 0);
54 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
55 signal OP2im : std_logic_vector(Input_SZ_2-1 downto 0);
55
56
56 signal go_st : std_logic;
57 signal go_st : std_logic;
57 signal Take_reg : std_logic;
58 signal Take_reg : std_logic;
58 signal Received_reg : std_logic;
59 signal Received_reg : std_logic;
59
60
60 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
61 type etat is (eX,e0,e1,e2,e3,e4,e5,idle,idle2,idle3);
61 signal ect : etat;
62 signal ect : etat;
62 signal st : etat;
63 signal st : etat;
63
64
64 begin
65 begin
65 process(clk,reset)
66 process(clk,reset)
66 begin
67 begin
67
68
68 if(reset='0')then
69 if(reset='0')then
69 ect <= eX;
70 ect <= eX;
70 st <= e0;
71 st <= e0;
71 go_st <= '0';
72 go_st <= '0';
72 CTRL <= "10000";
73 CTRL <= "10000";
73 Read <= '0';
74 Read <= '0';
74 Valid <= '0';
75 Valid <= '0';
75 Take_reg <= '0';
76 Take_reg <= '0';
76 Received_reg <= '0';
77 Received_reg <= '0';
77
78
78 elsif(clk'event and clk='1')then
79 elsif(clk'event and clk='1')then
79 Take_reg <= Take;
80 Take_reg <= Take;
80 Received_reg <= Received;
81 Received_reg <= Received;
81
82
82 case ect is
83 case ect is
83 when eX =>
84 when eX =>
84 go_st <= '0';
85 go_st <= '0';
85 Read <= '1';
86 Read <= '1';
86 CTRL <= "10000";
87 CTRL <= "10000";
87 ect <= e0;
88 ect <= e0;
88
89
89 when e0 =>
90 when e0 =>
90 OP1re <= IN1;
91 OP1re <= IN1;
91 OP2re <= IN2;
92 OP2re <= IN2;
92 if(Take_reg='0' and Take='1')then
93 if(Take_reg='0' and Take='1')then
93 read <= '0';
94 read <= '0';
94 ect <= e1;
95 ect <= e1;
95 end if;
96 end if;
96
97
97 when e1 =>
98 when e1 =>
98 OP1 <= OP1re;
99 OP1 <= OP1re;
99 OP2 <= OP2re;
100 OP2 <= OP2re;
100 CTRL <= "00001";
101 CTRL <= "00001";
101 Read <= '1';
102 Read <= '1';
102 ect <= idle;
103 ect <= idle;
103
104
104 when idle =>
105 when idle =>
105 OP1im <= IN1;
106 OP1im <= IN1;
106 OP2im <= IN2;
107 OP2im <= IN2;
107 CTRL <= "00000";
108 CTRL <= "00000";
108 if(Take_reg='1' and Take='0')then
109 if(Take_reg='1' and Take='0')then
109 Read <= '0';
110 Read <= '0';
110 ect <= e2;
111 ect <= e2;
111 end if;
112 end if;
112
113
113 when e2 =>
114 when e2 =>
114 OP1 <= OP1im;
115 OP1 <= OP1im;
115 OP2 <= OP2im;
116 OP2 <= OP2im;
116 CTRL <= "00001";
117 CTRL <= "00001";
117 ect <= idle2;
118 ect <= idle2;
118
119
119 when idle2 =>
120 when idle2 =>
120 CTRL <= "00000";
121 CTRL <= "00000";
121 go_st <= '1';
122 go_st <= '1';
122 if(Received_reg='0' and Received='1')then
123 if(Received_reg='0' and Received='1')then
123 ect <= e3;
124 if(Conjugate='1')then
125 ect <= eX;
126 else
127 ect <= e3;
128 end if;
124 end if;
129 end if;
125
130
126 when e3 =>
131 when e3 =>
127 CTRL <= "10000";
132 CTRL <= "10000";
128 go_st <= '0';
133 go_st <= '0';
129 ect <= e4;
134 ect <= e4;
130
135
131 when e4 =>
136 when e4 =>
132 OP1 <= OP1im;
137 OP1 <= OP1im;
133 OP2 <= OP2re;
138 OP2 <= OP2re;
134 CTRL <= "00001";
139 CTRL <= "00001";
135 ect <= e5;
140 ect <= e5;
136
141
137 when e5 =>
142 when e5 =>
138 OP1 <= OP1re;
143 OP1 <= OP1re;
139 OP2 <= OP2im;
144 OP2 <= OP2im;
140 CTRL <= "01001";
145 CTRL <= "01001";
141 ect <= idle3;
146 ect <= idle3;
142
147
143 when idle3 =>
148 when idle3 =>
144 CTRL <= "00000";
149 CTRL <= "00000";
145 go_st <= '1';
150 go_st <= '1';
146 if(Received_reg='1' and Received='0')then
151 if(Received_reg='1' and Received='0')then
147 ect <= eX;
152 ect <= eX;
148 end if;
153 end if;
149 end case;
154 end case;
150
155 ---------------------------------------------------------------------------------
151 case st is
156 case st is
152 when e0 =>
157 when e0 =>
153 if(go_st='1')then
158 if(go_st='1')then
154 st <= e1;
159 st <= e1;
155 end if;
160 end if;
156
161
157 when e1 =>
162 when e1 =>
158 Valid <= '1';
163 Valid <= '1';
159 st <= e2;
164 st <= e2;
160
165
161 when e2 =>
166 when e2 =>
162 if(Received_reg='0' and Received='1')then
167 if(Received_reg='0' and Received='1')then
163 Valid <= '0';
168 Valid <= '0';
164 st <= idle;
169 if(Conjugate='1')then
170 st <= idle2;
171 else
172 st <= idle;
173 end if;
165 end if;
174 end if;
166
175
167 when idle =>
176 when idle =>
168 st <= e3;
177 st <= e3;
169
178
170 when e3 =>
179 when e3 =>
171 if(go_st='1')then
180 if(go_st='1')then
172 st <= e4;
181 st <= e4;
173 end if;
182 end if;
174
183
175 when e4 =>
184 when e4 =>
176 Valid <= '1';
185 Valid <= '1';
177 st <= e5;
186 st <= e5;
178
187
179 when e5 =>
188 when e5 =>
180 if(Received_reg='1' and Received='0')then
189 if(Received_reg='1' and Received='0')then
181 Valid <= '0';
190 Valid <= '0';
182 st <= idle2;
191 st <= idle2;
183 end if;
192 end if;
184
193
185 when idle2 =>
194 when idle2 =>
186 st <= e0;
195 st <= e0;
187
196
188 when others =>
197 when others =>
189 null;
198 null;
190 end case;
199 end case;
191
200
192 end if;
201 end if;
193 end process;
202 end process;
194
203
195 end ar_ALU_Driver; No newline at end of file
204 end ar_ALU_Driver;
Show file before | Show file after | Hide comments
@@ -1,66 +1,67
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
25
26
26 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
27 --! Une ALU : Arithmetic and logical unit, permettant de r�aliser une ou plusieurs op�ration
27
28
28 entity ALU_v2 is
29 entity ALU_v2 is
29 generic(
30 generic(
30 Arith_en : integer := 1;
31 Arith_en : integer := 1;
31 Logic_en : integer := 1;
32 Logic_en : integer := 1;
32 Input_SZ_1 : integer := 16;
33 Input_SZ_1 : integer := 16;
33 Input_SZ_2 : integer := 9);
34 Input_SZ_2 : integer := 9);
34 port(
35 port(
35 clk : in std_logic; --! Horloge du composant
36 clk : in std_logic; --! Horloge du composant
36 reset : in std_logic; --! Reset general du composant
37 reset : in std_logic; --! Reset general du composant
37 ctrl : in std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
38 ctrl : in std_logic_vector(4 downto 0); --! Permet de s�lectionner la/les op�ration d�sir�e
38 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
39 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Op�rande
39 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
40 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Second Op�rande
40 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
41 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0) --! R�sultat de l'op�ration
41 );
42 );
42 end ALU_v2;
43 end ALU_v2;
43
44
44 --! @details S�lection grace a l'entr�e "ctrl" :
45 --! @details S�lection grace a l'entr�e "ctrl" :
45 --! Pause : IDLE = 00000
46 --! Pause : IDLE = 00000
46 --! Multiplieur/Accumulateur : MAC = 0XX01
47 --! Multiplieur/Accumulateur : MAC = 0XX01
47 --! Multiplication : MULT = 0XX10
48 --! Multiplication : MULT = 0XX10
48 --! Addition : ADD = 0XX11
49 --! Addition : ADD = 0XX11
49 --! Complement a 2 : 2C = 011XX
50 --! Complement a 2 : 2C = 011XX
50 --! Reset du MAC : CLRMAC = 10000
51 --! Reset du MAC : CLRMAC = 10000
51
52
52 architecture ar_ALU_v2 of ALU_v2 is
53 architecture ar_ALU_v2 of ALU_v2 is
53
54
54 signal clr_MAC : std_logic:='1';
55 signal clr_MAC : std_logic:='1';
55
56
56 begin
57 begin
57
58
58 clr_MAC <= '1' when ctrl = "10000" else '0';
59 clr_MAC <= '1' when ctrl = "10000" else '0';
59
60
60 arith : if Arith_en = 1 generate
61 arith : if Arith_en = 1 generate
61 MACinst : entity work.MAC_v2
62 MACinst : MAC_v2
62 generic map(Input_SZ_1,Input_SZ_2)
63 generic map(Input_SZ_1,Input_SZ_2)
63 port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES);
64 port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES);
64 end generate;
65 end generate;
65
66
66 end ar_ALU_v2; No newline at end of file
67 end ar_ALU_v2;
Show file before | Show file after | Hide comments
@@ -1,308 +1,310
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26 use lpp.general_purpose.all;
25
27
26 --! Un MAC : Multiplier Accumulator Chip
28 --! Un MAC : Multiplier Accumulator Chip
27
29
28 entity MAC_v2 is
30 entity MAC_v2 is
29 generic(
31 generic(
30 Input_SZ_A : integer := 8;
32 Input_SZ_A : integer := 8;
31 Input_SZ_B : integer := 8);
33 Input_SZ_B : integer := 8);
32 port(
34 port(
33 clk : in std_logic; --! Horloge du composant
35 clk : in std_logic; --! Horloge du composant
34 reset : in std_logic; --! Reset general du composant
36 reset : in std_logic; --! Reset general du composant
35 clr_MAC : in std_logic; --! Un reset sp�cifique au programme
37 clr_MAC : in std_logic; --! Un reset sp�cifique au programme
36 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); --! Permet de s�lectionner la/les fonctionnalit� d�sir�
38 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0); --! Permet de s�lectionner la/les fonctionnalit� d�sir�
37 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); --! Premier Op�rande
39 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0); --! Premier Op�rande
38 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); --! Second Op�rande
40 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0); --! Second Op�rande
39 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) --! R�sultat du MAC
41 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0) --! R�sultat du MAC
40 );
42 );
41 end MAC_v2;
43 end MAC_v2;
42
44
43
45
44 architecture ar_MAC_v2 of MAC_v2 is
46 architecture ar_MAC_v2 of MAC_v2 is
45
47
46
48
47 signal add,mult : std_logic;
49 signal add,mult : std_logic;
48 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
50 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
49
51
50 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
51 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
53 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
52 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
54 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
53
55
54 signal MACMUXsel : std_logic;
56 signal MACMUXsel : std_logic;
55 signal OP1_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
57 signal OP1_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
56 signal OP2_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
58 signal OP2_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
57
59
58 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
60 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
59 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
61 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
60
62
61 signal MACMUX2sel : std_logic;
63 signal MACMUX2sel : std_logic;
62
64
63 signal add_D : std_logic;
65 signal add_D : std_logic;
64 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
66 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
65 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
67 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
66 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
68 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
67 signal MACMUXsel_D : std_logic;
69 signal MACMUXsel_D : std_logic;
68 signal MACMUX2sel_D : std_logic;
70 signal MACMUX2sel_D : std_logic;
69 signal MACMUX2sel_D_D : std_logic;
71 signal MACMUX2sel_D_D : std_logic;
70 signal clr_MAC_D : std_logic;
72 signal clr_MAC_D : std_logic;
71 signal clr_MAC_D_D : std_logic;
73 signal clr_MAC_D_D : std_logic;
72 signal MAC_MUL_ADD_2C_D : std_logic_vector(3 downto 0);
74 signal MAC_MUL_ADD_2C_D : std_logic_vector(3 downto 0);
73
75
74
76
75 begin
77 begin
76
78
77
79
78
80
79 --==============================================================
81 --==============================================================
80 --=============M A C C O N T R O L E R=========================
82 --=============M A C C O N T R O L E R=========================
81 --==============================================================
83 --==============================================================
82 MAC_CONTROLER1 : entity work.MAC_CONTROLER
84 MAC_CONTROLER1 : MAC_CONTROLER
83 port map(
85 port map(
84 ctrl => MAC_MUL_ADD_2C_D(1 downto 0),
86 ctrl => MAC_MUL_ADD_2C_D(1 downto 0),
85 MULT => mult,
87 MULT => mult,
86 ADD => add,
88 ADD => add,
87 MACMUX_sel => MACMUXsel,
89 MACMUX_sel => MACMUXsel,
88 MACMUX2_sel => MACMUX2sel
90 MACMUX2_sel => MACMUX2sel
89
91
90 );
92 );
91 --==============================================================
93 --==============================================================
92
94
93
95
94
96
95
97
96 --==============================================================
98 --==============================================================
97 --=============M U L T I P L I E R==============================
99 --=============M U L T I P L I E R==============================
98 --==============================================================
100 --==============================================================
99 Multiplieri_nst : entity work.Multiplier
101 Multiplieri_nst : Multiplier
100 generic map(
102 generic map(
101 Input_SZ_A => Input_SZ_A,
103 Input_SZ_A => Input_SZ_A,
102 Input_SZ_B => Input_SZ_B
104 Input_SZ_B => Input_SZ_B
103 )
105 )
104 port map(
106 port map(
105 clk => clk,
107 clk => clk,
106 reset => reset,
108 reset => reset,
107 mult => mult,
109 mult => mult,
108 OP1 => OP1_2C,
110 OP1 => OP1_2C,
109 OP2 => OP2_2C,
111 OP2 => OP2_2C,
110 RES => MULTout
112 RES => MULTout
111 );
113 );
112
114
113 --==============================================================
115 --==============================================================
114
116
115
117
116
118
117
119
118 --==============================================================
120 --==============================================================
119 --======================A D D E R ==============================
121 --======================A D D E R ==============================
120 --==============================================================
122 --==============================================================
121 adder_inst : entity work.Adder
123 adder_inst : Adder
122 generic map(
124 generic map(
123 Input_SZ_A => Input_SZ_A+Input_SZ_B,
125 Input_SZ_A => Input_SZ_A+Input_SZ_B,
124 Input_SZ_B => Input_SZ_A+Input_SZ_B
126 Input_SZ_B => Input_SZ_A+Input_SZ_B
125 )
127 )
126 port map(
128 port map(
127 clk => clk,
129 clk => clk,
128 reset => reset,
130 reset => reset,
129 clr => clr_MAC_D_D,
131 clr => clr_MAC_D_D,
130 add => add_D,
132 add => add_D,
131 OP1 => ADDERinA,
133 OP1 => ADDERinA,
132 OP2 => ADDERinB,
134 OP2 => ADDERinB,
133 RES => ADDERout
135 RES => ADDERout
134 );
136 );
135
137
136 --==============================================================
138 --==============================================================
137
139
138
140
139
141
140
142
141 --==============================================================
143 --==============================================================
142 --===================TWO COMPLEMENTERS==========================
144 --===================TWO COMPLEMENTERS==========================
143 --==============================================================
145 --==============================================================
144 TWO_COMPLEMENTER1 : entity work.TwoComplementer
146 TWO_COMPLEMENTER1 : TwoComplementer
145 generic map(
147 generic map(
146 Input_SZ => Input_SZ_A
148 Input_SZ => Input_SZ_A
147 )
149 )
148 port map(
150 port map(
149 clk => clk,
151 clk => clk,
150 reset => reset,
152 reset => reset,
151 clr => clr_MAC,
153 clr => clr_MAC,
152 TwoComp => MAC_MUL_ADD_2C(2),
154 TwoComp => MAC_MUL_ADD_2C(2),
153 OP => OP1,
155 OP => OP1,
154 RES => OP1_2C
156 RES => OP1_2C
155 );
157 );
156
158
157
159
158 TWO_COMPLEMENTER2 : entity work.TwoComplementer
160 TWO_COMPLEMENTER2 : TwoComplementer
159 generic map(
161 generic map(
160 Input_SZ => Input_SZ_B
162 Input_SZ => Input_SZ_B
161 )
163 )
162 port map(
164 port map(
163 clk => clk,
165 clk => clk,
164 reset => reset,
166 reset => reset,
165 clr => clr_MAC,
167 clr => clr_MAC,
166 TwoComp => MAC_MUL_ADD_2C(3),
168 TwoComp => MAC_MUL_ADD_2C(3),
167 OP => OP2,
169 OP => OP2,
168 RES => OP2_2C
170 RES => OP2_2C
169 );
171 );
170 --==============================================================
172 --==============================================================
171
173
172 CTRL : entity work.MAC_REG
174 CTRL : MAC_REG
173 generic map(size => 2)
175 generic map(size => 2)
174 port map(
176 port map(
175 reset => reset,
177 reset => reset,
176 clk => clk,
178 clk => clk,
177 D => MAC_MUL_ADD_2C(1 downto 0),
179 D => MAC_MUL_ADD_2C(1 downto 0),
178 Q => MAC_MUL_ADD_2C_D(1 downto 0)
180 Q => MAC_MUL_ADD_2C_D(1 downto 0)
179 );
181 );
180
182
181 clr_MACREG1 : entity work.MAC_REG
183 clr_MACREG1 : MAC_REG
182 generic map(size => 1)
184 generic map(size => 1)
183 port map(
185 port map(
184 reset => reset,
186 reset => reset,
185 clk => clk,
187 clk => clk,
186 D(0) => clr_MAC,
188 D(0) => clr_MAC,
187 Q(0) => clr_MAC_D
189 Q(0) => clr_MAC_D
188 );
190 );
189
191
190 clr_MACREG2 : entity work.MAC_REG
192 clr_MACREG2 : MAC_REG
191 generic map(size => 1)
193 generic map(size => 1)
192 port map(
194 port map(
193 reset => reset,
195 reset => reset,
194 clk => clk,
196 clk => clk,
195 D(0) => clr_MAC_D,
197 D(0) => clr_MAC_D,
196 Q(0) => clr_MAC_D_D
198 Q(0) => clr_MAC_D_D
197 );
199 );
198
200
199 addREG : entity work.MAC_REG
201 addREG : MAC_REG
200 generic map(size => 1)
202 generic map(size => 1)
201 port map(
203 port map(
202 reset => reset,
204 reset => reset,
203 clk => clk,
205 clk => clk,
204 D(0) => add,
206 D(0) => add,
205 Q(0) => add_D
207 Q(0) => add_D
206 );
208 );
207
209
208
210
209 OP1REG : entity work.MAC_REG
211 OP1REG : MAC_REG
210 generic map(size => Input_SZ_A)
212 generic map(size => Input_SZ_A)
211 port map(
213 port map(
212 reset => reset,
214 reset => reset,
213 clk => clk,
215 clk => clk,
214 D => OP1_2C,
216 D => OP1_2C,
215 Q => OP1_2C_D
217 Q => OP1_2C_D
216 );
218 );
217
219
218
220
219 OP2REG : entity work.MAC_REG
221 OP2REG : MAC_REG
220 generic map(size => Input_SZ_B)
222 generic map(size => Input_SZ_B)
221 port map(
223 port map(
222 reset => reset,
224 reset => reset,
223 clk => clk,
225 clk => clk,
224 D => OP2_2C,
226 D => OP2_2C,
225 Q => OP2_2C_D
227 Q => OP2_2C_D
226 );
228 );
227
229
228
230
229 MULToutREG : entity work.MAC_REG
231 MULToutREG : MAC_REG
230 generic map(size => Input_SZ_A+Input_SZ_B)
232 generic map(size => Input_SZ_A+Input_SZ_B)
231 port map(
233 port map(
232 reset => reset,
234 reset => reset,
233 clk => clk,
235 clk => clk,
234 D => MULTout,
236 D => MULTout,
235 Q => MULTout_D
237 Q => MULTout_D
236 );
238 );
237
239
238
240
239 MACMUXselREG : entity work.MAC_REG
241 MACMUXselREG : MAC_REG
240 generic map(size => 1)
242 generic map(size => 1)
241 port map(
243 port map(
242 reset => reset,
244 reset => reset,
243 clk => clk,
245 clk => clk,
244 D(0) => MACMUXsel,
246 D(0) => MACMUXsel,
245 Q(0) => MACMUXsel_D
247 Q(0) => MACMUXsel_D
246 );
248 );
247
249
248
250
249
251
250 MACMUX2selREG : entity work.MAC_REG
252 MACMUX2selREG : MAC_REG
251 generic map(size => 1)
253 generic map(size => 1)
252 port map(
254 port map(
253 reset => reset,
255 reset => reset,
254 clk => clk,
256 clk => clk,
255 D(0) => MACMUX2sel,
257 D(0) => MACMUX2sel,
256 Q(0) => MACMUX2sel_D
258 Q(0) => MACMUX2sel_D
257 );
259 );
258
260
259
261
260 MACMUX2selREG2 : entity work.MAC_REG
262 MACMUX2selREG2 : MAC_REG
261 generic map(size => 1)
263 generic map(size => 1)
262 port map(
264 port map(
263 reset => reset,
265 reset => reset,
264 clk => clk,
266 clk => clk,
265 D(0) => MACMUX2sel_D,
267 D(0) => MACMUX2sel_D,
266 Q(0) => MACMUX2sel_D_D
268 Q(0) => MACMUX2sel_D_D
267 );
269 );
268
270
269
271
270 --==============================================================
272 --==============================================================
271 --======================M A C M U X ===========================
273 --======================M A C M U X ===========================
272 --==============================================================
274 --==============================================================
273 MACMUX_inst : entity work.MAC_MUX
275 MACMUX_inst : MAC_MUX
274 generic map(
276 generic map(
275 Input_SZ_A => Input_SZ_A+Input_SZ_B,
277 Input_SZ_A => Input_SZ_A+Input_SZ_B,
276 Input_SZ_B => Input_SZ_A+Input_SZ_B
278 Input_SZ_B => Input_SZ_A+Input_SZ_B
277
279
278 )
280 )
279 port map(
281 port map(
280 sel => MACMUXsel_D,
282 sel => MACMUXsel_D,
281 INA1 => ADDERout,
283 INA1 => ADDERout,
282 INA2 => OP2_Resz,
284 INA2 => OP2_Resz,
283 INB1 => MULTout,
285 INB1 => MULTout,
284 INB2 => OP1_Resz,
286 INB2 => OP1_Resz,
285 OUTA => ADDERinA,
287 OUTA => ADDERinA,
286 OUTB => ADDERinB
288 OUTB => ADDERinB
287 );
289 );
288 OP1_Resz <= std_logic_vector(resize(signed(OP1_2C_D),Input_SZ_A+Input_SZ_B));
290 OP1_Resz <= std_logic_vector(resize(signed(OP1_2C_D),Input_SZ_A+Input_SZ_B));
289 OP2_Resz <= std_logic_vector(resize(signed(OP2_2C_D),Input_SZ_A+Input_SZ_B));
291 OP2_Resz <= std_logic_vector(resize(signed(OP2_2C_D),Input_SZ_A+Input_SZ_B));
290 --==============================================================
292 --==============================================================
291
293
292
294
293 --==============================================================
295 --==============================================================
294 --======================M A C M U X2 ==========================
296 --======================M A C M U X2 ==========================
295 --==============================================================
297 --==============================================================
296 MAC_MUX2_inst : entity work.MAC_MUX2
298 MAC_MUX2_inst : MAC_MUX2
297 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
299 generic map(Input_SZ => Input_SZ_A+Input_SZ_B)
298 port map(
300 port map(
299 sel => MACMUX2sel_D_D,
301 sel => MACMUX2sel_D_D,
300 RES2 => MULTout_D,
302 RES2 => MULTout_D,
301 RES1 => ADDERout,
303 RES1 => ADDERout,
302 RES => RES
304 RES => RES
303 );
305 );
304
306
305
307
306 --==============================================================
308 --==============================================================
307
309
308 end ar_MAC_v2;
310 end ar_MAC_v2;
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@@ -1,64 +1,65
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.numeric_std.all;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
24 use IEEE.std_logic_1164.all;
25
25
26 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
26 --! Programme de calcule de Matrice Spectral, compos� d'une ALU et de son Driver
27
27
28 entity Matrix is
28 entity Matrix is
29 generic(
29 generic(
30 Input_SZ : integer := 16);
30 Input_SZ : integer := 16);
31 port(
31 port(
32 clk : in std_logic; --! Horloge du composant
32 clk : in std_logic; --! Horloge du composant
33 raz : in std_logic; --! Reset general du composant
33 raz : in std_logic; --! Reset general du composant
34 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
34 IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
35 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
35 IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donn�e d'entr�e
36 Take : in std_logic; --! Flag, op�rande r�cup�r�
36 Take : in std_logic; --! Flag, op�rande r�cup�r�
37 Received : in std_logic; --! Flag, R�sultat bien ressu
37 Received : in std_logic; --! Flag, R�sultat bien ressu
38 Valid : out std_logic; --! Flag, R�sultat disponible
38 Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugu�
39 Read : out std_logic; --! Flag, op�rande disponible
39 Valid : out std_logic; --! Flag, R�sultat disponible
40 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
40 Read : out std_logic; --! Flag, op�rande disponible
41 Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! R�sultat du calcul
41 );
42 );
42 end Matrix;
43 end Matrix;
43
44
44
45
45 architecture ar_Matrix of Matrix is
46 architecture ar_Matrix of Matrix is
46
47
47 signal CTRL : std_logic_vector(4 downto 0);
48 signal CTRL : std_logic_vector(4 downto 0);
48 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
49 signal OP1 : std_logic_vector(Input_SZ-1 downto 0);
49 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
50 signal OP2 : std_logic_vector(Input_SZ-1 downto 0);
50
51
51 begin
52 begin
52
53
53 DRIVE : entity work.ALU_Driver
54 DRIVE : entity work.ALU_Driver
54 generic map(Input_SZ,Input_SZ)
55 generic map(Input_SZ,Input_SZ)
55 port map(clk,raz,IN1,IN2,Take,Received,Valid,Read,CTRL,OP1,OP2);
56 port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2);
56
57
57
58
58 ALU : entity work.ALU_v2
59 ALU : entity work.ALU_v2
59 generic map(1,0,Input_SZ,Input_SZ)
60 generic map(1,0,Input_SZ,Input_SZ)
60 port map(clk,raz,CTRL,OP1,OP2,Result);
61 port map(clk,raz,CTRL,OP1,OP2,Result);
61
62
62
63
63 end ar_Matrix;
64 end ar_Matrix;
64
65
Show file before | Show file after | Hide comments
@@ -1,133 +1,189
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_matrix is
32 package lpp_matrix is
33
33
34 component APB_Matrix is
34 component APB_Matrix is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8);
40 abits : integer := 8);
41 port (
41 port (
42 clk : in std_logic; --! Horloge du composant
42 clk : in std_logic; --! Horloge du composant
43 rst : in std_logic; --! Reset general du composant
43 rst : in std_logic; --! Reset general du composant
44 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
44 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
45 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
45 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
46 );
46 );
47 end component;
47 end component;
48
48
49
49
50 component SpectralMatrix is
51 generic(
52 Input_SZ : integer := 16;
53 Result_SZ : integer := 32);
54 port(
55 clk : in std_logic;
56 reset : in std_logic;
57 B1 : in std_logic_vector(Input_SZ-1 downto 0);
58 B2 : in std_logic_vector(Input_SZ-1 downto 0);
59 B3 : in std_logic_vector(Input_SZ-1 downto 0);
60 E1 : in std_logic_vector(Input_SZ-1 downto 0);
61 E2 : in std_logic_vector(Input_SZ-1 downto 0);
62 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
63 Result : out std_logic_vector(Result_SZ-1 downto 0)
64 );
65 end component;
66
67
50 component Matrix is
68 component Matrix is
51 generic(
69 generic(
52 Input_SZ : integer := 16);
70 Input_SZ : integer := 16);
53 port(
71 port(
54 clk : in std_logic;
72 clk : in std_logic;
55 raz : in std_logic;
73 raz : in std_logic;
56 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
74 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
57 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
75 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
58 Take : in std_logic;
76 Take : in std_logic;
59 Received : in std_logic;
77 Received : in std_logic;
60 Valid : out std_logic;
78 Conjugate : in std_logic;
61 Read : out std_logic;
79 Valid : out std_logic;
62 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
80 Read : out std_logic;
81 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
63 );
82 );
64 end component;
83 end component;
65
84
66
85
67 component ALU_Driver is
86 component ALU_Driver is
68 generic(
87 generic(
69 Input_SZ_1 : integer := 16;
88 Input_SZ_1 : integer := 16;
70 Input_SZ_2 : integer := 16);
89 Input_SZ_2 : integer := 16);
71 port(
90 port(
72 clk : in std_logic;
91 clk : in std_logic;
73 reset : in std_logic;
92 reset : in std_logic;
74 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
93 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
75 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
94 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
76 Take : in std_logic;
95 Take : in std_logic;
77 Received : in std_logic;
96 Received : in std_logic;
78 Valid : out std_logic;
97 Conjugate : in std_logic;
79 Read : out std_logic;
98 Valid : out std_logic;
80 CTRL : out std_logic_vector(4 downto 0);
99 Read : out std_logic;
81 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
100 CTRL : out std_logic_vector(4 downto 0);
82 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
101 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
102 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
83 );
103 );
84 end component;
104 end component;
85
105
86
106
87 component ALU_v2 is
107 component ALU_v2 is
88 generic(
108 generic(
89 Arith_en : integer := 1;
109 Arith_en : integer := 1;
90 Logic_en : integer := 1;
110 Logic_en : integer := 1;
91 Input_SZ_1 : integer := 16;
111 Input_SZ_1 : integer := 16;
92 Input_SZ_2 : integer := 9);
112 Input_SZ_2 : integer := 9);
93 port(
113 port(
94 clk : in std_logic;
114 clk : in std_logic;
95 reset : in std_logic;
115 reset : in std_logic;
96 ctrl : in std_logic_vector(4 downto 0);
116 ctrl : in std_logic_vector(4 downto 0);
97 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
117 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
98 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
118 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
99 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
119 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
100 );
120 );
101 end component;
121 end component;
102
122
103
123
104 component MAC_v2 is
124 component MAC_v2 is
105 generic(
125 generic(
106 Input_SZ_A : integer := 8;
126 Input_SZ_A : integer := 8;
107 Input_SZ_B : integer := 8);
127 Input_SZ_B : integer := 8);
108 port(
128 port(
109 clk : in std_logic;
129 clk : in std_logic;
110 reset : in std_logic;
130 reset : in std_logic;
111 clr_MAC : in std_logic;
131 clr_MAC : in std_logic;
112 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
132 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
113 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
133 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
114 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
134 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
115 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
135 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
116 );
136 );
117 end component;
137 end component;
118
138
119
139
120 component TwoComplementer is
140 component TwoComplementer is
121 generic(
141 generic(
122 Input_SZ : integer := 16);
142 Input_SZ : integer := 16);
123 port(
143 port(
124 clk : in std_logic;
144 clk : in std_logic;
125 reset : in std_logic;
145 reset : in std_logic;
126 clr : in std_logic;
146 clr : in std_logic;
127 TwoComp : in std_logic;
147 TwoComp : in std_logic;
128 OP : in std_logic_vector(Input_SZ-1 downto 0);
148 OP : in std_logic_vector(Input_SZ-1 downto 0);
129 RES : out std_logic_vector(Input_SZ-1 downto 0)
149 RES : out std_logic_vector(Input_SZ-1 downto 0)
130 );
150 );
131 end component;
151 end component;
132
152
153
154 component GetResult is
155 generic(
156 Result_SZ : integer := 32);
157 port(
158 clk : in std_logic;
159 raz : in std_logic;
160 Valid : in std_logic;
161 Conjugate : in std_logic;
162 Res : in std_logic_vector(Result_SZ-1 downto 0);
163 Received : out std_logic;
164 Result : out std_logic_vector(Result_SZ-1 downto 0)
165 );
166 end component;
167
168
169 component SelectInputs is
170 generic(
171 Input_SZ : integer := 16);
172 port(
173 clk : in std_logic;
174 raz : in std_logic;
175 Read : in std_logic;
176 B1 : in std_logic_vector(Input_SZ-1 downto 0);
177 B2 : in std_logic_vector(Input_SZ-1 downto 0);
178 B3 : in std_logic_vector(Input_SZ-1 downto 0);
179 E1 : in std_logic_vector(Input_SZ-1 downto 0);
180 E2 : in std_logic_vector(Input_SZ-1 downto 0);
181 Conjugate : out std_logic;
182 Take : out std_logic;
183 ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2
184 OP1 : out std_logic_vector(Input_SZ-1 downto 0);
185 OP2 : out std_logic_vector(Input_SZ-1 downto 0)
186 );
187 end component;
188
133 end; No newline at end of file
189 end;
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@@ -1,80 +1,83
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoRead is
35 entity APB_FifoRead is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_WR : in std_logic; --! Demande l'�criture dans la m�moire, g�r� hors de l'IP
49 WriteEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'�criture dans la m�moire
50 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
52 );
53 end APB_FifoRead;
53 end APB_FifoRead;
54
54
55 --! @details Gestion de la FIFO uniquement en �criture
55 --! @details Gestion de la FIFO, �criture interne au FPGA, lecture via le bus APB
56
56
57 architecture ar_APB_FifoRead of APB_FifoRead is
57 architecture ar_APB_FifoRead of APB_FifoRead is
58
58
59 signal Low : std_logic:='0';
59 signal ReadEnable : std_logic;
60 signal ReadEnable : std_logic;
60 --signal WriteEnable : std_logic;
61 signal FlagEmpty : std_logic;
61 signal FlagEmpty : std_logic;
62 --signal FlagFull : std_logic;
62 signal FlagFull : std_logic;
63 signal ReUse : std_logic;
64 signal Lock : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
65 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
66 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 --signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
67 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
68 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
67
69
68 begin
70 begin
69
71
70 APB : ApbDriver
72 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
73 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo);
74 port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
73
75
74
76
75 MEMORY_READ : Top_FifoRead
77 FIFO : Top_FIFO
76 generic map(Data_sz,Addr_sz,addr_max_int)
78 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut);
79 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
78
80
81 DATA <= DataOut;
79
82
80 end ar_APB_FifoReade; No newline at end of file
83 end ar_APB_FifoRead; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,80 +1,83
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
31 use lpp.lpp_memory.all;
32
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
34
35 entity APB_FifoWrite is
35 entity APB_FifoWrite is
36 generic (
36 generic (
37 pindex : integer := 0;
37 pindex : integer := 0;
38 paddr : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
40 pirq : integer := 0;
41 abits : integer := 8;
41 abits : integer := 8;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
49 Flag_RE : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
49 ReadEnable : in std_logic; --! Demande de lecture de la m�moire, g�r� hors de l'IP
50 Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la m�moire
50 DATA : out std_logic_vector(Data_sz-1 downto 0); --! Donn�es en sortie de la m�moire
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
52 );
53 end APB_FifoWrite;
53 end APB_FifoWrite;
54
54
55 --! @details Gestion de la FIFO uniquement en lecture
55 --! @details Gestion de la FIFO, �criture via le bus APB, lecture interne au FPGA
56
56
57 architecture ar_APB_FifoWrite of APB_FifoWrite is
57 architecture ar_APB_FifoWrite of APB_FifoWrite is
58
58
59 --signal ReadEnable : std_logic;
59 signal Low : std_logic:='0';
60 signal WriteEnable : std_logic;
60 signal WriteEnable : std_logic;
61 --signal FlagEmpty : std_logic;
61 signal FlagEmpty : std_logic;
62 signal FlagFull : std_logic;
62 signal FlagFull : std_logic;
63 signal ReUse : std_logic;
64 signal Lock : std_logic;
63 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
65 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
64 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
66 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
65 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
67 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
66 --signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
68 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
67
69
68 begin
70 begin
69
71
70 APB : ApbDriver
72 APB : ApbDriver
71 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
73 generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int)
72 port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
74 port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
73
75
74
76
75 MEMORY_WRITE : Top_FifoWrite
77 FIFO : Top_FIFO
76 generic map(Data_sz,Addr_sz,addr_max_int)
78 generic map(Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut);
79 port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut);
78
80
81 DATA <= DataOut;
79
82
80 end ar_APB_FifoWrite; No newline at end of file
83 end ar_APB_FifoWrite;
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@@ -1,160 +1,165
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31
31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
33
33
34 entity ApbDriver is
34 entity ApbDriver is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
41 LPP_DEVICE : integer;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
51 FlagFull : in std_logic; --! Flag, M�moire pleine
51 FlagFull : in std_logic; --! Flag, M�moire pleine
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
52 ReUse : out std_logic; --! Flag, Permet de relire la m�moire du d�but
53 Lock : out std_logic; --! Flag, Permet de bloquer l'�criture dans la m�moire
53 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
54 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
54 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
55 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
55 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
56 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
56 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
57 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
57 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
58 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
58 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
59 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
59 );
60 );
60 end ApbDriver;
61 end ApbDriver;
61
62
62 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
63 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
63
64
64 architecture ar_ApbDriver of ApbDriver is
65 architecture ar_ApbDriver of ApbDriver is
65
66
66 constant REVISION : integer := 1;
67 constant REVISION : integer := 1;
67
68
68 constant pconfig : apb_config_type := (
69 constant pconfig : apb_config_type := (
69 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
70 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
70 1 => apb_iobar(paddr, pmask));
71 1 => apb_iobar(paddr, pmask));
71
72
72 type DEVICE_ctrlr_Reg is record
73 type DEVICE_ctrlr_Reg is record
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
74 DEVICE_Cfg : std_logic_vector(5 downto 0);
74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
77 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
77 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
78 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
78 end record;
79 end record;
79
80
80 signal Rec : DEVICE_ctrlr_Reg;
81 signal Rec : DEVICE_ctrlr_Reg;
81 signal Rdata : std_logic_vector(31 downto 0);
82 signal Rdata : std_logic_vector(31 downto 0);
82
83
83 signal FlagRE : std_logic;
84 signal FlagRE : std_logic;
84 signal FlagWR : std_logic;
85 signal FlagWR : std_logic;
85
86
86 begin
87 begin
87
88
88 Rec.DEVICE_Cfg(0) <= FlagRE;
89 Rec.DEVICE_Cfg(0) <= FlagRE;
89 Rec.DEVICE_Cfg(1) <= FlagWR;
90 Rec.DEVICE_Cfg(1) <= FlagWR;
90 Rec.DEVICE_Cfg(2) <= FlagEmpty;
91 Rec.DEVICE_Cfg(2) <= FlagEmpty;
91 Rec.DEVICE_Cfg(3) <= FlagFull;
92 Rec.DEVICE_Cfg(3) <= FlagFull;
92 ReUse <= Rec.DEVICE_Cfg(4);
93 ReUse <= Rec.DEVICE_Cfg(4);
94 Lock <= Rec.DEVICE_Cfg(5);
93
95
94 DataIn <= Rec.DEVICE_DataW;
96 DataIn <= Rec.DEVICE_DataW;
95 Rec.DEVICE_DataR <= DataOut;
97 Rec.DEVICE_DataR <= DataOut;
96 Rec.DEVICE_AddrW <= AddrIn;
98 Rec.DEVICE_AddrW <= AddrIn;
97 Rec.DEVICE_AddrR <= AddrOut;
99 Rec.DEVICE_AddrR <= AddrOut;
98
100
99
101
100
102
101 process(rst,clk)
103 process(rst,clk)
102 begin
104 begin
103 if(rst='0')then
105 if(rst='0')then
104 Rec.DEVICE_DataW <= (others => '0');
106 Rec.DEVICE_DataW <= (others => '0');
105 FlagWR <= '0';
107 FlagWR <= '0';
106 FlagRE <= '0';
108 FlagRE <= '0';
107 Rec.DEVICE_Cfg(4) <= '0';
109 Rec.DEVICE_Cfg(4) <= '0';
110 Rec.DEVICE_Cfg(5) <= '0';
108
111
109 elsif(clk'event and clk='1')then
112 elsif(clk'event and clk='1')then
110
113
111 --APB Write OP
114 --APB Write OP
112 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
115 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
113 case apbi.paddr(abits-1 downto 2) is
116 case apbi.paddr(abits-1 downto 2) is
114 when "000000" =>
117 when "000000" =>
115 FlagWR <= '1';
118 FlagWR <= '1';
116 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
119 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
117 when "000010" =>
120 when "000010" =>
118 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
121 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
122 Rec.DEVICE_Cfg(5) <= apbi.pwdata(20);
119 when others =>
123 when others =>
120 null;
124 null;
121 end case;
125 end case;
122 else
126 else
123 FlagWR <= '0';
127 FlagWR <= '0';
124 end if;
128 end if;
125
129
126 --APB Read OP
130 --APB Read OP
127 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
131 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
128 case apbi.paddr(abits-1 downto 2) is
132 case apbi.paddr(abits-1 downto 2) is
129 when "000000" =>
133 when "000000" =>
130 FlagRE <= '1';
134 FlagRE <= '1';
131 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
135 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
132 when "000001" =>
136 when "000001" =>
133 Rdata(31 downto 8) <= X"AAAAAA";
137 Rdata(31 downto 8) <= X"AAAAAA";
134 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
138 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
135 when "000101" =>
139 when "000101" =>
136 Rdata(31 downto 8) <= X"AAAAAA";
140 Rdata(31 downto 8) <= X"AAAAAA";
137 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
141 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
138 when "000010" =>
142 when "000010" =>
139 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
143 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
140 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
144 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
141 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
145 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
142 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
146 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
143 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
147 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
144 Rdata(31 downto 20) <= X"CCC";
148 Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5);
149 Rdata(31 downto 24) <= X"CC";
145 when others =>
150 when others =>
146 Rdata <= (others => '0');
151 Rdata <= (others => '0');
147 end case;
152 end case;
148 else
153 else
149 FlagRE <= '0';
154 FlagRE <= '0';
150 end if;
155 end if;
151
156
152 end if;
157 end if;
153 apbo.pconfig <= pconfig;
158 apbo.pconfig <= pconfig;
154 end process;
159 end process;
155
160
156 apbo.prdata <= Rdata when apbi.penable = '1';
161 apbo.prdata <= Rdata when apbi.penable = '1';
157 WriteEnable <= FlagWR;
162 WriteEnable <= FlagWR;
158 ReadEnable <= FlagRE;
163 ReadEnable <= FlagRE;
159
164
160 end ar_ApbDriver; No newline at end of file
165 end ar_ApbDriver;
Show file before | Show file after | Hide comments
@@ -1,236 +1,242
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_memory is
32 package lpp_memory is
33
33
34 --===========================================================|
34 --===========================================================|
35 --=================== FIFO Compl�te =========================|
35 --=================== FIFO Compl�te =========================|
36 --===========================================================|
36 --===========================================================|
37
37
38 component APB_FIFO is
38 component APB_FIFO is
39 generic (
39 generic (
40 pindex : integer := 0;
40 pindex : integer := 0;
41 paddr : integer := 0;
41 paddr : integer := 0;
42 pmask : integer := 16#fff#;
42 pmask : integer := 16#fff#;
43 pirq : integer := 0;
43 pirq : integer := 0;
44 abits : integer := 8;
44 abits : integer := 8;
45 Data_sz : integer := 16;
45 Data_sz : integer := 16;
46 Addr_sz : integer := 8;
46 Addr_sz : integer := 8;
47 addr_max_int : integer := 256);
47 addr_max_int : integer := 256);
48 port (
48 port (
49 clk : in std_logic;
49 clk : in std_logic;
50 rst : in std_logic;
50 rst : in std_logic;
51 apbi : in apb_slv_in_type;
51 apbi : in apb_slv_in_type;
52 apbo : out apb_slv_out_type
52 apbo : out apb_slv_out_type
53 );
53 );
54 end component;
54 end component;
55
55
56
56
57 component ApbDriver is
57 component ApbDriver is
58 generic (
58 generic (
59 pindex : integer := 0;
59 pindex : integer := 0;
60 paddr : integer := 0;
60 paddr : integer := 0;
61 pmask : integer := 16#fff#;
61 pmask : integer := 16#fff#;
62 pirq : integer := 0;
62 pirq : integer := 0;
63 abits : integer := 8;
63 abits : integer := 8;
64 LPP_DEVICE : integer;
64 LPP_DEVICE : integer;
65 Data_sz : integer := 16;
65 Data_sz : integer := 16;
66 Addr_sz : integer := 8;
66 Addr_sz : integer := 8;
67 addr_max_int : integer := 256);
67 addr_max_int : integer := 256);
68 port (
68 port (
69 clk : in std_logic;
69 clk : in std_logic;
70 rst : in std_logic;
70 rst : in std_logic;
71 ReadEnable : in std_logic;
71 ReadEnable : in std_logic;
72 WriteEnable : in std_logic;
72 WriteEnable : in std_logic;
73 FlagEmpty : in std_logic;
73 FlagEmpty : in std_logic;
74 FlagFull : in std_logic;
74 FlagFull : in std_logic;
75 ReUse : in std_logic;
75 ReUse : out std_logic;
76 Lock : out std_logic;
76 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 apbi : in apb_slv_in_type;
81 apbi : in apb_slv_in_type;
81 apbo : out apb_slv_out_type
82 apbo : out apb_slv_out_type
82 );
83 );
83 end component;
84 end component;
84
85
85
86
86 component Top_FIFO is
87 component Top_FIFO is
87 generic(
88 generic(
88 Data_sz : integer := 16;
89 Data_sz : integer := 16;
89 Addr_sz : integer := 8;
90 Addr_sz : integer := 8;
90 addr_max_int : integer := 256
91 addr_max_int : integer := 256
91 );
92 );
92 port(
93 port(
93 clk,raz : in std_logic;
94 clk,raz : in std_logic;
94 flag_RE : in std_logic;
95 flag_RE : in std_logic;
95 flag_WR : in std_logic;
96 flag_WR : in std_logic;
96 ReUse : in std_logic;
97 ReUse : in std_logic;
98 Lock : in std_logic;
97 Data_in : in std_logic_vector(Data_sz-1 downto 0);
99 Data_in : in std_logic_vector(Data_sz-1 downto 0);
98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
100 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
101 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
100 full : out std_logic;
102 full : out std_logic;
101 empty : out std_logic;
103 empty : out std_logic;
102 Data_out : out std_logic_vector(Data_sz-1 downto 0)
104 Data_out : out std_logic_vector(Data_sz-1 downto 0)
103 );
105 );
104 end component;
106 end component;
105
107
106
108
107 component Fifo_Read is
109 component Fifo_Read is
108 generic(
110 generic(
109 Addr_sz : integer := 8;
111 Addr_sz : integer := 8;
110 addr_max_int : integer := 256);
112 addr_max_int : integer := 256);
111 port(
113 port(
112 clk : in std_logic;
114 clk : in std_logic;
113 raz : in std_logic;
115 raz : in std_logic;
114 flag_RE : in std_logic;
116 flag_RE : in std_logic;
115 ReUse : in std_logic;
117 ReUse : in std_logic;
116 Waddr : in std_logic_vector(addr_sz-1 downto 0);
118 Waddr : in std_logic_vector(addr_sz-1 downto 0);
117 empty : out std_logic;
119 empty : out std_logic;
118 Raddr : out std_logic_vector(addr_sz-1 downto 0)
120 Raddr : out std_logic_vector(addr_sz-1 downto 0)
119 );
121 );
120 end component;
122 end component;
121
123
122
124
123 component Fifo_Write is
125 component Fifo_Write is
124 generic(
126 generic(
125 Addr_sz : integer := 8;
127 Addr_sz : integer := 8;
126 addr_max_int : integer := 256);
128 addr_max_int : integer := 256);
127 port(
129 port(
128 clk : in std_logic;
130 clk : in std_logic;
129 raz : in std_logic;
131 raz : in std_logic;
130 flag_WR : in std_logic;
132 flag_WR : in std_logic;
131 Raddr : in std_logic_vector(addr_sz-1 downto 0);
133 Raddr : in std_logic_vector(addr_sz-1 downto 0);
132 full : out std_logic;
134 full : out std_logic;
133 Waddr : out std_logic_vector(addr_sz-1 downto 0)
135 Waddr : out std_logic_vector(addr_sz-1 downto 0)
134 );
136 );
135 end component;
137 end component;
136
138
137
139
138 component Link_Reg is
140 component Link_Reg is
139 generic(Data_sz : integer := 16);
141 generic(Data_sz : integer := 16);
140 port(
142 port(
141 clk,raz : in std_logic;
143 clk,raz : in std_logic;
142 Data_one : in std_logic_vector(Data_sz-1 downto 0);
144 Data_one : in std_logic_vector(Data_sz-1 downto 0);
143 Data_two : in std_logic_vector(Data_sz-1 downto 0);
145 Data_two : in std_logic_vector(Data_sz-1 downto 0);
144 ReUse : in std_logic;
146 ReUse : in std_logic;
145 flag_RE : in std_logic;
147 flag_RE : in std_logic;
146 flag_WR : in std_logic;
148 flag_WR : in std_logic;
147 empty : in std_logic;
149 empty : in std_logic;
148 Data_out : out std_logic_vector(Data_sz-1 downto 0)
150 Data_out : out std_logic_vector(Data_sz-1 downto 0)
149 );
151 );
150 end component;
152 end component;
151
153
152 --===========================================================|
154 --===========================================================|
153 --================= Demi FIFO Ecriture ======================|
155 --================= Demi FIFO Ecriture ======================|
154 --===========================================================|
156 --===========================================================|
155
157
156 component APB_FifoWrite is
158 component APB_FifoWrite is
157 generic (
159 generic (
158 pindex : integer := 0;
160 pindex : integer := 0;
159 paddr : integer := 0;
161 paddr : integer := 0;
160 pmask : integer := 16#fff#;
162 pmask : integer := 16#fff#;
161 pirq : integer := 0;
163 pirq : integer := 0;
162 abits : integer := 8;
164 abits : integer := 8;
163 Data_sz : integer := 16;
165 Data_sz : integer := 16;
164 Addr_sz : integer := 8;
166 Addr_sz : integer := 8;
165 addr_max_int : integer := 256);
167 addr_max_int : integer := 256);
166 port (
168 port (
167 clk : in std_logic;
169 clk : in std_logic;
168 rst : in std_logic;
170 rst : in std_logic;
169 apbi : in apb_slv_in_type;
171 apbi : in apb_slv_in_type;
172 ReadEnable : in std_logic;
173 DATA : out std_logic_vector(Data_sz-1 downto 0);
170 apbo : out apb_slv_out_type
174 apbo : out apb_slv_out_type
171 );
175 );
172 end component;
176 end component;
173
177
174
178
175 component Top_FifoWrite is
179 --component Top_FifoWrite is
176 generic(
180 -- generic(
177 Data_sz : integer := 16;
181 -- Data_sz : integer := 16;
178 Addr_sz : integer := 8;
182 -- Addr_sz : integer := 8;
179 addr_max_int : integer := 256);
183 -- addr_max_int : integer := 256);
180 port(
184 -- port(
181 clk : in std_logic;
185 -- clk : in std_logic;
182 raz : in std_logic;
186 -- raz : in std_logic;
183 flag_RE : in std_logic;
187 -- flag_RE : in std_logic;
184 flag_WR : in std_logic;
188 -- flag_WR : in std_logic;
185 Data_in : in std_logic_vector(Data_sz-1 downto 0);
189 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
186 Raddr : in std_logic_vector(addr_sz-1 downto 0);
190 -- Raddr : in std_logic_vector(addr_sz-1 downto 0);
187 full : out std_logic;
191 -- full : out std_logic;
188 empty : out std_logic;
192 -- empty : out std_logic;
189 Waddr : out std_logic_vector(addr_sz-1 downto 0);
193 -- Waddr : out std_logic_vector(addr_sz-1 downto 0);
190 Data_out : out std_logic_vector(Data_sz-1 downto 0)
194 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
191 );
195 -- );
192 end component;
196 --end component;
193
197
194 --===========================================================|
198 --===========================================================|
195 --================== Demi FIFO Lecture ======================|
199 --================== Demi FIFO Lecture ======================|
196 --===========================================================|
200 --===========================================================|
197
201
198 component APB_FifoRead is
202 component APB_FifoRead is
199 generic (
203 generic (
200 pindex : integer := 0;
204 pindex : integer := 0;
201 paddr : integer := 0;
205 paddr : integer := 0;
202 pmask : integer := 16#fff#;
206 pmask : integer := 16#fff#;
203 pirq : integer := 0;
207 pirq : integer := 0;
204 abits : integer := 8;
208 abits : integer := 8;
205 Data_sz : integer := 16;
209 Data_sz : integer := 16;
206 Addr_sz : integer := 8;
210 Addr_sz : integer := 8;
207 addr_max_int : integer := 256);
211 addr_max_int : integer := 256);
208 port (
212 port (
209 clk : in std_logic;
213 clk : in std_logic;
210 rst : in std_logic;
214 rst : in std_logic;
211 apbi : in apb_slv_in_type;
215 apbi : in apb_slv_in_type;
216 WriteEnable : in std_logic;
217 DATA : out std_logic_vector(Data_sz-1 downto 0);
212 apbo : out apb_slv_out_type
218 apbo : out apb_slv_out_type
213 );
219 );
214 end component;
220 end component;
215
221
216
222
217 component Top_FifoRead is
223 --component Top_FifoRead is
218 generic(
224 -- generic(
219 Data_sz : integer := 16;
225 -- Data_sz : integer := 16;
220 Addr_sz : integer := 8;
226 -- Addr_sz : integer := 8;
221 addr_max_int : integer := 256);
227 -- addr_max_int : integer := 256);
222 port(
228 -- port(
223 clk : in std_logic;
229 -- clk : in std_logic;
224 raz : in std_logic;
230 -- raz : in std_logic;
225 flag_RE : in std_logic;
231 -- flag_RE : in std_logic;
226 flag_WR : in std_logic;
232 -- flag_WR : in std_logic;
227 Data_in : in std_logic_vector(Data_sz-1 downto 0);
233 -- Data_in : in std_logic_vector(Data_sz-1 downto 0);
228 Waddr : in std_logic_vector(addr_sz-1 downto 0);
234 -- Waddr : in std_logic_vector(addr_sz-1 downto 0);
229 full : out std_logic;
235 -- full : out std_logic;
230 empty : out std_logic;
236 -- empty : out std_logic;
231 Raddr : out std_logic_vector(addr_sz-1 downto 0);
237 -- Raddr : out std_logic_vector(addr_sz-1 downto 0);
232 Data_out : out std_logic_vector(Data_sz-1 downto 0)
238 -- Data_out : out std_logic_vector(Data_sz-1 downto 0)
233 );
239 -- );
234 end component;
240 --end component;
235
241
236 end;
242 end;
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