diff --git a/lib/lpp/lpp_matrix/ALU_Driver.vhd b/lib/lpp/lpp_matrix/ALU_Driver.vhd --- a/lib/lpp/lpp_matrix/ALU_Driver.vhd +++ b/lib/lpp/lpp_matrix/ALU_Driver.vhd @@ -30,17 +30,18 @@ entity ALU_Driver is Input_SZ_1 : integer := 16; Input_SZ_2 : integer := 16); port( - clk : in std_logic; --! Horloge du composant - reset : in std_logic; --! Reset general du composant - IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donnée d'entrée - IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donnée d'entrée - Take : in std_logic; --! Flag, opérande récupéré - Received : in std_logic; --! Flag, Résultat bien ressu - Valid : out std_logic; --! Flag, Résultat disponible - Read : out std_logic; --! Flag, opérande disponible - CTRL : out std_logic_vector(4 downto 0); --! Permet de sélectionner la/les opération désirée - OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Opérande - OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Opérande + clk : in std_logic; --! Horloge du composant + reset : in std_logic; --! Reset general du composant + IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); --! Donnée d'entrée + IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); --! Donnée d'entrée + Take : in std_logic; --! Flag, opérande récupéré + Received : in std_logic; --! Flag, Résultat bien ressu + Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugué + Valid : out std_logic; --! Flag, Résultat disponible + Read : out std_logic; --! Flag, opérande disponible + CTRL : out std_logic_vector(4 downto 0); --! Permet de sélectionner la/les opération désirée + OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); --! Premier Opérande + OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) --! Second Opérande ); end ALU_Driver; @@ -66,13 +67,13 @@ begin begin if(reset='0')then - ect <= eX; - st <= e0; - go_st <= '0'; - CTRL <= "10000"; - Read <= '0'; - Valid <= '0'; - Take_reg <= '0'; + ect <= eX; + st <= e0; + go_st <= '0'; + CTRL <= "10000"; + Read <= '0'; + Valid <= '0'; + Take_reg <= '0'; Received_reg <= '0'; elsif(clk'event and clk='1')then @@ -120,7 +121,11 @@ begin CTRL <= "00000"; go_st <= '1'; if(Received_reg='0' and Received='1')then - ect <= e3; + if(Conjugate='1')then + ect <= eX; + else + ect <= e3; + end if; end if; when e3 => @@ -147,7 +152,7 @@ begin ect <= eX; end if; end case; - +--------------------------------------------------------------------------------- case st is when e0 => if(go_st='1')then @@ -160,8 +165,12 @@ begin when e2 => if(Received_reg='0' and Received='1')then - Valid <= '0'; - st <= idle; + Valid <= '0'; + if(Conjugate='1')then + st <= idle2; + else + st <= idle; + end if; end if; when idle => diff --git a/lib/lpp/lpp_matrix/ALU_v2.vhd b/lib/lpp/lpp_matrix/ALU_v2.vhd --- a/lib/lpp/lpp_matrix/ALU_v2.vhd +++ b/lib/lpp/lpp_matrix/ALU_v2.vhd @@ -22,6 +22,7 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; +use lpp.lpp_matrix.all; --! Une ALU : Arithmetic and logical unit, permettant de réaliser une ou plusieurs opération @@ -58,7 +59,7 @@ begin clr_MAC <= '1' when ctrl = "10000" else '0'; arith : if Arith_en = 1 generate -MACinst : entity work.MAC_v2 +MACinst : MAC_v2 generic map(Input_SZ_1,Input_SZ_2) port map(clk,reset,clr_MAC,ctrl(3 downto 0),OP1,OP2,RES); end generate; diff --git a/lib/lpp/lpp_matrix/GetResult.vhd b/lib/lpp/lpp_matrix/GetResult.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/GetResult.vhd @@ -0,0 +1,86 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity GetResult is +generic( + Result_SZ : integer := 32); +port( + clk : in std_logic; + raz : in std_logic; + Valid : in std_logic; + Conjugate : in std_logic; + Res : in std_logic_vector(Result_SZ-1 downto 0); + Received : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end GetResult; + + +architecture ar_GetResult of GetResult is + +signal Valid_reg : std_logic; + +type state is (st0,st1); +signal ect : state; + +begin + process(clk,raz) + begin + + if(raz='0')then + Received <= '0'; + Valid_reg <= '0'; + ect <= st0; + Result <= (others => '0'); + + elsif(clk'event and clk='1')then + Valid_reg <= Valid; + + case ect is + when st0 => + Received <= '0'; + if(Valid_reg='0' and Valid='1')then + Result <= Res; + if(Conjugate='1')then + Received <= '1'; + ect <= st0; + else + ect <= st1; + end if; + end if; + + when st1 => + Received <= '1'; + if(Valid_reg='0' and Valid='1')then + Result <= Res; + ect <= st0; + end if; + + end case; + end if; + end process; + +end ar_GetResult; + diff --git a/lib/lpp/lpp_matrix/MAC_v2.vhd b/lib/lpp/lpp_matrix/MAC_v2.vhd --- a/lib/lpp/lpp_matrix/MAC_v2.vhd +++ b/lib/lpp/lpp_matrix/MAC_v2.vhd @@ -22,6 +22,8 @@ library IEEE; use IEEE.numeric_std.all; use IEEE.std_logic_1164.all; +use lpp.lpp_matrix.all; +use lpp.general_purpose.all; --! Un MAC : Multiplier Accumulator Chip @@ -79,7 +81,7 @@ begin --============================================================== --=============M A C C O N T R O L E R========================= --============================================================== -MAC_CONTROLER1 : entity work.MAC_CONTROLER +MAC_CONTROLER1 : MAC_CONTROLER port map( ctrl => MAC_MUL_ADD_2C_D(1 downto 0), MULT => mult, @@ -96,7 +98,7 @@ port map( --============================================================== --=============M U L T I P L I E R============================== --============================================================== -Multiplieri_nst : entity work.Multiplier +Multiplieri_nst : Multiplier generic map( Input_SZ_A => Input_SZ_A, Input_SZ_B => Input_SZ_B @@ -118,7 +120,7 @@ port map( --============================================================== --======================A D D E R ============================== --============================================================== -adder_inst : entity work.Adder +adder_inst : Adder generic map( Input_SZ_A => Input_SZ_A+Input_SZ_B, Input_SZ_B => Input_SZ_A+Input_SZ_B @@ -141,7 +143,7 @@ port map( --============================================================== --===================TWO COMPLEMENTERS========================== --============================================================== -TWO_COMPLEMENTER1 : entity work.TwoComplementer +TWO_COMPLEMENTER1 : TwoComplementer generic map( Input_SZ => Input_SZ_A ) @@ -155,7 +157,7 @@ port map( ); -TWO_COMPLEMENTER2 : entity work.TwoComplementer +TWO_COMPLEMENTER2 : TwoComplementer generic map( Input_SZ => Input_SZ_B ) @@ -169,7 +171,7 @@ port map( ); --============================================================== -CTRL : entity work.MAC_REG +CTRL : MAC_REG generic map(size => 2) port map( reset => reset, @@ -178,7 +180,7 @@ port map( Q => MAC_MUL_ADD_2C_D(1 downto 0) ); -clr_MACREG1 : entity work.MAC_REG +clr_MACREG1 : MAC_REG generic map(size => 1) port map( reset => reset, @@ -187,7 +189,7 @@ port map( Q(0) => clr_MAC_D ); -clr_MACREG2 : entity work.MAC_REG +clr_MACREG2 : MAC_REG generic map(size => 1) port map( reset => reset, @@ -196,7 +198,7 @@ port map( Q(0) => clr_MAC_D_D ); -addREG : entity work.MAC_REG +addREG : MAC_REG generic map(size => 1) port map( reset => reset, @@ -206,7 +208,7 @@ port map( ); -OP1REG : entity work.MAC_REG +OP1REG : MAC_REG generic map(size => Input_SZ_A) port map( reset => reset, @@ -216,7 +218,7 @@ port map( ); -OP2REG : entity work.MAC_REG +OP2REG : MAC_REG generic map(size => Input_SZ_B) port map( reset => reset, @@ -226,7 +228,7 @@ port map( ); -MULToutREG : entity work.MAC_REG +MULToutREG : MAC_REG generic map(size => Input_SZ_A+Input_SZ_B) port map( reset => reset, @@ -236,7 +238,7 @@ port map( ); -MACMUXselREG : entity work.MAC_REG +MACMUXselREG : MAC_REG generic map(size => 1) port map( reset => reset, @@ -247,7 +249,7 @@ port map( -MACMUX2selREG : entity work.MAC_REG +MACMUX2selREG : MAC_REG generic map(size => 1) port map( reset => reset, @@ -257,7 +259,7 @@ port map( ); -MACMUX2selREG2 : entity work.MAC_REG +MACMUX2selREG2 : MAC_REG generic map(size => 1) port map( reset => reset, @@ -270,7 +272,7 @@ port map( --============================================================== --======================M A C M U X =========================== --============================================================== -MACMUX_inst : entity work.MAC_MUX +MACMUX_inst : MAC_MUX generic map( Input_SZ_A => Input_SZ_A+Input_SZ_B, Input_SZ_B => Input_SZ_A+Input_SZ_B @@ -293,7 +295,7 @@ OP2_Resz <= std_logic_vector(resize(si --============================================================== --======================M A C M U X2 ========================== --============================================================== -MAC_MUX2_inst : entity work.MAC_MUX2 +MAC_MUX2_inst : MAC_MUX2 generic map(Input_SZ => Input_SZ_A+Input_SZ_B) port map( sel => MACMUX2sel_D_D, diff --git a/lib/lpp/lpp_matrix/Matrix.vhd b/lib/lpp/lpp_matrix/Matrix.vhd --- a/lib/lpp/lpp_matrix/Matrix.vhd +++ b/lib/lpp/lpp_matrix/Matrix.vhd @@ -29,15 +29,16 @@ entity Matrix is generic( Input_SZ : integer := 16); port( - clk : in std_logic; --! Horloge du composant - raz : in std_logic; --! Reset general du composant - IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donnée d'entrée - IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donnée d'entrée - Take : in std_logic; --! Flag, opérande récupéré - Received : in std_logic; --! Flag, Résultat bien ressu - Valid : out std_logic; --! Flag, Résultat disponible - Read : out std_logic; --! Flag, opérande disponible - Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! Résultat du calcul + clk : in std_logic; --! Horloge du composant + raz : in std_logic; --! Reset general du composant + IN1 : in std_logic_vector(Input_SZ-1 downto 0); --! Donnée d'entrée + IN2 : in std_logic_vector(Input_SZ-1 downto 0); --! Donnée d'entrée + Take : in std_logic; --! Flag, opérande récupéré + Received : in std_logic; --! Flag, Résultat bien ressu + Conjugate : in std_logic; --! Flag, Calcul sur un complexe et son conjugué + Valid : out std_logic; --! Flag, Résultat disponible + Read : out std_logic; --! Flag, opérande disponible + Result : out std_logic_vector(2*Input_SZ-1 downto 0) --! Résultat du calcul ); end Matrix; @@ -52,7 +53,7 @@ begin DRIVE : entity work.ALU_Driver generic map(Input_SZ,Input_SZ) - port map(clk,raz,IN1,IN2,Take,Received,Valid,Read,CTRL,OP1,OP2); + port map(clk,raz,IN1,IN2,Take,Received,Conjugate,Valid,Read,CTRL,OP1,OP2); ALU : entity work.ALU_v2 diff --git a/lib/lpp/lpp_matrix/SelectInputs.vhd b/lib/lpp/lpp_matrix/SelectInputs.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/SelectInputs.vhd @@ -0,0 +1,359 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity SelectInputs is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + raz : in std_logic; + Read : in std_logic; + B1 : in std_logic_vector(Input_SZ-1 downto 0); + B2 : in std_logic_vector(Input_SZ-1 downto 0); + B3 : in std_logic_vector(Input_SZ-1 downto 0); + E1 : in std_logic_vector(Input_SZ-1 downto 0); + E2 : in std_logic_vector(Input_SZ-1 downto 0); + Conjugate : out std_logic; + Take : out std_logic; + ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + OP1 : out std_logic_vector(Input_SZ-1 downto 0); + OP2 : out std_logic_vector(Input_SZ-1 downto 0) +); +end SelectInputs; + + +architecture ar_SelectInputs of SelectInputs is + +signal Read_reg : std_logic; +signal i : integer range 1 to 15; + +type state is (stX,st1a,st1b); +signal ect : state; + +begin + process(clk,raz) + begin + + if(raz='0')then + Take <= '0'; + i <= 0; + Read_reg <= '0'; + ect <= stX; + + elsif(clk'event and clk='1')then + Read_reg <= Read; + + case ect is + when stX => + i <= 1; + if(Read_reg='0' and Read='1')then + ect <= st1a; + end if; +------------------------------------------------------------------------------- + when st1a => + Take <= '1'; + if(Read_reg='0' and Read='1')then + ect <= st1b; + end if; + + when st1b => + Take <= '0'; + if(i=15)then + ect <= stX; + elsif(Read_reg='0' and Read='1')then + i <= i+1; + ect <= st1a; + end if; +------------------------------------------------------------------------------- +-- when st2a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st2b; +-- end if; +-- +-- when st2b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st3a; +-- end if; +--------------------------------------------------------------------------------- +-- when st3a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st3b; +-- end if; +-- +-- when st3b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st4a; +-- end if; +--------------------------------------------------------------------------------- +-- when st4a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st4b; +-- end if; +-- +-- when st4b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st5a; +-- end if; +--------------------------------------------------------------------------------- +-- +-- when st5a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st5b; +-- end if; +-- +-- when st5b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st6a; +-- end if; +--------------------------------------------------------------------------------- +-- when st6a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st6b; +-- end if; +-- +-- when st6b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st7a; +-- end if; +--------------------------------------------------------------------------------- +-- when st7a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st7b; +-- end if; +-- +-- when st7b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st8a; +-- end if; +--------------------------------------------------------------------------------- +-- when st8a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st8b; +-- end if; +-- +-- when st8b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st9a; +-- end if; +--------------------------------------------------------------------------------- +-- when st9a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st9b; +-- end if; +-- +-- when st9b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st10a; +-- end if; +--------------------------------------------------------------------------------- +-- when st10a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st10b; +-- end if; +-- +-- when st10b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st11a; +-- end if; +--------------------------------------------------------------------------------- +-- when st11a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st11b; +-- end if; +-- +-- when st11b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st12a; +-- end if; +--------------------------------------------------------------------------------- +-- when st12a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st12b; +-- end if; +-- +-- when st12b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st13a; +-- end if; +--------------------------------------------------------------------------------- +-- when st13a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st13b; +-- end if; +-- +-- when st13b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st14a; +-- end if; +--------------------------------------------------------------------------------- +-- when st14a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st14b; +-- end if; +-- +-- when st14b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st15a; +-- end if; +--------------------------------------------------------------------------------- +-- when st15a => +-- Take <= '1'; +-- if(Read_reg='0' and Read='1')then +-- ect <= st7_b; +-- end if; +-- +-- when st15b => +-- Take <= '0'; +-- if(Read_reg='0' and Read='1')then +-- ect <= stX; +-- end if; +------------------------------------------------------------------------------- + end case; + end if; + end process; + +with i select + ReadFIFO <= "10000" when 1, + "11000" when 2, + "01000" when 3, + "10100" when 4, + "01100" when 5, + "00100" when 6, + "10010" when 7, + "01010" when 8, + "00110" when 9, + "00010" when 10, + "10001" when 11, + "01001" when 12, + "00101" when 13, + "00011" when 14, + "00001" when 15, + "00000" when others; + +--with ect select +-- ReadB2 <= Read when st1, +-- Read when st2, +-- Read when st4, +-- Read when st7, +-- Read when st11, +-- '0' when others; +-- +--with ect select +-- ReadB3 <= Read when st3, +-- Read when st4, +-- Read when st5, +-- Read when st8, +-- Read when st12, +-- '0' when others; +-- +--with ect select +-- ReadE1 <= Read when st6, +-- Read when st7, +-- Read when st8, +-- Read when st9, +-- Read when st13, +-- '0' when others; +-- +--with ect select +-- ReadE2 <= Read when st10, +-- Read when st11, +-- Read when st12, +-- Read when st13, +-- Read when st14, +-- '0' when others; + +with i select + OP1 <= B1 when 1, + B1 when 2, + B1 when 4, + B1 when 7, + B1 when 11, + B2 when 3, + B2 when 5, + B2 when 8, + B2 when 12, + B3 when 6, + B3 when 9, + B3 when 13, + E1 when 10, + E1 when 14, + E2 when 15, + X"FFFF" when others; + +with i select + OP2 <= B1 when 1, + B2 when 2, + B2 when 3, + B3 when 4, + B3 when 5, + B3 when 6, + E1 when 7, + E1 when 8, + E1 when 9, + E1 when 10, + E2 when 11, + E2 when 12, + E2 when 13, + E2 when 14, + E2 when 15, + X"FFFF" when others; + +with i select + Conjugate <= '1' when 1, + '1' when 3, + '1' when 6, + '1' when 10, + '1' when 15, + '0' when others; + + +--RE_FIFO <= ReadE2 & ReadE1 & ReadB3 & ReadB2 & ReadB1; +end ar_SelectInputs; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/SpectralMatrix.vhd b/lib/lpp/lpp_matrix/SpectralMatrix.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_matrix/SpectralMatrix.vhd @@ -0,0 +1,74 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------- +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; +use lpp.lpp_matrix.all; + +entity SpectralMatrix is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + B1 : in std_logic_vector(Input_SZ-1 downto 0); + B2 : in std_logic_vector(Input_SZ-1 downto 0); + B3 : in std_logic_vector(Input_SZ-1 downto 0); + E1 : in std_logic_vector(Input_SZ-1 downto 0); + E2 : in std_logic_vector(Input_SZ-1 downto 0); + ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end SpectralMatrix; + + +architecture ar_SpectralMatrix of SpectralMatrix is + +signal Read : std_logic; +signal Take : std_logic; +signal Received : std_logic; +signal Valid : std_logic; +signal Conjugate : std_logic; +signal OP1 : std_logic_vector(Input_SZ-1 downto 0); +signal OP2 : std_logic_vector(Input_SZ-1 downto 0); +signal Resultat : std_logic_vector(Result_SZ-1 downto 0); + +begin + + +IN0 : SelectInputs + generic map(Input_SZ) + port map(clk,reset,Read,B1,B2,B3,E1,E2,Conjugate,Take,ReadFIFO,OP1,OP2); + + +CALC0 : Matrix + generic map(Input_SZ) + port map(clk,reset,OP1,OP2,Take,Received,Conjugate,Valid,Read,Resultat); + + +RES0 : GetResult + generic map(Result_SZ) + port map(clk,reset,Valid,Conjugate,Resultat,Received,Result); + + +end ar_SpectralMatrix; \ No newline at end of file diff --git a/lib/lpp/lpp_matrix/lpp_matrix.vhd b/lib/lpp/lpp_matrix/lpp_matrix.vhd --- a/lib/lpp/lpp_matrix/lpp_matrix.vhd +++ b/lib/lpp/lpp_matrix/lpp_matrix.vhd @@ -47,19 +47,38 @@ component APB_Matrix is end component; +component SpectralMatrix is +generic( + Input_SZ : integer := 16; + Result_SZ : integer := 32); +port( + clk : in std_logic; + reset : in std_logic; + B1 : in std_logic_vector(Input_SZ-1 downto 0); + B2 : in std_logic_vector(Input_SZ-1 downto 0); + B3 : in std_logic_vector(Input_SZ-1 downto 0); + E1 : in std_logic_vector(Input_SZ-1 downto 0); + E2 : in std_logic_vector(Input_SZ-1 downto 0); + ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end component; + + component Matrix is generic( Input_SZ : integer := 16); port( - clk : in std_logic; - raz : in std_logic; - IN1 : in std_logic_vector(Input_SZ-1 downto 0); - IN2 : in std_logic_vector(Input_SZ-1 downto 0); - Take : in std_logic; - Received : in std_logic; - Valid : out std_logic; - Read : out std_logic; - Result : out std_logic_vector(2*Input_SZ-1 downto 0) + clk : in std_logic; + raz : in std_logic; + IN1 : in std_logic_vector(Input_SZ-1 downto 0); + IN2 : in std_logic_vector(Input_SZ-1 downto 0); + Take : in std_logic; + Received : in std_logic; + Conjugate : in std_logic; + Valid : out std_logic; + Read : out std_logic; + Result : out std_logic_vector(2*Input_SZ-1 downto 0) ); end component; @@ -69,17 +88,18 @@ component ALU_Driver is Input_SZ_1 : integer := 16; Input_SZ_2 : integer := 16); port( - clk : in std_logic; - reset : in std_logic; - IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); - IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); - Take : in std_logic; - Received : in std_logic; - Valid : out std_logic; - Read : out std_logic; - CTRL : out std_logic_vector(4 downto 0); - OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); - OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) + clk : in std_logic; + reset : in std_logic; + IN1 : in std_logic_vector(Input_SZ_1-1 downto 0); + IN2 : in std_logic_vector(Input_SZ_2-1 downto 0); + Take : in std_logic; + Received : in std_logic; + Conjugate : in std_logic; + Valid : out std_logic; + Read : out std_logic; + CTRL : out std_logic_vector(4 downto 0); + OP1 : out std_logic_vector(Input_SZ_1-1 downto 0); + OP2 : out std_logic_vector(Input_SZ_2-1 downto 0) ); end component; @@ -130,4 +150,40 @@ port( ); end component; + +component GetResult is +generic( + Result_SZ : integer := 32); +port( + clk : in std_logic; + raz : in std_logic; + Valid : in std_logic; + Conjugate : in std_logic; + Res : in std_logic_vector(Result_SZ-1 downto 0); + Received : out std_logic; + Result : out std_logic_vector(Result_SZ-1 downto 0) +); +end component; + + +component SelectInputs is +generic( + Input_SZ : integer := 16); +port( + clk : in std_logic; + raz : in std_logic; + Read : in std_logic; + B1 : in std_logic_vector(Input_SZ-1 downto 0); + B2 : in std_logic_vector(Input_SZ-1 downto 0); + B3 : in std_logic_vector(Input_SZ-1 downto 0); + E1 : in std_logic_vector(Input_SZ-1 downto 0); + E2 : in std_logic_vector(Input_SZ-1 downto 0); + Conjugate : out std_logic; + Take : out std_logic; + ReadFIFO : out std_logic_vector(4 downto 0); --B1,B2,B3,E1,E2 + OP1 : out std_logic_vector(Input_SZ-1 downto 0); + OP2 : out std_logic_vector(Input_SZ-1 downto 0) +); +end component; + end; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoRead.vhd b/lib/lpp/lpp_memory/APB_FifoRead.vhd --- a/lib/lpp/lpp_memory/APB_FifoRead.vhd +++ b/lib/lpp/lpp_memory/APB_FifoRead.vhd @@ -28,7 +28,7 @@ use grlib.devices.all; library lpp; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; -use lpp.lpp_fifo.all; +use lpp.lpp_memory.all; --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba @@ -43,38 +43,41 @@ entity APB_FifoRead is Addr_sz : integer := 8; addr_max_int : integer := 256); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - Flag_WR : in std_logic; --! Demande l'écriture dans la mémoire, géré hors de l'IP - Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + WriteEnable : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP + DATA : out std_logic_vector(Data_sz-1 downto 0); --! Données en sortie de la mémoire + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end APB_FifoRead; ---! @details Gestion de la FIFO uniquement en écriture +--! @details Gestion de la FIFO, écriture interne au FPGA, lecture via le bus APB architecture ar_APB_FifoRead of APB_FifoRead is +signal Low : std_logic:='0'; signal ReadEnable : std_logic; ---signal WriteEnable : std_logic; signal FlagEmpty : std_logic; ---signal FlagFull : std_logic; +signal FlagFull : std_logic; +signal ReUse : std_logic; +signal Lock : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); ---signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); +signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,open,FlagEmpty,open,DataIn,DataOut,open,AddrOut,apbi,apbo); + port map(clk,rst,ReadEnable,Low,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - MEMORY_READ : Top_FifoRead + FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,ReadEnable,flag_WR,DataIn,Waddr,FlagEmpty,AddrOut,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); +DATA <= DataOut; -end ar_APB_FifoReade; \ No newline at end of file +end ar_APB_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/APB_FifoWrite.vhd b/lib/lpp/lpp_memory/APB_FifoWrite.vhd --- a/lib/lpp/lpp_memory/APB_FifoWrite.vhd +++ b/lib/lpp/lpp_memory/APB_FifoWrite.vhd @@ -28,7 +28,7 @@ use grlib.devices.all; library lpp; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; -use lpp.lpp_fifo.all; +use lpp.lpp_memory.all; --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba @@ -43,38 +43,41 @@ entity APB_FifoWrite is Addr_sz : integer := 8; addr_max_int : integer := 256); port ( - clk : in std_logic; --! Horloge du composant - rst : in std_logic; --! Reset general du composant - apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus - Flag_RE : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP - Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture dans la mémoire - apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus + clk : in std_logic; --! Horloge du composant + rst : in std_logic; --! Reset general du composant + apbi : in apb_slv_in_type; --! Registre de gestion des entrées du bus + ReadEnable : in std_logic; --! Demande de lecture de la mémoire, géré hors de l'IP + DATA : out std_logic_vector(Data_sz-1 downto 0); --! Données en sortie de la mémoire + apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus ); end APB_FifoWrite; ---! @details Gestion de la FIFO uniquement en lecture +--! @details Gestion de la FIFO, écriture via le bus APB, lecture interne au FPGA architecture ar_APB_FifoWrite of APB_FifoWrite is ---signal ReadEnable : std_logic; +signal Low : std_logic:='0'; signal WriteEnable : std_logic; ---signal FlagEmpty : std_logic; +signal FlagEmpty : std_logic; signal FlagFull : std_logic; +signal ReUse : std_logic; +signal Lock : std_logic; signal DataIn : std_logic_vector(Data_sz-1 downto 0); signal DataOut : std_logic_vector(Data_sz-1 downto 0); signal AddrIn : std_logic_vector(Addr_sz-1 downto 0); ---signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); +signal AddrOut : std_logic_vector(Addr_sz-1 downto 0); begin APB : ApbDriver generic map(pindex,paddr,pmask,pirq,abits,LPP_FIFO,Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,open,WriteEnable,open,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); + port map(clk,rst,Low,WriteEnable,FlagEmpty,FlagFull,ReUse,Lock,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo); - MEMORY_WRITE : Top_FifoWrite + FIFO : Top_FIFO generic map(Data_sz,Addr_sz,addr_max_int) - port map(clk,rst,flag_RE,WriteEnable,DataIn,Raddr,FlagFull,AddrIn,DataOut); + port map(clk,rst,ReadEnable,WriteEnable,ReUse,Lock,DataIn,AddrOut,AddrIn,FlagFull,FlagEmpty,DataOut); +DATA <= DataOut; end ar_APB_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/ApbDriver.vhd b/lib/lpp/lpp_memory/ApbDriver.vhd --- a/lib/lpp/lpp_memory/ApbDriver.vhd +++ b/lib/lpp/lpp_memory/ApbDriver.vhd @@ -49,7 +49,8 @@ entity ApbDriver is WriteEnable : out std_logic; --! Instruction d'écriture en mémoire FlagEmpty : in std_logic; --! Flag, Mémoire vide FlagFull : in std_logic; --! Flag, Mémoire pleine - ReUse : out std_logic; --! Flag, Permet de relire la mémoire du début + ReUse : out std_logic; --! Flag, Permet de relire la mémoire du début + Lock : out std_logic; --! Flag, Permet de bloquer l'écriture dans la mémoire DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de données en entrée DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de données en sortie AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (écriture) @@ -70,7 +71,7 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); type DEVICE_ctrlr_Reg is record - DEVICE_Cfg : std_logic_vector(4 downto 0); + DEVICE_Cfg : std_logic_vector(5 downto 0); DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0); DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0); DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0); @@ -90,6 +91,7 @@ Rec.DEVICE_Cfg(1) <= FlagWR; Rec.DEVICE_Cfg(2) <= FlagEmpty; Rec.DEVICE_Cfg(3) <= FlagFull; ReUse <= Rec.DEVICE_Cfg(4); +Lock <= Rec.DEVICE_Cfg(5); DataIn <= Rec.DEVICE_DataW; Rec.DEVICE_DataR <= DataOut; @@ -105,6 +107,7 @@ Rec.DEVICE_AddrR <= AddrOut; FlagWR <= '0'; FlagRE <= '0'; Rec.DEVICE_Cfg(4) <= '0'; + Rec.DEVICE_Cfg(5) <= '0'; elsif(clk'event and clk='1')then @@ -116,6 +119,7 @@ Rec.DEVICE_AddrR <= AddrOut; Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0); when "000010" => Rec.DEVICE_Cfg(4) <= apbi.pwdata(16); + Rec.DEVICE_Cfg(5) <= apbi.pwdata(20); when others => null; end case; @@ -140,8 +144,9 @@ Rec.DEVICE_AddrR <= AddrOut; Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1); Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2); Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3); - Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); - Rdata(31 downto 20) <= X"CCC"; + Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4); + Rdata(23 downto 20) <= "000" & Rec.DEVICE_Cfg(5); + Rdata(31 downto 24) <= X"CC"; when others => Rdata <= (others => '0'); end case; diff --git a/lib/lpp/lpp_memory/Top_FifoRead.vhd b/lib/lpp/lpp_memory/Top_FifoRead.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Top_FifoRead.vhd +++ /dev/null @@ -1,103 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library techmap; -use techmap.gencomp.all; -use work.config.all; - ---! Programme de la FIFO - -entity Top_FifoRead is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant - Waddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire - empty : out std_logic; --! Flag, Mémoire vide - Raddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mémoire - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant - ); -end Top_FifoRead; - ---! @details Une mémoire SRAM de chez Gaisler est utilisée, ---! associée a une fifo, utilisé pour la lecture - -architecture ar_Top_FifoRead of Top_FifoRead is - -component syncram_2p - generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); - port ( - rclk : in std_ulogic; - renable : in std_ulogic; - raddress : in std_logic_vector((abits -1) downto 0); - dataout : out std_logic_vector((dbits -1) downto 0); - wclk : in std_ulogic; - write : in std_ulogic; - waddress : in std_logic_vector((abits -1) downto 0); - datain : in std_logic_vector((dbits -1) downto 0)); -end component; - -signal Raddr_int : std_logic_vector(addr_sz-1 downto 0); -signal s_flag_RE : std_logic; -signal s_empty : std_logic; - -begin - - SRAM : syncram_2p - generic map(CFG_MEMTECH,addr_sz,Data_sz) - port map(clk,s_flag_RE,Waddr,Data_int,clk,flag_WR,Raddr_int,Data_in); - - - RE : entity work.Fifo_Read - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_RE,Waddr,s_empty,Raddr_int); - - link : entity work.Link_Reg - generic map(Data_sz) - port map(clk,raz,Data_in,Data_int,s_flag_RE,flag_WR,s_empty,Data_out); - - process(clk,raz) - begin - if(raz='0')then - s_flag_RE <= '0'; - - elsif(clk'event and clk='1')then - if(s_empty='0')then - s_flag_RE <= Flag_RE; - else - s_flag_RE <= '0'; - end if; - - end if; - end process; - -empty <= s_empty; -Raddr <= Raddr_int; - -end ar_Top_FifoRead; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/Top_FifoWrite.vhd b/lib/lpp/lpp_memory/Top_FifoWrite.vhd deleted file mode 100644 --- a/lib/lpp/lpp_memory/Top_FifoWrite.vhd +++ /dev/null @@ -1,101 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; -library techmap; -use techmap.gencomp.all; -use work.config.all; - ---! Programme de la FIFO - -entity Top_FifoWrite is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk,raz : in std_logic; --! Horloge et reset general du composant - flag_RE : in std_logic; --! Flag, Demande la lecture de la mémoire - flag_WR : in std_logic; --! Flag, Demande l'écriture dans la mémoire - Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrée du composant - Raddr : in std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre d'écriture dans la mémoire - full : out std_logic; --! Flag, Mémoire pleine - Waddr : out std_logic_vector(addr_sz-1 downto 0); --! Adresse du registre de lecture de la mémoire - Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant - ); -end Top_FifoWrite; - ---! @details Une mémoire SRAM de chez Gaisler est utilisée, ---! associée a un Driver, utilisée pour écrire dans celle-ci - -architecture ar_Top_FifoWrite of Top_FifoWrite is - -component syncram_2p - generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer := 0); - port ( - rclk : in std_ulogic; - renable : in std_ulogic; - raddress : in std_logic_vector((abits -1) downto 0); - dataout : out std_logic_vector((dbits -1) downto 0); - wclk : in std_ulogic; - write : in std_ulogic; - waddress : in std_logic_vector((abits -1) downto 0); - datain : in std_logic_vector((dbits -1) downto 0)); -end component; - -signal Waddr_int : std_logic_vector(addr_sz-1 downto 0); -signal s_flag_WR : std_logic; -signal s_full : std_logic; - -begin - - - WR : entity work.Fifo_Write - generic map(Addr_sz,addr_max_int) - port map(clk,raz,s_flag_WR,Raddr,s_full,Waddr_int); - - - SRAM : syncram_2p - generic map(CFG_MEMTECH,Addr_sz,Data_sz) - port map(clk,flag_RE,Raddr,Data_out,clk,s_flag_WR,Waddr_int,Data_in); - - - process(clk,raz) - begin - if(raz='0')then - s_flag_WR <= '0'; - - elsif(clk'event and clk='1')then - if(s_full='0')then - s_flag_WR <= Flag_WR; - else - s_flag_WR <= '0'; - end if; - - end if; - end process; - -Waddr <= Waddr_int; -full <= s_full; - -end ar_Top_FifoWrite; \ No newline at end of file diff --git a/lib/lpp/lpp_memory/lpp_memory.vhd b/lib/lpp/lpp_memory/lpp_memory.vhd --- a/lib/lpp/lpp_memory/lpp_memory.vhd +++ b/lib/lpp/lpp_memory/lpp_memory.vhd @@ -72,7 +72,8 @@ component ApbDriver is WriteEnable : in std_logic; FlagEmpty : in std_logic; FlagFull : in std_logic; - ReUse : in std_logic; + ReUse : out std_logic; + Lock : out std_logic; DataIn : out std_logic_vector(Data_sz-1 downto 0); DataOut : in std_logic_vector(Data_sz-1 downto 0); AddrIn : in std_logic_vector(Addr_sz-1 downto 0); @@ -94,6 +95,7 @@ component Top_FIFO is flag_RE : in std_logic; flag_WR : in std_logic; ReUse : in std_logic; + Lock : in std_logic; Data_in : in std_logic_vector(Data_sz-1 downto 0); Addr_RE : out std_logic_vector(addr_sz-1 downto 0); Addr_WR : out std_logic_vector(addr_sz-1 downto 0); @@ -167,29 +169,31 @@ component APB_FifoWrite is clk : in std_logic; rst : in std_logic; apbi : in apb_slv_in_type; + ReadEnable : in std_logic; + DATA : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type ); end component; -component Top_FifoWrite is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); - Raddr : in std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - empty : out std_logic; - Waddr : out std_logic_vector(addr_sz-1 downto 0); - Data_out : out std_logic_vector(Data_sz-1 downto 0) - ); -end component; +--component Top_FifoWrite is +-- generic( +-- Data_sz : integer := 16; +-- Addr_sz : integer := 8; +-- addr_max_int : integer := 256); +-- port( +-- clk : in std_logic; +-- raz : in std_logic; +-- flag_RE : in std_logic; +-- flag_WR : in std_logic; +-- Data_in : in std_logic_vector(Data_sz-1 downto 0); +-- Raddr : in std_logic_vector(addr_sz-1 downto 0); +-- full : out std_logic; +-- empty : out std_logic; +-- Waddr : out std_logic_vector(addr_sz-1 downto 0); +-- Data_out : out std_logic_vector(Data_sz-1 downto 0) +-- ); +--end component; --===========================================================| --================== Demi FIFO Lecture ======================| @@ -209,28 +213,30 @@ component APB_FifoRead is clk : in std_logic; rst : in std_logic; apbi : in apb_slv_in_type; + WriteEnable : in std_logic; + DATA : out std_logic_vector(Data_sz-1 downto 0); apbo : out apb_slv_out_type ); end component; -component Top_FifoRead is - generic( - Data_sz : integer := 16; - Addr_sz : integer := 8; - addr_max_int : integer := 256); - port( - clk : in std_logic; - raz : in std_logic; - flag_RE : in std_logic; - flag_WR : in std_logic; - Data_in : in std_logic_vector(Data_sz-1 downto 0); - Waddr : in std_logic_vector(addr_sz-1 downto 0); - full : out std_logic; - empty : out std_logic; - Raddr : out std_logic_vector(addr_sz-1 downto 0); - Data_out : out std_logic_vector(Data_sz-1 downto 0) - ); -end component; +--component Top_FifoRead is +-- generic( +-- Data_sz : integer := 16; +-- Addr_sz : integer := 8; +-- addr_max_int : integer := 256); +-- port( +-- clk : in std_logic; +-- raz : in std_logic; +-- flag_RE : in std_logic; +-- flag_WR : in std_logic; +-- Data_in : in std_logic_vector(Data_sz-1 downto 0); +-- Waddr : in std_logic_vector(addr_sz-1 downto 0); +-- full : out std_logic; +-- empty : out std_logic; +-- Raddr : out std_logic_vector(addr_sz-1 downto 0); +-- Data_out : out std_logic_vector(Data_sz-1 downto 0) +-- ); +--end component; end;