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add lpp_waveform (and sub module)
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE std.textio.ALL;
29
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE GRLIB.DMA2AHB_Package.ALL;
34
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
37
38 PACKAGE lpp_dma_pkg_LPP_JCP IS
39
40 COMPONENT lpp_dma_send_1word_LPP_JCP
41 PORT (
42 HCLK : IN STD_ULOGIC;
43 HRESETn : IN STD_ULOGIC;
44 DMAIn : OUT DMA_In_Type;
45 DMAOut : IN DMA_OUt_Type;
46 send : IN STD_LOGIC;
47 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 ren : OUT STD_LOGIC;
50 send_ok : OUT STD_LOGIC;
51 send_ko : OUT STD_LOGIC);
52 END COMPONENT;
53
54 COMPONENT lpp_dma_send_16word_LPP_JCP
55 PORT (
56 HCLK : IN STD_ULOGIC;
57 HRESETn : IN STD_ULOGIC;
58 DMAIn : OUT DMA_In_Type;
59 DMAOut : IN DMA_OUt_Type;
60 send : IN STD_LOGIC;
61 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 ren : OUT STD_LOGIC;
64 send_ok : OUT STD_LOGIC;
65 send_ko : OUT STD_LOGIC);
66 END COMPONENT;
67
68 END;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34
35 ENTITY lpp_dma_send_16word_LPP_JCP IS
36 PORT (
37 -- AMBA AHB system signals
38 HCLK : IN STD_ULOGIC;
39 HRESETn : IN STD_ULOGIC;
40
41 -- DMA
42 DMAIn : OUT DMA_In_Type;
43 DMAOut : IN DMA_OUt_Type;
44
45 --
46 send : IN STD_LOGIC;
47 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 ren : OUT STD_LOGIC;
50 --
51 send_ok : OUT STD_LOGIC;
52 send_ko : OUT STD_LOGIC
53
54 );
55 END lpp_dma_send_16word_LPP_JCP;
56
57 ARCHITECTURE beh OF lpp_dma_send_16word_LPP_JCP IS
58
59 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
60 SIGNAL state : state_fsm_send_16word;
61
62 SIGNAL data_counter : INTEGER;
63 SIGNAL grant_counter : INTEGER;
64
65 BEGIN -- beh
66
67 DMAIn.Beat <= HINCR16;
68 DMAIn.Size <= HSIZE32;
69
70 PROCESS (HCLK, HRESETn)
71 BEGIN -- PROCESS
72 IF HRESETn = '0' THEN -- asynchronous reset (active low)
73 state <= IDLE;
74 send_ok <= '0';
75 send_ko <= '0';
76
77 DMAIn.Reset <= '1';
78 DMAIn.Address <= (OTHERS => '0');
79 DMAIn.Request <= '0';
80 DMAIn.Store <= '0';
81 DMAIn.Burst <= '1';
82 DMAIn.Lock <= '0';
83 data_counter <= 0;
84 grant_counter <= 0;
85 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
86
87 DMAIn.Reset <= '0';
88
89 CASE state IS
90 WHEN IDLE =>
91 DMAIn.Store <= '1';
92 DMAIn.Request <= '0';
93 send_ok <= '0';
94 send_ko <= '0';
95 DMAIn.Address <= address;
96 data_counter <= 0;
97 DMAIn.Lock <= '0'; -- FIX test
98 IF send = '1' THEN
99 state <= REQUEST_BUS;
100 DMAIn.Request <= '1';
101 DMAIn.Lock <= '1'; -- FIX test
102 DMAIn.Store <= '1';
103 END IF;
104 WHEN REQUEST_BUS =>
105 IF DMAOut.Grant = '1' THEN
106 data_counter <= 1;
107 grant_counter <= 1;
108 state <= SEND_DATA;
109 END IF;
110 WHEN SEND_DATA =>
111
112 IF DMAOut.Fault = '1' THEN
113 DMAIn.Reset <= '0';
114 DMAIn.Address <= (OTHERS => '0');
115 DMAIn.Request <= '0';
116 DMAIn.Store <= '0';
117 DMAIn.Burst <= '0';
118 state <= ERROR0;
119 ELSE
120
121 IF DMAOut.Grant = '1' THEN
122 IF grant_counter = 15 THEN
123 DMAIn.Reset <= '0';
124 DMAIn.Request <= '0';
125 DMAIn.Store <= '0';
126 DMAIn.Burst <= '0';
127 ELSE
128 grant_counter <= grant_counter+1;
129 END IF;
130 END IF;
131
132 IF DMAOut.OKAY = '1' THEN
133 IF data_counter = 15 THEN
134 DMAIn.Address <= (OTHERS => '0');
135 state <= WAIT_LAST_READY;
136 ELSE
137 data_counter <= data_counter + 1;
138 END IF;
139 END IF;
140 END IF;
141
142
143 WHEN WAIT_LAST_READY =>
144 IF DMAOut.Ready = '1' THEN
145 IF grant_counter = 15 THEN
146 state <= IDLE;
147 send_ok <= '1';
148 send_ko <= '0';
149 ELSE
150 state <= ERROR0;
151 END IF;
152 END IF;
153
154 WHEN ERROR0 =>
155 state <= ERROR1;
156 WHEN ERROR1 =>
157 send_ok <= '0';
158 send_ko <= '1';
159 state <= IDLE;
160 WHEN OTHERS => NULL;
161 END CASE;
162 END IF;
163 END PROCESS;
164
165 DMAIn.Data <= data;
166
167 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
168 '1';
169
170 -- \/ JC - 20/01/2014 \/
171 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
172 -- '1';
173 -- /\ JC - 20/01/2014 /\
174
175 -- \/ JC - 11/12/2013 \/
176 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
177 -- '1';
178 -- /\ JC - 11/12/2013 /\
179
180 -- \/ JC - 10/12/2013 \/
181 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
182 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
183 -- '1';
184 -- /\ JC - 10/12/2013 /\
185
186 -- \/ JC - 09/12/2013 \/
187 --ren <= '0' WHEN state = SEND_DATA ELSE
188 -- '1';
189 -- /\ JC - 09/12/2013 /\
190
191 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
27
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
32 USE GRLIB.DMA2AHB_Package.ALL;
33
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_dma_send_1word_LPP_JCP IS
38 PORT (
39 -- AMBA AHB system signals
40 HCLK : IN STD_ULOGIC;
41 HRESETn : IN STD_ULOGIC;
42
43 -- DMA
44 DMAIn : OUT DMA_In_Type;
45 DMAOut : IN DMA_OUt_Type;
46 --
47 send : IN STD_LOGIC;
48 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 ren : OUT STD_LOGIC;
51 --
52 send_ok : OUT STD_LOGIC;
53 send_ko : OUT STD_LOGIC
54 );
55 END lpp_dma_send_1word_LPP_JCP;
56
57 ARCHITECTURE beh OF lpp_dma_send_1word_LPP_JCP IS
58
59 TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1);
60 SIGNAL state : state_fsm_send_1word;
61
62 BEGIN -- beh
63
64 DMAIn.Reset <= '0';
65 DMAIn.Address <= address;
66 DMAIn.Data <= data;
67 DMAIn.Beat <= (OTHERS => '0');
68 DMAIn.Size <= HSIZE32;
69 DMAIn.Burst <= '0';
70
71 PROCESS (HCLK, HRESETn)
72 BEGIN -- PROCESS
73 IF HRESETn = '0' THEN -- asynchronous reset (active low)
74 state <= IDLE;
75 DMAIn.Request <= '0';
76 DMAIn.Store <= '0';
77 send_ok <= '0';
78 send_ko <= '0';
79 DMAIn.Lock <= '0';
80 ren <= '1';
81 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
82 ren <= '1';
83 CASE state IS
84 WHEN IDLE =>
85 DMAIn.Store <= '1';
86 DMAIn.Request <= '0';
87 send_ok <= '0';
88 send_ko <= '0';
89 DMAIn.Lock <= '0';
90 IF send = '1' THEN
91 DMAIn.Request <= '1';
92 DMAIn.Lock <= '1';
93 state <= REQUEST_BUS;
94 END IF;
95 WHEN REQUEST_BUS =>
96 IF DMAOut.Grant = '1' THEN
97 DMAIn.Request <= '0';
98 DMAIn.Store <= '0';
99 state <= SEND_DATA;
100 ren <= '0';
101 END IF;
102 WHEN SEND_DATA =>
103 IF DMAOut.Fault = '1' THEN
104 DMAIn.Request <= '0';
105 DMAIn.Store <= '0';
106 state <= ERROR0;
107 ELSIF DMAOut.Ready = '1' THEN
108 DMAIn.Request <= '0';
109 DMAIn.Store <= '0';
110 send_ok <= '1';
111 send_ko <= '0';
112 state <= IDLE;
113 END IF;
114 WHEN ERROR0 =>
115 state <= ERROR1;
116 WHEN ERROR1 =>
117 send_ok <= '0';
118 send_ko <= '1';
119 state <= IDLE;
120 WHEN OTHERS => NULL;
121 END CASE;
122 END IF;
123 END PROCESS;
124
125 END beh;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 LIBRARY staging;
40 USE staging.lpp_dma_pkg_LPP_JCP.ALL;
41
42
43 ENTITY lpp_dma_singleOrBurst_LPP_JCP IS
44 GENERIC (
45 tech : INTEGER := inferred;
46 hindex : INTEGER := 2
47 );
48 PORT (
49 -- AMBA AHB system signals
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 --
53 run : IN STD_LOGIC;
54 -- AMBA AHB Master Interface
55 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 --
58 send : IN STD_LOGIC;
59 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
60 done : OUT STD_LOGIC;
61 ren : OUT STD_LOGIC;
62 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 --
65 debug_dmaout_okay : OUT STD_LOGIC
66
67 );
68 END;
69
70 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst_LPP_JCP IS
71 -----------------------------------------------------------------------------
72 SIGNAL DMAIn : DMA_In_Type;
73 SIGNAL DMAOut : DMA_OUt_Type;
74 -----------------------------------------------------------------------------
75 -----------------------------------------------------------------------------
76 -- CONTROL
77 SIGNAL single_send : STD_LOGIC;
78 SIGNAL burst_send : STD_LOGIC;
79
80 -----------------------------------------------------------------------------
81 -- SEND SINGLE MODULE
82 SIGNAL single_dmai : DMA_In_Type;
83
84 SIGNAL single_send_ok : STD_LOGIC;
85 SIGNAL single_send_ko : STD_LOGIC;
86 SIGNAL single_ren : STD_LOGIC;
87 -----------------------------------------------------------------------------
88 -- SEND SINGLE MODULE
89 SIGNAL burst_dmai : DMA_In_Type;
90
91 SIGNAL burst_send_ok : STD_LOGIC;
92 SIGNAL burst_send_ko : STD_LOGIC;
93 SIGNAL burst_ren : STD_LOGIC;
94 -----------------------------------------------------------------------------
95 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 -----------------------------------------------------------------------------
97 SIGNAL send_reg : STD_LOGIC;
98 SIGNAL send_s : STD_LOGIC;
99
100
101 BEGIN
102
103 debug_dmaout_okay <= DMAOut.OKAY;
104
105
106 -----------------------------------------------------------------------------
107 -- DMA to AHB interface
108 DMA2AHB_1 : DMA2AHB
109 GENERIC MAP (
110 hindex => hindex,
111 vendorid => VENDOR_LPP,
112 deviceid => 10,
113 version => 0,
114 syncrst => 1,
115 boundary => 1)
116 PORT MAP (
117 HCLK => HCLK,
118 HRESETn => HRESETn,
119 DMAIn => DMAIn,
120 DMAOut => DMAOut,
121
122 AHBIn => AHB_Master_In,
123 AHBOut => AHB_Master_Out);
124 -----------------------------------------------------------------------------
125
126 -----------------------------------------------------------------------------
127 PROCESS (HCLK, HRESETn)
128 BEGIN
129 IF HRESETn = '0' THEN
130 send_reg <= '0';
131 ELSIF HCLK'event AND HCLK = '1' THEN
132 send_reg <= send;
133 END IF;
134 END PROCESS;
135 send_s <= send_reg;
136
137 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
138 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
139
140 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
141
142 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
143
144 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 single_ren;
146
147
148 -----------------------------------------------------------------------------
149 -- SEND 1 word by DMA
150 -----------------------------------------------------------------------------
151 lpp_dma_send_1word_1 : lpp_dma_send_1word_LPP_JCP
152 PORT MAP (
153 HCLK => HCLK,
154 HRESETn => HRESETn,
155 DMAIn => single_dmai,
156 DMAOut => DMAOut,
157
158 send => single_send,
159 address => address,
160 data => data_2_halfword,
161 ren => single_ren,
162
163 send_ok => single_send_ok,
164 send_ko => single_send_ko
165 );
166
167 -----------------------------------------------------------------------------
168 -- SEND 16 word by DMA (in burst mode)
169 -----------------------------------------------------------------------------
170 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
171
172 lpp_dma_send_16word_1 : lpp_dma_send_16word_LPP_JCP
173 PORT MAP (
174 HCLK => HCLK,
175 HRESETn => HRESETn,
176 DMAIn => burst_dmai,
177 DMAOut => DMAOut,
178
179 send => burst_send,
180 address => address,
181 data => data_2_halfword,
182 ren => burst_ren,
183
184 send_ok => burst_send_ok,
185 send_ko => burst_send_ko);
186
187 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30
31 LIBRARY staging;
32 USE staging.sample_type.ALL;
33
34 PACKAGE AMBA_Peripherals_LPP_JCP IS
35
36 COMPONENT apb_lfr_time_management_LPP_JCP IS
37 GENERIC(
38 pindex : INTEGER := 0; --! APB slave index
39 paddr : INTEGER := 0; --! ADDR field of the APB BAR
40 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
41 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
42 nb_wait_period : INTEGER := 375 --! nb perdiod at clk49_152MHz
43 -- to wait before incremented the
44 -- fine time counter
45 );
46 PORT (
47 clk25MHz : IN STD_LOGIC; --! Clock
48 clk49_152MHz : IN STD_LOGIC; --! secondary clock
49 resetn : IN STD_LOGIC; --! Reset
50 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
51 apbi : IN apb_slv_in_type; --! APB slave input signals
52 apbo : OUT apb_slv_out_type; --! APB slave output signals
53 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
54 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
55 );
56 END COMPONENT;
57
58 COMPONENT lpp_lfr_LPP_JCP
59 GENERIC (
60 Mem_use : INTEGER;
61 nb_data_by_buffer_size : INTEGER;
62 nb_word_by_buffer_size : INTEGER;
63 nb_snapshot_param_size : INTEGER;
64 delta_vector_size : INTEGER;
65 delta_vector_size_f0_2 : INTEGER;
66 pindex : INTEGER;
67 paddr : INTEGER;
68 pmask : INTEGER;
69 pirq_ms : INTEGER;
70 pirq_wfp : INTEGER;
71 hindex : INTEGER;
72 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
73 PORT (
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 sample_B : IN Samples14v(2 DOWNTO 0);
77 sample_E : IN Samples14v(4 DOWNTO 0);
78 sample_val : IN STD_LOGIC;
79 apbi : IN apb_slv_in_type;
80 apbo : OUT apb_slv_out_type;
81 ahbi : IN AHB_Mst_In_Type;
82 ahbo : OUT AHB_Mst_Out_Type;
83 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
85 data_shaping_BW : OUT STD_LOGIC;
86 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
87 END COMPONENT;
88
89 COMPONENT lpp_dma_singleOrBurst_LPP_JCP
90 GENERIC (
91 tech : INTEGER;
92 hindex : INTEGER);
93 PORT (
94 HCLK : IN STD_ULOGIC;
95 HRESETn : IN STD_ULOGIC;
96 run : IN STD_LOGIC;
97 AHB_Master_In : IN AHB_Mst_In_Type;
98 AHB_Master_Out : OUT AHB_Mst_Out_Type;
99 send : IN STD_LOGIC;
100 valid_burst : IN STD_LOGIC;
101 done : OUT STD_LOGIC;
102 ren : OUT STD_LOGIC;
103 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 debug_dmaout_okay : OUT STD_LOGIC);
106 END COMPONENT;
107
108 END;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
32
33 LIBRARY staging;
34 USE staging.apb_devices_list_LPP_JCP.ALL;
35 USE staging.general_purpose_LPP_JCP.ALL;
36 USE staging.lpp_lfr_time_management_LPP_JCP.ALL;
37
38 ENTITY apb_lfr_time_management_LPP_JCP IS
39
40 GENERIC(
41 pindex : INTEGER := 0; --! APB slave index
42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
45 nb_wait_period : INTEGER := 375
46 );
47
48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
50 clk49_152MHz : IN STD_LOGIC; --! secondary clock
51 resetn : IN STD_LOGIC; --! Reset
52
53 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54 apbi : IN apb_slv_in_type; --! APB slave input signals
55 apbo : OUT apb_slv_out_type; --! APB slave output signals
56 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
57 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
58 );
59
60 END apb_lfr_time_management_LPP_JCP;
61
62 ARCHITECTURE Behavioral OF apb_lfr_time_management_LPP_JCP IS
63
64 CONSTANT REVISION : INTEGER := 1;
65 CONSTANT pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
67 1 => apb_iobar(paddr, pmask)
68 );
69
70 TYPE apb_lfr_time_management_Reg IS RECORD
71 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
75 END RECORD;
76
77 SIGNAL r : apb_lfr_time_management_Reg;
78 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 SIGNAL force_tick : STD_LOGIC;
80 SIGNAL previous_force_tick : STD_LOGIC;
81 SIGNAL soft_tick : STD_LOGIC;
82
83 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
85
86 SIGNAL coarsetime_reg_updated : STD_LOGIC;
87 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
88
89 SIGNAL coarse_time_new : STD_LOGIC;
90 SIGNAL coarse_time_new_49 : STD_LOGIC;
91 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
92 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
93
94 SIGNAL fine_time_new : STD_LOGIC;
95 SIGNAL fine_time_new_temp : STD_LOGIC;
96 SIGNAL fine_time_new_49 : STD_LOGIC;
97 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL tick : STD_LOGIC;
100 SIGNAL new_timecode : STD_LOGIC;
101 SIGNAL new_coarsetime : STD_LOGIC;
102
103 BEGIN
104 -----------------------------------------------------------------------------
105 -- TODO
106 -- IRQ 1 & 2
107 -----------------------------------------------------------------------------
108 irq2 <= '0';
109 irq1 <= '0';
110
111 apbo.pirq(pirq) <= irq1;
112 apbo.pirq(pirq+1) <= irq2;
113
114 PROCESS(resetn, clk25MHz)
115 BEGIN
116
117 IF resetn = '0' THEN
118 Rdata <= (OTHERS => '0');
119 r.coarse_time_load <= x"80000000";
120 r.ctrl <= x"00000000";
121 force_tick <= '0';
122 previous_force_tick <= '0';
123 soft_tick <= '0';
124
125 coarsetime_reg_updated <= '0';
126
127 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
128 coarsetime_reg_updated <= '0';
129
130 force_tick <= r.ctrl(0);
131 previous_force_tick <= force_tick;
132 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
133 soft_tick <= '1';
134 ELSE
135 soft_tick <= '0';
136 END IF;
137
138 --APB Write OP
139 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
140 CASE apbi.paddr(7 DOWNTO 2) IS
141 WHEN "000000" =>
142 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
143 WHEN "000001" =>
144 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
145 coarsetime_reg_updated <= '1';
146 WHEN OTHERS =>
147 END CASE;
148 ELSIF r.ctrl(0) = '1' THEN
149 r.ctrl(0) <= '0';
150 END IF;
151
152 --APB READ OP
153 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
154 CASE apbi.paddr(7 DOWNTO 2) IS
155 WHEN "000000" =>
156 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
157 WHEN "000001" =>
158 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
159 WHEN "000010" =>
160 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
161 WHEN "000011" =>
162 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
163 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
164 WHEN OTHERS =>
165 Rdata(31 DOWNTO 0) <= x"00000000";
166 END CASE;
167 END IF;
168
169 END IF;
170 END PROCESS;
171
172 apbo.prdata <= Rdata;
173 apbo.pconfig <= pconfig;
174 apbo.pindex <= pindex;
175
176 coarse_time <= r.coarse_time;
177 fine_time <= r.fine_time;
178 -----------------------------------------------------------------------------
179
180 coarsetime_reg <= r.coarse_time_load;
181 r.coarse_time <= coarse_time_s;
182 r.fine_time <= fine_time_s;
183 -----------------------------------------------------------------------------
184
185 tick <= grspw_tick OR soft_tick;
186
187 SYNC_VALID_BI_1 : SYNC_VALID_BIT_LPP_JCP
188 GENERIC MAP (
189 NB_FF_OF_SYNC => 2)
190 PORT MAP (
191 clk_in => clk25MHz,
192 clk_out => clk49_152MHz,
193 rstn => resetn,
194 sin => tick,
195 sout => new_timecode);
196
197 SYNC_VALID_BIT_2 : SYNC_VALID_BIT_LPP_JCP
198 GENERIC MAP (
199 NB_FF_OF_SYNC => 2)
200 PORT MAP (
201 clk_in => clk25MHz,
202 clk_out => clk49_152MHz,
203 rstn => resetn,
204 sin => coarsetime_reg_updated,
205 sout => new_coarsetime);
206
207 SYNC_FF_1 : SYNC_FF_LPP_JCP
208 GENERIC MAP (
209 NB_FF_OF_SYNC => 2)
210 PORT MAP (
211 clk => clk25MHz,
212 rstn => resetn,
213 A => fine_time_new_49,
214 A_sync => fine_time_new_temp);
215
216 lpp_edge_detection_1 : lpp_edge_detection_LPP_JCP
217 PORT MAP (
218 clk => clk25MHz,
219 rstn => resetn,
220 sin => fine_time_new_temp,
221 sout => fine_time_new);
222
223 SYNC_VALID_BIT_4 : SYNC_VALID_BIT_LPP_JCP
224 GENERIC MAP (
225 NB_FF_OF_SYNC => 2)
226 PORT MAP (
227 clk_in => clk49_152MHz,
228 clk_out => clk25MHz,
229 rstn => resetn,
230 sin => coarse_time_new_49,
231 sout => coarse_time_new);
232
233 PROCESS (clk25MHz, resetn)
234 BEGIN -- PROCESS
235 IF resetn = '0' THEN -- asynchronous reset (active low)
236 fine_time_s <= (OTHERS => '0');
237 coarse_time_s <= (OTHERS => '0');
238 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
239 IF fine_time_new = '1' THEN
240 fine_time_s <= fine_time_49;
241 END IF;
242 IF coarse_time_new = '1' THEN
243 coarse_time_s <= coarse_time_49;
244 END IF;
245 END IF;
246 END PROCESS;
247
248 -----------------------------------------------------------------------------
249 -- LFR_TIME_MANAGMENT
250 -----------------------------------------------------------------------------
251 lfr_time_management_1 : lfr_time_management_LPP_JCP
252 GENERIC MAP (
253 nb_time_code_missing_limit => 60,
254 nb_wait_period => 375)
255 PORT MAP (
256 clk => clk49_152MHz,
257 rstn => resetn,
258
259 new_timecode => new_timecode,
260 new_coarsetime => new_coarsetime,
261 coarsetime_reg => coarsetime_reg,
262
263 fine_time => fine_time_49,
264 fine_time_new => fine_time_new_49,
265 coarse_time => coarse_time_49,
266 coarse_time_new => coarse_time_new_49);
267
268 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27 LIBRARY staging;
28 USE staging.lpp_lfr_time_management_LPP_JCP.ALL;
29
30 ENTITY lfr_time_management_LPP_JCP IS
31 GENERIC (
32 nb_time_code_missing_limit : INTEGER := 60;
33 nb_wait_pediod : INTEGER := 375
34 );
35 PORT (
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38
39 new_timecode : IN STD_LOGIC; -- transition signal information
40 new_coarsetime : IN STD_LOGIC; -- transition signal information
41 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
42
43 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
44 fine_time_new : OUT STD_LOGIC;
45 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 coarse_time_new : OUT STD_LOGIC
47 );
48 END lfr_time_management_LPP_JCP;
49
50 ARCHITECTURE Behavioral OF lfr_time_management_LPP_JCP IS
51
52 SIGNAL counter_clear : STD_LOGIC;
53 SIGNAL counter_full : STD_LOGIC;
54
55 SIGNAL nb_time_code_missing : INTEGER;
56 SIGNAL coarse_time_s : INTEGER;
57
58 SIGNAL new_coarsetime_s : STD_LOGIC;
59
60 BEGIN
61
62 lpp_counter_1 : lpp_counter_LPP_JCP
63 GENERIC MAP (
64 nb_wait_period => nb_wait_pediod,
65 nb_bit_of_data => 16)
66 PORT MAP (
67 clk => clk,
68 rstn => rstn,
69 clear => counter_clear,
70 full => counter_full,
71 data => fine_time,
72 new_data => fine_time_new);
73
74 PROCESS (clk, rstn)
75 BEGIN -- PROCESS
76 IF rstn = '0' THEN -- asynchronous reset (active low)
77 nb_time_code_missing <= 0;
78 counter_clear <= '0';
79 coarse_time_s <= 0;
80 coarse_time_new <= '0';
81 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
82 IF new_coarsetime = '1' THEN
83 new_coarsetime_s <= '1';
84 ELSIF new_timecode = '1' THEN
85 new_coarsetime_s <= '0';
86 END IF;
87
88 IF new_timecode = '1' THEN
89 coarse_time_new <= '1';
90 IF new_coarsetime_s = '1' THEN
91 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
92 ELSE
93 coarse_time_s <= coarse_time_s + 1;
94 END IF;
95 nb_time_code_missing <= 0;
96 counter_clear <= '1';
97 ELSE
98 coarse_time_new <= '0';
99 counter_clear <= '0';
100 IF counter_full = '1' THEN
101 coarse_time_new <= '1';
102 coarse_time_s <= coarse_time_s + 1;
103 IF nb_time_code_missing = nb_time_code_missing_limit THEN
104 nb_time_code_missing <= nb_time_code_missing_limit;
105 ELSE
106 nb_time_code_missing <= nb_time_code_missing + 1;
107 END IF;
108 END IF;
109 END IF;
110 END IF;
111 END PROCESS;
112
113 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
114 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
115
116 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.NUMERIC_STD.ALL;
27
28 ENTITY lpp_counter_LPP_JCP IS
29
30 GENERIC (
31 nb_wait_period : INTEGER := 750;
32 nb_bit_of_data : INTEGER := 16
33 );
34 PORT (
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 clear : IN STD_LOGIC;
38 full : OUT STD_LOGIC;
39 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
40 new_data : OUT STD_LOGIC
41 );
42
43 END lpp_counter_LPP_JCP;
44
45 ARCHITECTURE beh OF lpp_counter_LPP_JCP IS
46
47 SIGNAL counter_wait : INTEGER;
48 SIGNAL counter_data : INTEGER;
49
50 SIGNAL new_data_s : STD_LOGIC;
51 BEGIN -- beh
52
53 PROCESS (clk, rstn)
54 BEGIN -- PROCESS
55 IF rstn = '0' THEN -- asynchronous reset (active low)
56 counter_wait <= 0;
57 counter_data <= 0;
58 full <= '0';
59 new_data_s <= '0';
60 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
61 IF clear = '1' THEN
62 counter_wait <= 0;
63 counter_data <= 0;
64 full <= '0';
65 new_data_s <= NOT new_data_s;
66 ELSE
67 IF counter_wait = nb_wait_period-1 THEN
68 counter_wait <= 0;
69 new_data_s <= NOT new_data_s;
70 IF counter_data = (2**nb_bit_of_data)-1 THEN
71 full <= '1';
72 counter_data <= 0;
73 ELSE
74 full <= '0';
75 counter_data <= counter_data +1;
76 END IF;
77 ELSE
78 full <= '0';
79 counter_wait <= counter_wait +1;
80 END IF;
81 END IF;
82 END IF;
83 END PROCESS;
84
85 data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data));
86 new_data <= new_data_s;
87
88 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30
31 PACKAGE lpp_lfr_time_management_LPP_JCP IS
32
33 COMPONENT lfr_time_management_LPP_JCP
34 GENERIC (
35 nb_time_code_missing_limit : INTEGER;
36 nb_wait_pediod : INTEGER := 375);
37 PORT (
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 new_timecode : IN STD_LOGIC;
41 new_coarsetime : IN STD_LOGIC;
42 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
43 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
44 fine_time_new : OUT STD_LOGIC;
45 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 coarse_time_new : OUT STD_LOGIC
47 );
48 END COMPONENT;
49
50 COMPONENT lpp_counter_LPP_JCP
51 GENERIC (
52 nb_wait_period : INTEGER;
53 nb_bit_of_data : INTEGER);
54 PORT (
55 clk : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
57 clear : IN STD_LOGIC;
58 full : OUT STD_LOGIC;
59 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
60 new_data : OUT STD_LOGIC);
61 END COMPONENT;
62
63 END lpp_lfr_time_management__LPP_JCP;
64
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY staging;
34 USE staging.lpp_waveform_pkg_LPP_JCP.ALL;
35 USE staging.general_purpose_LPP_JCP.ALL;
36
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
39
40 ENTITY lpp_waveform_LPP_JCP IS
41
42 GENERIC (
43 tech : INTEGER := inferred;
44 data_size : INTEGER := 96; --16*6
45 nb_data_by_buffer_size : INTEGER := 11;
46 nb_word_by_buffer_size : INTEGER := 11;
47 nb_snapshot_param_size : INTEGER := 11;
48 delta_vector_size : INTEGER := 20;
49 delta_vector_size_f0_2 : INTEGER := 3);
50
51 PORT (
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
55 ---- AMBA AHB Master Interface
56 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
57 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
58
59 --config
60 reg_run : IN STD_LOGIC;
61 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
62 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
65 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
67
68 enable_f0 : IN STD_LOGIC;
69 enable_f1 : IN STD_LOGIC;
70 enable_f2 : IN STD_LOGIC;
71 enable_f3 : IN STD_LOGIC;
72
73 burst_f0 : IN STD_LOGIC;
74 burst_f1 : IN STD_LOGIC;
75 burst_f2 : IN STD_LOGIC;
76
77 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
78 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
79 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
80 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
83 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
84 ---------------------------------------------------------------------------
85 -- INPUT
86 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
87 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
88
89 --f0
90 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91 data_f0_in_valid : IN STD_LOGIC;
92 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
93 --f1
94 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
95 data_f1_in_valid : IN STD_LOGIC;
96 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
97 --f2
98 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
99 data_f2_in_valid : IN STD_LOGIC;
100 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
101 --f3
102 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 data_f3_in_valid : IN STD_LOGIC;
104 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105
106 ---------------------------------------------------------------------------
107 -- OUTPUT
108 --f0
109 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
111 data_f0_data_out_valid : OUT STD_LOGIC;
112 data_f0_data_out_valid_burst : OUT STD_LOGIC;
113 data_f0_data_out_ren : IN STD_LOGIC;
114 --f1
115 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 data_f1_data_out_valid : OUT STD_LOGIC;
118 data_f1_data_out_valid_burst : OUT STD_LOGIC;
119 data_f1_data_out_ren : IN STD_LOGIC;
120 --f2
121 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data_f2_data_out_valid : OUT STD_LOGIC;
124 data_f2_data_out_valid_burst : OUT STD_LOGIC;
125 data_f2_data_out_ren : IN STD_LOGIC;
126 --f3
127 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 data_f3_data_out_valid : OUT STD_LOGIC;
130 data_f3_data_out_valid_burst : OUT STD_LOGIC;
131 data_f3_data_out_ren : IN STD_LOGIC;
132
133 ---------------------------------------------------------------------------
134 --
135 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
136 );
137
138 END lpp_waveform_LPP_JCP;
139
140 ARCHITECTURE beh OF lpp_waveform_LPP_JCP IS
141 SIGNAL start_snapshot_f0 : STD_LOGIC;
142 SIGNAL start_snapshot_f1 : STD_LOGIC;
143 SIGNAL start_snapshot_f2 : STD_LOGIC;
144
145 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
148 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149
150 SIGNAL data_f0_out_valid : STD_LOGIC;
151 SIGNAL data_f1_out_valid : STD_LOGIC;
152 SIGNAL data_f2_out_valid : STD_LOGIC;
153 SIGNAL data_f3_out_valid : STD_LOGIC;
154 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
155 --
156 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 --
170 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 --
175 SIGNAL run : STD_LOGIC;
176 --
177 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
178 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
179 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
180 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
181 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
182 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
183 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
184 --
185
186 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
187 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
188 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
190
191 --
192
193 SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
195
196 BEGIN -- beh
197
198 -----------------------------------------------------------------------------
199 -- DEBUG
200 -----------------------------------------------------------------------------
201 PROCESS (clk, rstn)
202 BEGIN -- PROCESS
203 IF rstn = '0' THEN -- asynchronous reset (active low)
204 observation_reg <= (OTHERS => '0');
205 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
206 observation_reg <= observation_reg_s;
207 END IF;
208 END PROCESS;
209 observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0;
210 observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
211 observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ;
212 observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0);
213 observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0);
214 observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
215 -----------------------------------------------------------------------------
216
217 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler_LPP_JCP
218 GENERIC MAP (
219 delta_vector_size => delta_vector_size,
220 delta_vector_size_f0_2 => delta_vector_size_f0_2
221 )
222 PORT MAP (
223 clk => clk,
224 rstn => rstn,
225 reg_run => reg_run,
226 reg_start_date => reg_start_date,
227 reg_delta_snapshot => reg_delta_snapshot,
228 reg_delta_f0 => reg_delta_f0,
229 reg_delta_f0_2 => reg_delta_f0_2,
230 reg_delta_f1 => reg_delta_f1,
231 reg_delta_f2 => reg_delta_f2,
232 coarse_time => coarse_time(30 DOWNTO 0),
233 data_f0_valid => data_f0_in_valid,
234 data_f2_valid => data_f2_in_valid,
235 start_snapshot_f0 => start_snapshot_f0,
236 start_snapshot_f1 => start_snapshot_f1,
237 start_snapshot_f2 => start_snapshot_f2,
238 wfp_on => run);
239
240 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_LPP_JCP
241 GENERIC MAP (
242 data_size => data_size,
243 nb_snapshot_param_size => nb_snapshot_param_size)
244 PORT MAP (
245 clk => clk,
246 rstn => rstn,
247 run => run,
248 enable => enable_f0,
249 burst_enable => burst_f0,
250 nb_snapshot_param => nb_snapshot_param,
251 start_snapshot => start_snapshot_f0,
252 data_in => data_f0_in,
253 data_in_valid => data_f0_in_valid,
254 data_out => data_f0_out,
255 data_out_valid => data_f0_out_valid);
256
257 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
258
259 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot_LPP_JCP
260 GENERIC MAP (
261 data_size => data_size,
262 nb_snapshot_param_size => nb_snapshot_param_size+1)
263 PORT MAP (
264 clk => clk,
265 rstn => rstn,
266 run => run,
267 enable => enable_f1,
268 burst_enable => burst_f1,
269 nb_snapshot_param => nb_snapshot_param_more_one,
270 start_snapshot => start_snapshot_f1,
271 data_in => data_f1_in,
272 data_in_valid => data_f1_in_valid,
273 data_out => data_f1_out,
274 data_out_valid => data_f1_out_valid);
275
276 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot_LPP_JCP
277 GENERIC MAP (
278 data_size => data_size,
279 nb_snapshot_param_size => nb_snapshot_param_size+1)
280 PORT MAP (
281 clk => clk,
282 rstn => rstn,
283 run => run,
284 enable => enable_f2,
285 burst_enable => burst_f2,
286 nb_snapshot_param => nb_snapshot_param_more_one,
287 start_snapshot => start_snapshot_f2,
288 data_in => data_f2_in,
289 data_in_valid => data_f2_in_valid,
290 data_out => data_f2_out,
291 data_out_valid => data_f2_out_valid);
292
293 lpp_waveform_burst_f3 : lpp_waveform_burst_LPP_JCP
294 GENERIC MAP (
295 data_size => data_size)
296 PORT MAP (
297 clk => clk,
298 rstn => rstn,
299 run => run,
300 enable => enable_f3,
301 data_in => data_f3_in,
302 data_in_valid => data_f3_in_valid,
303 data_out => data_f3_out,
304 data_out_valid => data_f3_out_valid);
305 -----------------------------------------------------------------------------
306
307 PROCESS (clk, rstn)
308 BEGIN -- PROCESS
309 IF rstn = '0' THEN -- asynchronous reset (active low)
310 time_reg1 <= (OTHERS => '0');
311 time_reg2 <= (OTHERS => '0');
312 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
313 time_reg1 <= fine_time & coarse_time;
314 time_reg2 <= time_reg1;
315 END IF;
316 END PROCESS;
317
318 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
319 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
320 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid_LPP_JCP
321 PORT MAP (
322 HCLK => clk,
323 HRESETn => rstn,
324 run => run,
325 valid_in => valid_in(I),
326 ack_in => valid_ack(I),
327 time_in => time_reg2, -- Todo
328 valid_out => valid_out(I),
329 time_out => time_out(I), -- Todo
330 error => status_new_err(I));
331 END GENERATE all_input_valid;
332
333 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
334 data_out(0, I) <= data_f0_out(I);
335 data_out(1, I) <= data_f1_out(I);
336 data_out(2, I) <= data_f2_out(I);
337 data_out(3, I) <= data_f3_out(I);
338 END GENERATE all_bit_of_data_out;
339
340 -----------------------------------------------------------------------------
341 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
342 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
343 time_out_2(J, I) <= time_out(J)(I);
344 END GENERATE all_sample_of_time_out;
345 END GENERATE all_bit_of_time_out;
346
347 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter_LPP_JCP
348 GENERIC MAP (tech => tech,
349 nb_data_by_buffer_size => nb_data_by_buffer_size)
350 PORT MAP (
351 clk => clk,
352 rstn => rstn,
353 run => run,
354 nb_data_by_buffer => nb_data_by_buffer,
355 data_in_valid => valid_out,
356 data_in_ack => valid_ack,
357 data_in => data_out,
358 time_in => time_out_2,
359
360 data_out => wdata,
361 data_out_wen => data_wen,
362 full_almost => full_almost,
363 full => full);
364
365 -----------------------------------------------------------------------------
366
367 lpp_waveform_fifo_1 : FIFO_shared_memory_4channel_LPP_JCP
368 GENERIC MAP (tech => tech)
369 PORT MAP (
370 clk => clk,
371 rstn => rstn,
372 run => run,
373
374 empty => s_empty,
375 empty_almost => s_empty_almost,
376 data_ren => s_data_ren,
377 rdata => s_rdata,
378
379
380 full_almost => full_almost,
381 full => full,
382 data_wen => data_wen,
383 wdata => wdata);
384
385 lpp_waveform_fifo_headreg_1 : FIFO_shared_memory_4channel_headreg_LPP_JCP
386 GENERIC MAP (tech => tech)
387 PORT MAP (
388 clk => clk,
389 rstn => rstn,
390 run => run,
391 o_empty_almost => empty_almost,
392 o_empty => empty,
393
394 o_data_ren => data_ren,
395 o_rdata_0 => data_f0_data_out,
396 o_rdata_1 => data_f1_data_out,
397 o_rdata_2 => data_f2_data_out,
398 o_rdata_3 => data_f3_data_out,
399
400 i_empty_almost => s_empty_almost,
401 i_empty => s_empty,
402 i_data_ren => s_data_ren,
403 i_rdata => s_rdata);
404
405 data_ren <= data_f3_data_out_ren &
406 data_f2_data_out_ren &
407 data_f1_data_out_ren &
408 data_f0_data_out_ren;
409
410 lpp_waveform_gen_address_1 : lpp_waveform_genaddress_LPP_JCP
411 GENERIC MAP (
412 nb_data_by_buffer_size => nb_word_by_buffer_size)
413 PORT MAP (
414 clk => clk,
415 rstn => rstn,
416 run => run,
417
418 -------------------------------------------------------------------------
419 -- CONFIG
420 -------------------------------------------------------------------------
421 nb_data_by_buffer => nb_word_by_buffer,
422
423 addr_data_f0 => addr_data_f0,
424 addr_data_f1 => addr_data_f1,
425 addr_data_f2 => addr_data_f2,
426 addr_data_f3 => addr_data_f3,
427 -------------------------------------------------------------------------
428 -- CTRL
429 -------------------------------------------------------------------------
430 -- IN
431 empty => empty,
432 empty_almost => empty_almost,
433 data_ren => data_ren,
434
435 -------------------------------------------------------------------------
436 -- STATUS
437 -------------------------------------------------------------------------
438 status_full => status_full_s,
439 status_full_ack => status_full_ack,
440 status_full_err => status_full_err,
441
442 -------------------------------------------------------------------------
443 -- ADDR DATA OUT
444 -------------------------------------------------------------------------
445 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
446 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
447 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
448 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
449
450 data_f0_data_out_valid => data_f0_data_out_valid,
451 data_f1_data_out_valid => data_f1_data_out_valid,
452 data_f2_data_out_valid => data_f2_data_out_valid,
453 data_f3_data_out_valid => data_f3_data_out_valid,
454
455 data_f0_addr_out => data_f0_addr_out,
456 data_f1_addr_out => data_f1_addr_out,
457 data_f2_addr_out => data_f2_addr_out,
458 data_f3_addr_out => data_f3_addr_out
459 );
460
461 status_full <= status_full_s;
462
463 END beh;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3
4 ENTITY lpp_waveform_burst_LPP_JCP IS
5
6 GENERIC (
7 data_size : INTEGER := 16);
8
9 PORT (
10 clk : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
12 run : IN STD_LOGIC;
13
14 enable : IN STD_LOGIC;
15
16 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
17 data_in_valid : IN STD_LOGIC;
18
19 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
20 data_out_valid : OUT STD_LOGIC
21 );
22
23 END lpp_waveform_burst_LPP_JCP;
24
25 ARCHITECTURE beh OF lpp_waveform_burst_LPP_JCP IS
26 BEGIN -- beh
27
28 PROCESS (clk, rstn)
29 BEGIN
30 IF rstn = '0' THEN
31 data_out <= (OTHERS => '0');
32 data_out_valid <= '0';
33 ELSIF clk'EVENT AND clk = '1' THEN
34 data_out <= data_in;
35 IF enable = '0' OR run = '0' THEN
36 data_out_valid <= '0';
37 ELSE
38 data_out_valid <= data_in_valid;
39 END IF;
40 END IF;
41 END PROCESS;
42
43 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
25
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29
30
31 ENTITY lpp_waveform_dma_genvalid_LPP_JCP IS
32 PORT (
33 HCLK : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
36
37 valid_in : IN STD_LOGIC;
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
39
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 error : OUT STD_LOGIC
44 );
45 END;
46
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid_LPP_JCP IS
48 TYPE state_fsm IS (IDLE, VALID);
49 SIGNAL state : state_fsm;
50 BEGIN
51
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
53 BEGIN
54 IF HRESETn = '0' THEN
55 state <= IDLE;
56 valid_out <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
60 CASE state IS
61 WHEN IDLE =>
62
63 valid_out <= '0';
64 error <= '0';
65 IF run = '1' AND valid_in = '1' THEN
66 state <= VALID;
67 valid_out <= '1';
68 time_out <= time_in;
69 END IF;
70
71 WHEN VALID =>
72 IF run = '0' THEN
73 state <= IDLE;
74 valid_out <= '0';
75 error <= '0';
76 ELSE
77 IF valid_in = '1' THEN
78 IF ack_in = '1' THEN
79 state <= VALID;
80 valid_out <= '1';
81 time_out <= time_in;
82 ELSE
83 state <= IDLE;
84 error <= '1';
85 valid_out <= '0';
86 END IF;
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
89 valid_out <= '0';
90 END IF;
91 END IF;
92
93 WHEN OTHERS => NULL;
94 END CASE;
95 END IF;
96 END PROCESS FSM_SELECT_ADDRESS;
97
98 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.std_logic_1164.ALL;
25 USE IEEE.numeric_std.ALL;
26
27 LIBRARY staging;
28 USE staging.lpp_waveform_pkg_LPP_JCP.ALL;
29 USE staging.general_purpose_LPP_JCP.ALL;
30
31 ENTITY lpp_waveform_fifo_arbiter_LPP_JCP IS
32 GENERIC(
33 tech : INTEGER := 0;
34 nb_data_by_buffer_size : INTEGER := 11
35 );
36 PORT(
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 ---------------------------------------------------------------------------
40 run : IN STD_LOGIC;
41 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
42 ---------------------------------------------------------------------------
43 -- SNAPSHOT INTERFACE (INPUT)
44 ---------------------------------------------------------------------------
45 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
47 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
48 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
49
50 ---------------------------------------------------------------------------
51 -- FIFO INTERFACE (OUTPUT)
52 ---------------------------------------------------------------------------
53 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
54 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
56 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
57
58 );
59 END ENTITY;
60
61
62 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter_LPP_JCP IS
63 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
64 SIGNAL state : state_type_fifo_arbiter;
65
66 -----------------------------------------------------------------------------
67 -- DATA MUX
68 -----------------------------------------------------------------------------
69 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
73 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
78 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
79
80 -----------------------------------------------------------------------------
81 -- RR and SELECTION
82 -----------------------------------------------------------------------------
83 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
86 SIGNAL sel_reg : STD_LOGIC;
87 SIGNAL sel_ack : STD_LOGIC;
88 SIGNAL no_sel : STD_LOGIC;
89
90 -----------------------------------------------------------------------------
91 -- REG
92 -----------------------------------------------------------------------------
93 SIGNAL count_enable : STD_LOGIC;
94 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
96
97 BEGIN
98
99 -----------------------------------------------------------------------------
100 -- CONTROL
101 -----------------------------------------------------------------------------
102 PROCESS (clk, rstn)
103 BEGIN -- PROCESS
104 IF rstn = '0' THEN -- asynchronous reset (active low)
105 count_enable <= '0';
106 data_in_ack <= (OTHERS => '0');
107 data_out_wen <= (OTHERS => '1');
108 sel_ack <= '0';
109 state <= IDLE;
110 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
111 count_enable <= '0';
112 data_in_ack <= (OTHERS => '0');
113 data_out_wen <= (OTHERS => '1');
114 sel_ack <= '0';
115 IF run = '0' THEN
116 state <= IDLE;
117 ELSE
118 CASE state IS
119 WHEN IDLE =>
120 IF no_sel = '0' THEN
121 state <= TIME1;
122 END IF;
123 WHEN TIME1 =>
124 count_enable <= '1';
125 IF UNSIGNED(count) = 0 THEN
126 state <= TIME2;
127 data_out_wen <= NOT sel;
128 data_out <= data_sel(0);
129 ELSE
130 state <= DATA1;
131 END IF;
132 WHEN TIME2 =>
133 data_out_wen <= NOT sel;
134 data_out <= data_sel(1) ;
135 state <= DATA1;
136 WHEN DATA1 =>
137 data_out_wen <= NOT sel;
138 data_out <= data_sel(2);
139 state <= DATA2;
140 WHEN DATA2 =>
141 data_out_wen <= NOT sel;
142 data_out <= data_sel(3);
143 state <= DATA3;
144 WHEN DATA3 =>
145 data_out_wen <= NOT sel;
146 data_out <= data_sel(4);
147 state <= LAST;
148 data_in_ack <= sel;
149 WHEN LAST =>
150 state <= IDLE;
151 sel_ack <= '1';
152
153 WHEN OTHERS => NULL;
154 END CASE;
155 END IF;
156 END IF;
157 END PROCESS;
158 -----------------------------------------------------------------------------
159 -----------------------------------------------------------------------------
160 -- DATA MUX
161 -----------------------------------------------------------------------------
162 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
163 I_time_in: IF I < 48 GENERATE
164 data_0_v(I) <= time_in(0,I);
165 data_1_v(I) <= time_in(1,I);
166 data_2_v(I) <= time_in(2,I);
167 data_3_v(I) <= time_in(3,I);
168 END GENERATE I_time_in;
169 I_null: IF (I > 47) AND (I < 32*2) GENERATE
170 data_0_v(I) <= '0';
171 data_1_v(I) <= '0';
172 data_2_v(I) <= '0';
173 data_3_v(I) <= '0';
174 END GENERATE I_null;
175 I_data_in: IF I > 32*2-1 GENERATE
176 data_0_v(I) <= data_in(0,I-32*2);
177 data_1_v(I) <= data_in(1,I-32*2);
178 data_2_v(I) <= data_in(2,I-32*2);
179 data_3_v(I) <= data_in(3,I-32*2);
180 END GENERATE I_data_in;
181 END GENERATE all_bit_data_in;
182
183 all_word: FOR J IN 4 DOWNTO 0 GENERATE
184 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
185 data_0(J)(I) <= data_0_v(J*32+I);
186 data_1(J)(I) <= data_1_v(J*32+I);
187 data_2(J)(I) <= data_2_v(J*32+I);
188 data_3(J)(I) <= data_3_v(J*32+I);
189 END GENERATE all_data_bit;
190 END GENERATE all_word;
191
192 data_sel <= data_0 WHEN sel(0) = '1' ELSE
193 data_1 WHEN sel(1) = '1' ELSE
194 data_2 WHEN sel(2) = '1' ELSE
195 data_3;
196
197
198 -----------------------------------------------------------------------------
199 -- RR and SELECTION
200 -----------------------------------------------------------------------------
201 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
202 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
203 END GENERATE all_input_rr;
204
205 RR_Arbiter_4_1 : RR_Arbiter_4_LPP_JCP
206 PORT MAP (
207 clk => clk,
208 rstn => rstn,
209 in_valid => valid_in_rr,
210 out_grant => sel_s);
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 sel <= "0000";
216 sel_reg <= '0';
217 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
218 IF sel_reg = '0' OR sel_ack = '1' THEN
219 sel <= sel_s;
220 IF sel_s = "0000" THEN
221 sel_reg <= '0';
222 ELSE
223 sel_reg <= '1';
224 END IF;
225 END IF;
226 END IF;
227 END PROCESS;
228
229 no_sel <= '1' WHEN sel = "0000" ELSE '0';
230
231 -----------------------------------------------------------------------------
232 -- REG
233 -----------------------------------------------------------------------------
234 reg_count_i: lpp_waveform_fifo_arbiter_reg_LPP_JCP
235 GENERIC MAP (
236 data_size => nb_data_by_buffer_size,
237 data_nb => 4)
238 PORT MAP (
239 clk => clk,
240 rstn => rstn,
241 run => run,
242 max_count => nb_data_by_buffer,
243 enable => count_enable,
244 sel => sel,
245 data => count,
246 data_s => count_s);
247
248
249
250
251 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY lpp_waveform_fifo_arbiter_reg_LPP_JCP IS
27 GENERIC(
28 data_size : INTEGER;
29 data_nb : INTEGER
30 );
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 ---------------------------------------------------------------------------
35 run : IN STD_LOGIC;
36
37 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
38
39 enable : IN STD_LOGIC;
40 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
41
42 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
43 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
44 );
45 END ENTITY;
46
47
48 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg_LPP_JCP IS
49
50 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
51 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
52
53 SIGNAL reg_sel : INTEGER := 0;
54 SIGNAL reg_sel_s : INTEGER := 0;
55
56 BEGIN
57
58 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
59 PROCESS (clk, rstn)
60 BEGIN -- PROCESS
61 IF rstn = '0' THEN -- asynchronous reset (active low)
62 reg(I) <= 0;
63 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
64 IF run = '0' THEN
65 reg(I) <= 0;
66 ELSE
67 IF sel(I) = '1' THEN
68 reg(I) <= reg_sel_s;
69 END IF;
70 END IF;
71 END IF;
72 END PROCESS;
73 END GENERATE all_reg;
74
75 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
76 reg(1) WHEN sel(1) = '1' ELSE
77 reg(2) WHEN sel(2) = '1' ELSE
78 reg(3);
79
80 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
81 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
82 0;
83
84 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
85 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
86
87 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY staging;
34 USE staging.lpp_waveform_pkg_LPP_JCP .ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress_LPP_JCP IS
40
41 GENERIC (
42 nb_data_by_buffer_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
52 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 -------------------------------------------------------------------------
57 -- CTRL
58 -------------------------------------------------------------------------
59 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
61 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
62
63 -------------------------------------------------------------------------
64 -- STATUS
65 -------------------------------------------------------------------------
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 -------------------------------------------------------------------------
71 -- ADDR DATA OUT
72 -------------------------------------------------------------------------
73 data_f0_data_out_valid_burst : OUT STD_LOGIC;
74 data_f1_data_out_valid_burst : OUT STD_LOGIC;
75 data_f2_data_out_valid_burst : OUT STD_LOGIC;
76 data_f3_data_out_valid_burst : OUT STD_LOGIC;
77
78 data_f0_data_out_valid : OUT STD_LOGIC;
79 data_f1_data_out_valid : OUT STD_LOGIC;
80 data_f2_data_out_valid : OUT STD_LOGIC;
81 data_f3_data_out_valid : OUT STD_LOGIC;
82
83 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87
88 );
89
90 END lpp_waveform_genaddress_LPP_JCP;
91
92 ARCHITECTURE beh OF lpp_waveform_genaddress_LPP_JCP IS
93 SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
94 SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
95 SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
96 SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
97 -----------------------------------------------------------------------------
98 -- Valid gen
99 -----------------------------------------------------------------------------
100 SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
103
104 -----------------------------------------------------------------------------
105 -- Register
106 -----------------------------------------------------------------------------
107 SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
108 SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
109 SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
110 SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
111 SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
112 SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
113
114 -----------------------------------------------------------------------------
115 --
116 -----------------------------------------------------------------------------
117 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
118
119 TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0);
120 SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
121 SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
122
123 SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0);
124
125 BEGIN -- beh
126
127 -----------------------------------------------------------------------------
128 -- valid gen
129 -----------------------------------------------------------------------------
130 data_f0_data_out_valid <= data_out_valid(0);
131 data_f1_data_out_valid <= data_out_valid(1);
132 data_f2_data_out_valid <= data_out_valid(2);
133 data_f3_data_out_valid <= data_out_valid(3);
134
135 data_f0_data_out_valid_burst <= data_out_valid_burst(0);
136 data_f1_data_out_valid_burst <= data_out_valid_burst(1);
137 data_f2_data_out_valid_burst <= data_out_valid_burst(2);
138 data_f3_data_out_valid_burst <= data_out_valid_burst(3);
139
140
141
142 all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE
143 addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I));
144
145 addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000")
146 AND (UNSIGNED(addr_avail(I)) > 15)
147 ELSE '0';
148
149 data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
150 '0' WHEN empty(I) = '1' ELSE
151 '0' WHEN addr_burst_avail(I) = '1' ELSE
152 '0' WHEN (run = '0') ELSE
153 '1';
154
155 data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
156 '0' WHEN empty(I) = '1' ELSE
157 '0' WHEN addr_burst_avail(I) = '0' ELSE
158 '0' WHEN empty_almost(I) = '1' ELSE
159 '0' WHEN (run = '0') ELSE
160 '1';
161 END GENERATE all_bit_data_valid_out;
162
163 -----------------------------------------------------------------------------
164 -- Register
165 -----------------------------------------------------------------------------
166 all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE
167 all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE
168 PROCESS (clk, rstn)
169 BEGIN -- PROCESS
170 IF rstn = '0' THEN -- asynchronous reset (active low)
171 data_addr_v_reg(I, J) <= '0';
172 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 IF run = '1' AND status_full_ack(I) = '0' THEN
174 data_addr_v_reg(I, J) <= data_addr_v_pre(I, J);
175 ELSE
176 data_addr_v_reg(I, J) <= data_addr_v_base(I, J);
177 END IF;
178 END IF;
179 END PROCESS;
180
181 data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
182
183 END GENERATE all_data_addr;
184
185 data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE
186 data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE
187 data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE
188 data_addr_v_reg(3, J);
189
190 data_addr_v_base(0, J) <= addr_data_f0_s(J);
191 data_addr_v_base(1, J) <= addr_data_f1_s(J);
192 data_addr_v_base(2, J) <= addr_data_f2_s(J);
193 data_addr_v_base(3, J) <= addr_data_f3_s(J);
194
195 data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ;
196 data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ;
197 data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ;
198 data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ;
199
200 END GENERATE all_data_bit;
201
202 addr_data_f0_s <= addr_data_f0(31 DOWNTO 2);
203 addr_data_f1_s <= addr_data_f1(31 DOWNTO 2);
204 addr_data_f2_s <= addr_data_f2(31 DOWNTO 2);
205 addr_data_f3_s <= addr_data_f3(31 DOWNTO 2);
206
207 data_f0_addr_out(1 DOWNTO 0) <= "00";
208 data_f1_addr_out(1 DOWNTO 0) <= "00";
209 data_f2_addr_out(1 DOWNTO 0) <= "00";
210 data_f3_addr_out(1 DOWNTO 0) <= "00";
211
212
213
214
215 -----------------------------------------------------------------------------
216 -- ADDER
217 -----------------------------------------------------------------------------
218
219 data_addr_pre <= data_addr_reg + 1;
220
221 -----------------------------------------------------------------------------
222 -- FULL STATUS
223 -----------------------------------------------------------------------------
224 all_status : FOR I IN 3 DOWNTO 0 GENERATE
225 all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE
226 addr_v_p(I)(J) <= data_addr_v_pre(I, J);
227 addr_v_b(I)(J) <= data_addr_v_base(I, J);
228 END GENERATE all_bit_addr;
229
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 status_full_s(I) <= '0';
234 status_full_err(I) <= '0';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 IF run = '1' AND status_full_ack(I) = '0' THEN
237 IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
238 status_full_s(I) <= '1';
239 IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN
240 status_full_err(I) <= '1';
241 END IF;
242 END IF;
243 ELSE
244 status_full_s(I) <= '0';
245 status_full_err(I) <= '0';
246 END IF;
247 END IF;
248 END PROCESS;
249
250 END GENERATE all_status;
251
252 status_full <= status_full_s;
253
254
255 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
34
35 PACKAGE lpp_waveform_pkg_LPP_JCP IS
36
37 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
38
39 -----------------------------------------------------------------------------
40 -- SNAPSHOT
41 -----------------------------------------------------------------------------
42
43 COMPONENT lpp_waveform_snapshot_LPP_JCP
44 GENERIC (
45 data_size : INTEGER;
46 nb_snapshot_param_size : INTEGER);
47 PORT (
48 clk : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
50 run : IN STD_LOGIC;
51 enable : IN STD_LOGIC;
52 burst_enable : IN STD_LOGIC;
53 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
54 start_snapshot : IN STD_LOGIC;
55 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
56 data_in_valid : IN STD_LOGIC;
57 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 data_out_valid : OUT STD_LOGIC);
59 END COMPONENT;
60
61 COMPONENT lpp_waveform_burst_LPP_JCP
62 GENERIC (
63 data_size : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 run : IN STD_LOGIC;
68 enable : IN STD_LOGIC;
69 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
70 data_in_valid : IN STD_LOGIC;
71 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 data_out_valid : OUT STD_LOGIC);
73 END COMPONENT;
74
75 COMPONENT lpp_waveform_snapshot_controler_LPP_JCP
76 GENERIC (
77 delta_vector_size : INTEGER;
78 delta_vector_size_f0_2 : INTEGER);
79 PORT (
80 clk : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
82 reg_run : IN STD_LOGIC;
83 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
84 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
85 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
90 data_f0_valid : IN STD_LOGIC;
91 data_f2_valid : IN STD_LOGIC;
92 start_snapshot_f0 : OUT STD_LOGIC;
93 start_snapshot_f1 : OUT STD_LOGIC;
94 start_snapshot_f2 : OUT STD_LOGIC;
95 wfp_on : OUT STD_LOGIC);
96 END COMPONENT;
97
98 COMPONENT lpp_waveform_dma_genvalid_LPP_JCP
99 PORT (
100 HCLK : IN STD_LOGIC;
101 HRESETn : IN STD_LOGIC;
102 run : IN STD_LOGIC;
103 valid_in : IN STD_LOGIC;
104 ack_in : IN STD_LOGIC;
105 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
106 valid_out : OUT STD_LOGIC;
107 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
108 error : OUT STD_LOGIC);
109 END COMPONENT;
110
111 -----------------------------------------------------------------------------
112 -- FIFO
113 -----------------------------------------------------------------------------
114 COMPONENT lpp_waveform_fifo_arbiter_LPP_JCP
115 GENERIC (
116 tech : INTEGER;
117 nb_data_by_buffer_size : INTEGER);
118 PORT (
119 clk : IN STD_LOGIC;
120 rstn : IN STD_LOGIC;
121 run : IN STD_LOGIC;
122 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
123 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
124 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
125 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
126 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
127 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
129 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
130 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
131 END COMPONENT;
132
133 -----------------------------------------------------------------------------
134 -- GEN ADDRESS
135 -----------------------------------------------------------------------------
136 COMPONENT lpp_waveform_genaddress_LPP_JCP
137 GENERIC (
138 nb_data_by_buffer_size : INTEGER);
139 PORT (
140 clk : IN STD_LOGIC;
141 rstn : IN STD_LOGIC;
142 run : IN STD_LOGIC;
143 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
144 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
149 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
150 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
151 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
152 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
154 data_f0_data_out_valid_burst : OUT STD_LOGIC;
155 data_f1_data_out_valid_burst : OUT STD_LOGIC;
156 data_f2_data_out_valid_burst : OUT STD_LOGIC;
157 data_f3_data_out_valid_burst : OUT STD_LOGIC;
158 data_f0_data_out_valid : OUT STD_LOGIC;
159 data_f1_data_out_valid : OUT STD_LOGIC;
160 data_f2_data_out_valid : OUT STD_LOGIC;
161 data_f3_data_out_valid : OUT STD_LOGIC;
162 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
166 END COMPONENT;
167
168 -----------------------------------------------------------------------------
169 -- lpp_waveform_fifo_arbiter_reg
170 -----------------------------------------------------------------------------
171 COMPONENT lpp_waveform_fifo_arbiter_reg_LPP_JCP
172 GENERIC (
173 data_size : INTEGER;
174 data_nb : INTEGER);
175 PORT (
176 clk : IN STD_LOGIC;
177 rstn : IN STD_LOGIC;
178 run : IN STD_LOGIC;
179 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
180 enable : IN STD_LOGIC;
181 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
182 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
183 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
184 END COMPONENT;
185
186 END lpp_waveform_pkg_LPP_JCP;
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 ENTITY lpp_waveform_snapshot_LPP_JCP IS
6
7 GENERIC (
8 data_size : INTEGER := 16;
9 nb_snapshot_param_size : INTEGER := 11);
10
11 PORT (
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 run : IN STD_LOGIC;
15
16 enable : IN STD_LOGIC;
17 burst_enable : IN STD_LOGIC;
18 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
19
20 start_snapshot : IN STD_LOGIC;
21
22 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
23 data_in_valid : IN STD_LOGIC;
24
25 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
26 data_out_valid : OUT STD_LOGIC
27 );
28
29 END lpp_waveform_snapshot_LPP_JCP;
30
31 ARCHITECTURE beh OF lpp_waveform_snapshot_LPP_JCP IS
32 SIGNAL counter_points_snapshot : INTEGER;
33 BEGIN -- beh
34
35 PROCESS (clk, rstn)
36 BEGIN
37 IF rstn = '0' THEN
38 data_out <= (OTHERS => '0');
39 data_out_valid <= '0';
40 counter_points_snapshot <= 0;
41 ELSIF clk'EVENT AND clk = '1' THEN
42 data_out <= data_in;
43 IF enable = '0' OR run = '0' THEN
44 data_out_valid <= '0';
45 counter_points_snapshot <= 0;
46 ELSE
47 IF burst_enable = '1' THEN
48 -- BURST ModE --
49 data_out_valid <= data_in_valid;
50 counter_points_snapshot <= 0;
51 ELSE
52 -- SNAPShOT MODE --
53 IF start_snapshot = '1' THEN
54 IF data_in_valid = '1' THEN
55 counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1;
56 data_out_valid <= '1';
57 ELSE
58 counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param));
59 data_out_valid <= '0';
60 END IF;
61 ELSE
62 IF data_in_valid = '1' THEN
63 IF counter_points_snapshot > 0 THEN
64 counter_points_snapshot <= counter_points_snapshot - 1;
65 data_out_valid <= '1';
66 ELSE
67 counter_points_snapshot <= counter_points_snapshot;
68 data_out_valid <= '0';
69 END IF;
70 ELSE
71 counter_points_snapshot <= counter_points_snapshot;
72 data_out_valid <= '0';
73 END IF;
74 END IF;
75
76 END IF;
77 END IF;
78 END IF;
79 END PROCESS;
80
81 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 ENTITY lpp_waveform_snapshot_controler_LPP_JCP IS
28
29 GENERIC (
30 delta_vector_size : INTEGER := 20;
31 delta_vector_size_f0_2 : INTEGER := 3
32 );
33
34 PORT (
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 ---------------------------------------------------------------------------
38 --REGISTER CONTROL
39 reg_run : IN STD_LOGIC;
40 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
41 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
42 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
43 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
44 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
45 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
46 ---------------------------------------------------------------------------
47 -- INPUT
48 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
49 data_f0_valid : IN STD_LOGIC;
50 data_f2_valid : IN STD_LOGIC;
51 ---------------------------------------------------------------------------
52 -- OUTPUT
53 start_snapshot_f0 : OUT STD_LOGIC;
54 start_snapshot_f1 : OUT STD_LOGIC;
55 start_snapshot_f2 : OUT STD_LOGIC;
56 wfp_on : OUT STD_LOGIC
57 );
58
59 END lpp_waveform_snapshot_controler_LPP_JCP;
60
61 ARCHITECTURE beh OF lpp_waveform_snapshot_controler_LPP_JCP IS
62 -----------------------------------------------------------------------------
63 -- WAVEFORM ON/OFF FSM
64 SIGNAL state_on : STD_LOGIC;
65 SIGNAL wfp_on_s : STD_LOGIC;
66 -----------------------------------------------------------------------------
67 -- StartSnapshot Generator for f2, f1 and f0_pre
68 SIGNAL start_snapshot_f0_pre : STD_LOGIC;
69 -- SIGNAL first_decount_s : STD_LOGIC;
70 SIGNAL first_decount : STD_LOGIC;
71 SIGNAL first_init : STD_LOGIC;
72 SIGNAL counter_delta_snapshot : INTEGER;
73 -----------------------------------------------------------------------------
74 -- StartSnapshot Generator for f0
75 SIGNAL counter_delta_f0 : INTEGER;
76 SIGNAL send_start_snapshot_f0 : STD_LOGIC;
77 BEGIN -- beh
78 wfp_on <= wfp_on_s;
79
80 -----------------------------------------------------------------------------
81 -- WAVEFORM ON/OFF FSM
82 -----------------------------------------------------------------------------
83 -- INPUT reg_run
84 -- coarse_time
85 -- reg_start_date
86 -- OUTPUT wfp_on_s
87 -----------------------------------------------------------------------------
88 waveform_on_off_fsm : PROCESS (clk, rstn)
89 BEGIN
90 IF rstn = '0' THEN
91 state_on <= '0';
92 ELSIF clk'EVENT AND clk = '1' THEN
93 IF state_on = '1' THEN -- Waveform Picker ON
94 state_on <= reg_run;
95 ELSE -- Waveform Picker OFF
96 IF coarse_time = reg_start_date THEN
97 state_on <= reg_run;
98 END IF;
99 END IF;
100 END IF;
101 END PROCESS waveform_on_off_fsm;
102 wfp_on_s <= state_on;
103 -----------------------------------------------------------------------------
104
105 -----------------------------------------------------------------------------
106 -- StartSnapshot Generator for f2, f1 and f0_pre
107 -----------------------------------------------------------------------------
108 -- INPUT wfp_on_s
109 -- reg_delta_snapshot
110 -- reg_delta_f0
111 -- reg_delta_f1
112 -- reg_delta_f2
113 -- data_f2_valid
114 -- OUTPUT start_snapshot_f0_pre
115 -- start_snapshot_f1
116 -- start_snapshot_f2
117 -----------------------------------------------------------------------------
118 --lpp_front_positive_detection_1 : lpp_front_positive_detection
119 -- PORT MAP (
120 -- clk => clk,
121 -- rstn => rstn,
122 -- sin => wfp_on_s,
123 -- sout => first_decount_s);
124
125 Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn)
126 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
127 IF rstn = '0' THEN -- asynchronous reset (active low)
128 counter_delta_snapshot <= 0;
129 first_decount <= '1';
130 first_init <= '1';
131 start_snapshot_f0_pre <= '0';
132 start_snapshot_f1 <= '0';
133 start_snapshot_f2 <= '0';
134 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
135 IF wfp_on_s = '0' THEN
136 counter_delta_snapshot <= 0;
137 first_decount <= '1';
138 first_init <= '1';
139 start_snapshot_f0_pre <= '0';
140 start_snapshot_f1 <= '0';
141 start_snapshot_f2 <= '0';
142 ELSE
143 start_snapshot_f0_pre <= '0';
144 start_snapshot_f1 <= '0';
145 start_snapshot_f2 <= '0';
146
147 IF data_f2_valid = '1' THEN
148 IF first_init = '1' THEN
149 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2));
150 first_init <= '0';
151 ELSE
152 IF counter_delta_snapshot > 0 THEN
153 counter_delta_snapshot <= counter_delta_snapshot - 1;
154 ELSE
155 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot));
156 first_decount <= '0';
157 END IF;
158
159 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN
160 IF first_decount = '0' THEN
161 start_snapshot_f0_pre <= '1';
162 END IF;
163 END IF;
164
165 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN
166 IF first_decount = '0' THEN
167 start_snapshot_f1 <= '1';
168 END IF;
169 END IF;
170
171 IF counter_delta_snapshot = 0 THEN
172 start_snapshot_f2 <= '1';
173 END IF;
174 END IF;
175 END IF;
176 END IF;
177 END IF;
178 END PROCESS Decounter_Cyclic_DeltaSnapshot;
179 -----------------------------------------------------------------------------
180
181
182 -----------------------------------------------------------------------------
183 -- StartSnapshot Generator for f0
184 -----------------------------------------------------------------------------
185 -- INPUT wfp_on_s
186 -- start_snapshot_f0_pre
187 -- reg_delta_snapshot
188 -- reg_delta_f0_2
189 -- data_f0_valid
190 -- OUTPUT start_snapshot_f0
191 -----------------------------------------------------------------------------
192 Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn)
193 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 counter_delta_f0 <= 0;
196 start_snapshot_f0 <= '0';
197 send_start_snapshot_f0 <= '0';
198 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
199 start_snapshot_f0 <= '0';
200 IF wfp_on_s = '0' THEN
201 counter_delta_f0 <= 0;
202 send_start_snapshot_f0 <= '1';
203 ELSE
204 IF start_snapshot_f0_pre = '1' THEN
205 send_start_snapshot_f0 <= '0';
206 counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2));
207 ELSIF data_f0_valid = '1' THEN
208 IF counter_delta_f0 > 0 THEN
209 send_start_snapshot_f0 <= '0';
210 counter_delta_f0 <= counter_delta_f0 - 1;
211 ELSE
212 IF send_start_snapshot_f0 = '0' THEN
213 send_start_snapshot_f0 <= '1';
214 start_snapshot_f0 <= '1';
215 END IF;
216 END IF;
217 END IF;
218 END IF;
219 END IF;
220 END PROCESS Decounter_DeltaSnapshot_f0;
221 -----------------------------------------------------------------------------
222
223 END beh;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe PELLION
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 ----------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 ENTITY RR_Arbiter_4_LPP_JCP IS
28
29 PORT (
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
33 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
34 );
35
36 END RR_Arbiter_4_LPP_JCP;
37
38 ARCHITECTURE beh OF RR_Arbiter_4_LPP_JCP IS
39
40 SIGNAL out_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
41 SIGNAL grant_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
42
43 BEGIN -- beh
44
45 out_grant <= out_grant_s;
46
47 out_grant_s <= "0001" WHEN grant_sel = "00" AND in_valid(0) = '1' ELSE
48 "0010" WHEN grant_sel = "00" AND in_valid(1) = '1' ELSE
49 "0100" WHEN grant_sel = "00" AND in_valid(2) = '1' ELSE
50 "1000" WHEN grant_sel = "00" AND in_valid(3) = '1' ELSE
51 "0010" WHEN grant_sel = "01" AND in_valid(1) = '1' ELSE
52 "0100" WHEN grant_sel = "01" AND in_valid(2) = '1' ELSE
53 "1000" WHEN grant_sel = "01" AND in_valid(3) = '1' ELSE
54 "0001" WHEN grant_sel = "01" AND in_valid(0) = '1' ELSE
55 "0100" WHEN grant_sel = "10" AND in_valid(2) = '1' ELSE
56 "1000" WHEN grant_sel = "10" AND in_valid(3) = '1' ELSE
57 "0001" WHEN grant_sel = "10" AND in_valid(0) = '1' ELSE
58 "0010" WHEN grant_sel = "10" AND in_valid(1) = '1' ELSE
59 "1000" WHEN grant_sel = "11" AND in_valid(3) = '1' ELSE
60 "0001" WHEN grant_sel = "11" AND in_valid(0) = '1' ELSE
61 "0010" WHEN grant_sel = "11" AND in_valid(1) = '1' ELSE
62 "0100" WHEN grant_sel = "11" AND in_valid(2) = '1' ELSE
63 "0000";
64
65 PROCESS (clk, rstn)
66 BEGIN -- PROCESS
67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 grant_sel <= "00";
69 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
70 CASE out_grant_s IS
71 WHEN "0001" => grant_sel <= "01";
72 WHEN "0010" => grant_sel <= "10";
73 WHEN "0100" => grant_sel <= "11";
74 WHEN "1000" => grant_sel <= "00";
75 WHEN OTHERS => grant_sel <= grant_sel;
76 END CASE;
77 END IF;
78 END PROCESS;
79
80 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28
29 LIBRARY staging;
30 USE staging.FIFO_shared_memory_4channel_pkg_LPP_JCP.ALL;
31
32 ENTITY FIFO_shared_memory_4channel_LPP_JCP IS
33 GENERIC(
34 tech : INTEGER := 0
35 );
36 PORT(
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 ---------------------------------------------------------------------------
40 run : IN STD_LOGIC;
41
42 ---------------------------------------------------------------------------
43 empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
44 empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
45 data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
46 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
47
48 ---------------------------------------------------------------------------
49 full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
50 full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
51 data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
52 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 );
54 END ENTITY;
55
56
57 ARCHITECTURE ar_FIFO_shared_memory_4channel OF FIFO_shared_memory_4channel_LPP_JCP IS
58
59
60 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
61 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
62 SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0);
64
65 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
66 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
67 SIGNAL re : STD_LOGIC;
68 SIGNAL we : STD_LOGIC;
69
70 BEGIN
71
72 SRAM : syncram_2p
73 GENERIC MAP(tech, 7, 32)
74 PORT MAP(clk, re, data_addr_r, rdata,
75 clk, we, data_addr_w, wdata);
76
77 re <= data_mem_re(3) OR
78 data_mem_re(2) OR
79 data_mem_re(1) OR
80 data_mem_re(0);
81
82 we <= data_mem_we(3) OR
83 data_mem_we(2) OR
84 data_mem_we(1) OR
85 data_mem_we(0);
86
87 data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE
88 data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE
89 data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE
90 data_mem_addr_r(3);
91
92 data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE
93 data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE
94 data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE
95 data_mem_addr_w(3);
96
97 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
98 FIFO_shared_memory_4channel_ctrl_data: FIFO_shared_memory_4channel_ctrl_LPP_JCP
99 GENERIC MAP (
100 offset => 32*I,
101 length => 32)
102 PORT MAP (
103 clk => clk,
104 rstn => rstn,
105 run => run,
106 ren => data_ren(I),
107 wen => data_wen(I),
108 mem_re => data_mem_re(I),
109 mem_we => data_mem_we(I),
110 mem_addr_ren => data_mem_addr_r(I),
111 mem_addr_wen => data_mem_addr_w(I),
112 empty_almost => empty_almost(I),
113 empty => empty(I),
114 full_almost => full_almost(I),
115 full => full(I)
116 );
117 END GENERATE gen_fifo_ctrl_data;
118
119
120
121 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY FIFO_shared_memory_4channel_ctrl_LPP_JCP IS
27 generic(
28 offset : INTEGER := 0;
29 length : INTEGER := 20
30 );
31 PORT(
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34
35 run : IN STD_LOGIC;
36
37 ren : IN STD_LOGIC;
38 wen : IN STD_LOGIC;
39
40 mem_re : OUT STD_LOGIC;
41 mem_we : OUT STD_LOGIC;
42
43 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
44 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
45 ---------------------------------------------------------------------------
46 empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
47 empty : OUT STD_LOGIC;
48 full_almost : OUT STD_LOGIC; --occupancy is greater than MAX - 5 * 32b
49 full : OUT STD_LOGIC
50
51 );
52 END ENTITY;
53
54
55 ARCHITECTURE ar_FIFO_shared_memory_4channel_ctrl OF FIFO_shared_memory_4channel_ctrl_LPP_JCP IS
56
57 SIGNAL sFull : STD_LOGIC;
58 SIGNAL sFull_s : STD_LOGIC;
59 SIGNAL sEmpty_s : STD_LOGIC;
60
61 SIGNAL sEmpty : STD_LOGIC;
62 SIGNAL sREN : STD_LOGIC;
63 SIGNAL sWEN : STD_LOGIC;
64 SIGNAL sRE : STD_LOGIC;
65 SIGNAL sWE : STD_LOGIC;
66
67 SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0;
68 SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0;
69 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
70 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
71
72 SIGNAL space_busy : INTEGER RANGE 0 TO length := 0;
73 SIGNAL space_free : INTEGER RANGE 0 TO length := 0;
74
75 BEGIN
76 mem_re <= sRE;
77 mem_we <= sWE;
78 --=============================
79 -- Read section
80 --=============================
81 sREN <= REN OR sEmpty;
82 sRE <= NOT sREN;
83
84 sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE
85 '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE
86 '0';
87
88 Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ;
89
90 PROCESS (clk, rstn)
91 BEGIN
92 IF(rstn = '0')then
93 Raddr_vect <= 0;
94 sempty <= '1';
95 ELSIF(clk'EVENT AND clk = '1')then
96 IF run = '0' THEN
97 Raddr_vect <= 0;
98 sempty <= '1';
99 ELSE
100 sEmpty <= sempty_s;
101 IF(sREN = '0' and sempty = '0')then
102 Raddr_vect <= Raddr_vect_s;
103 END IF;
104 END IF;
105 END IF;
106 END PROCESS;
107
108 --=============================
109 -- Write section
110 --=============================
111 sWEN <= WEN OR sFull;
112 sWE <= NOT sWEN;
113
114 sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE
115 '1' WHEN sFull = '1' AND REN = '1' ELSE
116 '0';
117
118 Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ;
119
120 PROCESS (clk, rstn)
121 BEGIN
122 IF(rstn = '0')then
123 Waddr_vect <= 0;
124 sfull <= '0';
125 ELSIF(clk'EVENT AND clk = '1')THEN
126 IF run = '0' THEN
127 Waddr_vect <= 0;
128 sfull <= '0';
129 ELSE
130 sfull <= sfull_s;
131 IF(sWEN = '0' and sfull = '0')THEN
132 Waddr_vect <= Waddr_vect_s;
133 END IF;
134 END IF;
135 END IF;
136 END PROCESS;
137
138
139 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
140 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
141
142
143 -----------------------------------------------------------------------------
144 --
145 -----------------------------------------------------------------------------
146 empty_almost <= '0' WHEN space_busy > 15 ELSE '1';
147 empty <= sEmpty;
148
149 full_almost <= '0' WHEN space_free > 4 ELSE '1';
150 full <= sfull;
151
152 -----------------------------------------------------------------------------
153 --
154 -----------------------------------------------------------------------------
155 space_busy <= length WHEN sfull = '1' ELSE
156 length + Waddr_vect - Raddr_vect WHEN Waddr_vect < Raddr_vect ELSE
157 Waddr_vect - Raddr_vect;
158
159 space_free <= length - space_busy;
160
161
162 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 ENTITY FIFO_shared_memory_4channel_headreg_LPP_JCP IS
27 GENERIC(
28 tech : INTEGER := 0
29 );
30 PORT(
31 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
33 ---------------------------------------------------------------------------
34 run : IN STD_LOGIC;
35 ---------------------------------------------------------------------------
36 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
37 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
39 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
40 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
41 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
42 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --
43 ---------------------------------------------------------------------------
44 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --
47 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
48 );
49 END ENTITY;
50
51
52 ARCHITECTURE ar_FIFO_shared_memory_4channel_headreg OF FIFO_shared_memory_4channel_headreg_LPP_JCP IS
53 SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
54 SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
55 SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
56 SIGNAL one_ren_and_notEmpty : STD_LOGIC;
57 SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0);
58 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
59 SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
60 SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
61 SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
62 SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 BEGIN
64
65 -----------------------------------------------------------------------------
66 -- DATA_REN_FIFO
67 -----------------------------------------------------------------------------
68 i_data_ren <= s_ren;
69 PROCESS (clk, rstn)
70 BEGIN
71 IF rstn = '0' THEN
72 s_ren_reg <= (OTHERS => '1');
73 ELSIF clk'EVENT AND clk = '1' THEN
74 IF run = '1' THEN
75 s_ren_reg <= s_ren;
76 ELSE
77 s_ren_reg <= (OTHERS => '1');
78 END IF;
79 END IF;
80 END PROCESS;
81
82 s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE
83 NOT ((NOT i_empty(0)) AND (NOT reg_full(0)));
84 s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE
85 '1' WHEN s_ren(0) = '0' ELSE
86 NOT ((NOT i_empty(1)) AND (NOT reg_full(1)));
87 s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE
88 '1' WHEN s_ren(0) = '0' ELSE
89 '1' WHEN s_ren(1) = '0' ELSE
90 NOT ((NOT i_empty(2)) AND (NOT reg_full(2)));
91 s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE
92 '1' WHEN s_ren(0) = '0' ELSE
93 '1' WHEN s_ren(1) = '0' ELSE
94 '1' WHEN s_ren(2) = '0' ELSE
95 NOT ((NOT i_empty(3)) AND (NOT reg_full(3)));
96 -----------------------------------------------------------------------------
97 all_ren : FOR I IN 3 DOWNTO 0 GENERATE
98 ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I));
99 END GENERATE all_ren;
100 one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1';
101
102 -----------------------------------------------------------------------------
103 -- DATA
104 -----------------------------------------------------------------------------
105 o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0;
106 o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1;
107 o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2;
108 o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3;
109
110 PROCESS (clk, rstn)
111 BEGIN
112 IF rstn = '0' THEN
113 s_rdata_0 <= (OTHERS => '0');
114 s_rdata_1 <= (OTHERS => '0');
115 s_rdata_2 <= (OTHERS => '0');
116 s_rdata_3 <= (OTHERS => '0');
117 ELSIF clk'EVENT AND clk = '1' THEN
118 IF run = '1' THEN
119 IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF;
120 IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF;
121 IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF;
122 IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF;
123 ELSE
124 s_rdata_0 <= (OTHERS => '0');
125 s_rdata_1 <= (OTHERS => '0');
126 s_rdata_2 <= (OTHERS => '0');
127 s_rdata_3 <= (OTHERS => '0');
128 END IF;
129 END IF;
130 END PROCESS;
131
132 all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE
133 PROCESS (clk, rstn)
134 BEGIN
135 IF rstn = '0' THEN
136 reg_full(I) <= '0';
137 ELSIF clk'EVENT AND clk = '1' THEN
138 -- IF s_ren_reg(I) = '0' THEN
139 IF run = '1' THEN
140 IF s_ren(I) = '0' THEN
141 reg_full(I) <= '1';
142 ELSIF o_data_ren(I) = '0' THEN
143 reg_full(I) <= '0';
144 END IF;
145 ELSE
146 reg_full(I) <= '0';
147 END IF;
148 END IF;
149 END PROCESS;
150 END GENERATE all_reg_full;
151
152 -----------------------------------------------------------------------------
153 -- EMPTY
154 -----------------------------------------------------------------------------
155 o_empty <= NOT reg_full;
156
157 -----------------------------------------------------------------------------
158 -- EMPTY_ALMOST
159 -----------------------------------------------------------------------------
160 o_empty_almost <= s_empty_almost;
161
162 all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE
163 PROCESS (clk, rstn)
164 BEGIN -- PROCESS
165 IF rstn = '0' THEN -- asynchronous reset (active low)
166 s_empty_almost(I) <= '1';
167 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
168 IF run = '1' THEN
169 IF s_ren(I) = '0' THEN
170 s_empty_almost(I) <= i_empty_almost(I);
171 ELSIF o_data_ren(I) = '0' THEN
172 s_empty_almost(I) <= '1';
173 ELSE
174 IF i_empty_almost(I) = '0' THEN
175 s_empty_almost(I) <= '0';
176 END IF;
177 END IF;
178 ELSE
179 s_empty_almost(I) <= '1';
180 END IF;
181 END IF;
182 END PROCESS;
183 END GENERATE all_empty_almost;
184
185 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
26 PACKAGE FIFO_shared_memory_4channel_pkg_LPP_JCP IS
27
28 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
29
30 COMPONENT FIFO_shared_memory_4channel_headreg_LPP_JCP
31 GENERIC (
32 tech : INTEGER);
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
37 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
38 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
39 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
40 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
41 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
42 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
43 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
46 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
47 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
48 END COMPONENT;
49
50 COMPONENT FIFO_shared_memory_4channel_ctrl_LPP_JCP
51 GENERIC (
52 offset : INTEGER;
53 length : INTEGER);
54 PORT (
55 clk : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
57 run : IN STD_LOGIC;
58 ren : IN STD_LOGIC;
59 wen : IN STD_LOGIC;
60 mem_re : OUT STD_LOGIC;
61 mem_we : OUT STD_LOGIC;
62 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
63 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
64 empty_almost : OUT STD_LOGIC;
65 empty : OUT STD_LOGIC;
66 full_almost : OUT STD_LOGIC;
67 full : OUT STD_LOGIC);
68 END COMPONENT;
69
70
71 END FIFO_shared_memory_4channel_pkg_LPP_JCP;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
27
28 PACKAGE general_purpose_LPP_JCP IS
29
30 -----------------------------------------------------------------------------
31 -- SYNCHRONIZER
32 -----------------------------------------------------------------------------
33 COMPONENT SYNC_FF_LPP_JCP
34 GENERIC (
35 NB_FF_OF_SYNC : INTEGER);
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 A : IN STD_LOGIC;
40 A_sync : OUT STD_LOGIC);
41 END COMPONENT;
42
43 COMPONENT SYNC_VALID_BIT_LPP_JCP
44 GENERIC (
45 NB_FF_OF_SYNC : INTEGER);
46 PORT (
47 clk_in : IN STD_LOGIC;
48 clk_out : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
50 sin : IN STD_LOGIC;
51 sout : OUT STD_LOGIC);
52 END COMPONENT;
53
54 -----------------------------------------------------------------------------
55 -- EDGE DETECTION
56 -----------------------------------------------------------------------------
57 COMPONENT lpp_edge_detection_LPP_JCP
58 PORT (
59 clk : IN STD_LOGIC;
60 rstn : IN STD_LOGIC;
61 sin : IN STD_LOGIC;
62 sout : OUT STD_LOGIC);
63 END COMPONENT;
64
65 COMPONENT lpp_edge_to_level_LPP_JCP
66 PORT (
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 sin : IN STD_LOGIC;
70 sout : OUT STD_LOGIC);
71 END COMPONENT;
72
73 -----------------------------------------------------------------------------
74 -- COMPUTING
75 -----------------------------------------------------------------------------
76 COMPONENT ALU_LPP_JCP
77 GENERIC (
78 Arith_en : INTEGER;
79 Logic_en : INTEGER;
80 Input_SZ_1 : INTEGER;
81 Input_SZ_2 : INTEGER;
82 COMP_EN : INTEGER);
83 PORT (
84 clk : IN STD_LOGIC;
85 reset : IN STD_LOGIC;
86 ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
87 comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
88 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
89 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
90 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0));
91 END COMPONENT;
92
93 COMPONENT MAC_LPP_JCP
94 GENERIC (
95 Input_SZ_A : INTEGER;
96 Input_SZ_B : INTEGER;
97 COMP_EN : INTEGER);
98 PORT (
99 clk : IN STD_LOGIC;
100 reset : IN STD_LOGIC;
101 clr_MAC : IN STD_LOGIC;
102 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
103 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
104 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
105 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
106 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0));
107 END COMPONENT;
108
109 -----------------------------------------------------------------------------
110 -- COMMON
111 -----------------------------------------------------------------------------
112 COMPONENT Multiplier_LPP_JCP
113 GENERIC (
114 Input_SZ_A : INTEGER;
115 Input_SZ_B : INTEGER);
116 PORT (
117 clk : IN STD_LOGIC;
118 reset : IN STD_LOGIC;
119 mult : IN STD_LOGIC;
120 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
121 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
122 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0));
123 END COMPONENT;
124
125 COMPONENT Adder_LPP_JCP
126 GENERIC (
127 Input_SZ_A : INTEGER;
128 Input_SZ_B : INTEGER);
129 PORT (
130 clk : IN STD_LOGIC;
131 reset : IN STD_LOGIC;
132 clr : IN STD_LOGIC;
133 load : IN STD_LOGIC;
134 add : IN STD_LOGIC;
135 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
136 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
137 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0));
138 END COMPONENT;
139
140 COMPONENT TwoComplementer_LPP_JCP
141 GENERIC (
142 Input_SZ : INTEGER);
143 PORT (
144 clk : IN STD_LOGIC;
145 reset : IN STD_LOGIC;
146 clr : IN STD_LOGIC;
147 TwoComp : IN STD_LOGIC;
148 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
149 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0));
150 END COMPONENT;
151
152 COMPONENT Register_LPP_JCP
153 GENERIC (
154 size : INTEGER);
155 PORT (
156 reset : IN STD_LOGIC;
157 clk : IN STD_LOGIC;
158 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
159 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0));
160 END COMPONENT;
161
162 COMPONENT MUX_LPP_JCP
163 GENERIC (
164 Input_SZ_A : INTEGER;
165 Input_SZ_B : INTEGER);
166 PORT (
167 sel : IN STD_LOGIC;
168 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
169 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
170 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
171 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
172 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
173 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0));
174 END COMPONENT;
175
176 COMPONENT MUX2_LPP_JCP
177 GENERIC (
178 Input_SZ : integer);
179 PORT (
180 sel : in std_logic;
181 RES1 : in std_logic_vector(Input_SZ-1 downto 0);
182 RES2 : in std_logic_vector(Input_SZ-1 downto 0);
183 RES : out std_logic_vector(Input_SZ-1 downto 0));
184 END COMPONENT;
185
186 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
187 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
188
189 COMPONENT MUXN_LPP_JCP
190 GENERIC (
191 Input_SZ : INTEGER;
192 NbStage : INTEGER);
193 PORT (
194 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
195 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0);
196 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
197 END COMPONENT;
198
199 -----------------------------------------------------------------------------
200 -- ARBITER
201 -----------------------------------------------------------------------------
202 COMPONENT RR_Arbiter_4_LPP_JCP
203 PORT (
204 clk : IN STD_LOGIC;
205 rstn : IN STD_LOGIC;
206 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
207 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
208 END COMPONENT;
209
210 -----------------------------------------------------------------------------
211 -- FIFO
212 -----------------------------------------------------------------------------
213 COMPONENT FIFO_shared_memory_4channel_LPP_JCP
214 GENERIC (
215 tech : INTEGER);
216 PORT (
217 clk : IN STD_LOGIC;
218 rstn : IN STD_LOGIC;
219 run : IN STD_LOGIC;
220 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
221 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
222 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
223 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
224 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
225 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
226 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
227 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
228 END COMPONENT;
229
230 COMPONENT FIFO_shared_memory_4channel_headreg_LPP_JCP
231 GENERIC (
232 tech : INTEGER);
233 PORT (
234 clk : IN STD_LOGIC;
235 rstn : IN STD_LOGIC;
236 run : IN STD_LOGIC;
237 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
238 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
239 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
240 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
241 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
242 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
243 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
244 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
245 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
246 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
247 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
248 END COMPONENT;
249
250 END;
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@@ -14,6 +14,7 USE GRLIB.DMA2AHB_Package.ALL;
14 LIBRARY staging;
14 LIBRARY staging;
15 USE staging.sample_type_LPP_JCP.ALL;
15 USE staging.sample_type_LPP_JCP.ALL;
16 USE staging.lpp_lfr_pkg_LPP_JCP.ALL;
16 USE staging.lpp_lfr_pkg_LPP_JCP.ALL;
17 USE staging.general_purpose_LPP_JCP.ALL;
17 USE staging.memory_LPP_JCP.ALL;
18 USE staging.memory_LPP_JCP.ALL;
18
19
19 ENTITY lpp_lfr_LPP_JCP IS
20 ENTITY lpp_lfr_LPP_JCP IS
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@@ -134,5 +134,78 PACKAGE lpp_lfr_pkg_LPP_JCP IS
134 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
135 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
135 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
136 END COMPONENT;
136 END COMPONENT;
137
138 -----------------------------------------------------------------------------
139 -- lpp_waveform
140 -----------------------------------------------------------------------------
141 COMPONENT lpp_waveform_LPP_JCP
142 GENERIC (
143 tech : INTEGER;
144 data_size : INTEGER;
145 nb_data_by_buffer_size : INTEGER;
146 nb_word_by_buffer_size : INTEGER;
147 nb_snapshot_param_size : INTEGER;
148 delta_vector_size : INTEGER;
149 delta_vector_size_f0_2 : INTEGER);
150 PORT (
151 clk : IN STD_LOGIC;
152 rstn : IN STD_LOGIC;
153 reg_run : IN STD_LOGIC;
154 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
155 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
156 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
157 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
158 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
159 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 enable_f0 : IN STD_LOGIC;
161 enable_f1 : IN STD_LOGIC;
162 enable_f2 : IN STD_LOGIC;
163 enable_f3 : IN STD_LOGIC;
164 burst_f0 : IN STD_LOGIC;
165 burst_f1 : IN STD_LOGIC;
166 burst_f2 : IN STD_LOGIC;
167 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
171 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
172 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
173 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
174 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
176 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 data_f0_in_valid : IN STD_LOGIC;
178 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
180 data_f1_in_valid : IN STD_LOGIC;
181 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
182 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
183 data_f2_in_valid : IN STD_LOGIC;
184 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
185 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 data_f3_in_valid : IN STD_LOGIC;
187 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
188 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
190 data_f0_data_out_valid : OUT STD_LOGIC;
191 data_f0_data_out_valid_burst : OUT STD_LOGIC;
192 data_f0_data_out_ren : IN STD_LOGIC;
193 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
194 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
195 data_f1_data_out_valid : OUT STD_LOGIC;
196 data_f1_data_out_valid_burst : OUT STD_LOGIC;
197 data_f1_data_out_ren : IN STD_LOGIC;
198 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
199 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
200 data_f2_data_out_valid : OUT STD_LOGIC;
201 data_f2_data_out_valid_burst : OUT STD_LOGIC;
202 data_f2_data_out_ren : IN STD_LOGIC;
203 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
204 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
205 data_f3_data_out_valid : OUT STD_LOGIC;
206 data_f3_data_out_valid_burst : OUT STD_LOGIC;
207 data_f3_data_out_ren : IN STD_LOGIC;
208 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
209 END COMPONENT;
137
210
138 END;
211 END;
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@@ -8,3 +8,18 lpp_lfr/lpp_lfr.vhd
8 lpp_lfr/lpp_lfr_apbreg.vhd
8 lpp_lfr/lpp_lfr_apbreg.vhd
9 lpp_lfr/lpp_filter/FILTERcfg.vhd
9 lpp_lfr/lpp_filter/FILTERcfg.vhd
10 lpp_lfr/lpp_filter/lpp_lfr_filter.vhd
10 lpp_lfr/lpp_filter/lpp_lfr_filter.vhd
11 lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd
12 lpp_lfr/lpp_waveform/lpp_waveform.vhd
13 lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd
14 lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd
15 lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd
16 lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd
17 lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd
18 lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
19 lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd
20 AHB_DMA/lpp_dma_pkg.vhd
21 AHB_DMA/lpp_dma_send_1word.vhd
22 AHB_DMA/lpp_dma_send_16word.vhd
23 AHB_DMA/lpp_dma_singleOrBurst.vhd
24
25
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@@ -13,3 +13,8 Common/Register.vhd
13 Common/MUX.vhd
13 Common/MUX.vhd
14 Common/MUX2.vhd
14 Common/MUX2.vhd
15 Common/MUXN.vhd
15 Common/MUXN.vhd
16 Arbiter/RR_Arbiter_4.vhd
17 FIFO/FIFO_shared_memory_4channel_pkg.vhd
18 FIFO/FIFO_shared_memory_4channel.vhd
19 FIFO/FIFO_shared_memory_4channel_ctrl.vhd
20 FIFO/FIFO_shared_memory_4channel_headreg.vhd
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