diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_pkg.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_pkg.vhd @@ -0,0 +1,68 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE std.textio.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_dma_pkg_LPP_JCP IS + + COMPONENT lpp_dma_send_1word_LPP_JCP + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_dma_send_16word_LPP_JCP + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC); + END COMPONENT; + +END; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_16word.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_16word.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_16word.vhd @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_dma_send_16word_LPP_JCP IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- DMA + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + + -- + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + -- + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC + + ); +END lpp_dma_send_16word_LPP_JCP; + +ARCHITECTURE beh OF lpp_dma_send_16word_LPP_JCP IS + + TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY); + SIGNAL state : state_fsm_send_16word; + + SIGNAL data_counter : INTEGER; + SIGNAL grant_counter : INTEGER; + +BEGIN -- beh + + DMAIn.Beat <= HINCR16; + DMAIn.Size <= HSIZE32; + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + send_ok <= '0'; + send_ko <= '0'; + + DMAIn.Reset <= '1'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '1'; + DMAIn.Lock <= '0'; + data_counter <= 0; + grant_counter <= 0; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + DMAIn.Reset <= '0'; + + CASE state IS + WHEN IDLE => + DMAIn.Store <= '1'; + DMAIn.Request <= '0'; + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Address <= address; + data_counter <= 0; + DMAIn.Lock <= '0'; -- FIX test + IF send = '1' THEN + state <= REQUEST_BUS; + DMAIn.Request <= '1'; + DMAIn.Lock <= '1'; -- FIX test + DMAIn.Store <= '1'; + END IF; + WHEN REQUEST_BUS => + IF DMAOut.Grant = '1' THEN + data_counter <= 1; + grant_counter <= 1; + state <= SEND_DATA; + END IF; + WHEN SEND_DATA => + + IF DMAOut.Fault = '1' THEN + DMAIn.Reset <= '0'; + DMAIn.Address <= (OTHERS => '0'); + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + state <= ERROR0; + ELSE + + IF DMAOut.Grant = '1' THEN + IF grant_counter = 15 THEN + DMAIn.Reset <= '0'; + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + DMAIn.Burst <= '0'; + ELSE + grant_counter <= grant_counter+1; + END IF; + END IF; + + IF DMAOut.OKAY = '1' THEN + IF data_counter = 15 THEN + DMAIn.Address <= (OTHERS => '0'); + state <= WAIT_LAST_READY; + ELSE + data_counter <= data_counter + 1; + END IF; + END IF; + END IF; + + + WHEN WAIT_LAST_READY => + IF DMAOut.Ready = '1' THEN + IF grant_counter = 15 THEN + state <= IDLE; + send_ok <= '1'; + send_ko <= '0'; + ELSE + state <= ERROR0; + END IF; + END IF; + + WHEN ERROR0 => + state <= ERROR1; + WHEN ERROR1 => + send_ok <= '0'; + send_ko <= '1'; + state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + + DMAIn.Data <= data; + + ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE + '1'; + + -- \/ JC - 20/01/2014 \/ + --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE + -- '1'; + -- /\ JC - 20/01/2014 /\ + + -- \/ JC - 11/12/2013 \/ + --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + -- '1'; + -- /\ JC - 11/12/2013 /\ + + -- \/ JC - 10/12/2013 \/ + --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE + -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE + -- '1'; + -- /\ JC - 10/12/2013 /\ + + -- \/ JC - 09/12/2013 \/ + --ren <= '0' WHEN state = SEND_DATA ELSE + -- '1'; + -- /\ JC - 09/12/2013 /\ + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_1word.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_1word.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_send_1word.vhd @@ -0,0 +1,125 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_dma_send_1word_LPP_JCP IS + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- DMA + DMAIn : OUT DMA_In_Type; + DMAOut : IN DMA_OUt_Type; + -- + send : IN STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ren : OUT STD_LOGIC; + -- + send_ok : OUT STD_LOGIC; + send_ko : OUT STD_LOGIC + ); +END lpp_dma_send_1word_LPP_JCP; + +ARCHITECTURE beh OF lpp_dma_send_1word_LPP_JCP IS + + TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1); + SIGNAL state : state_fsm_send_1word; + +BEGIN -- beh + + DMAIn.Reset <= '0'; + DMAIn.Address <= address; + DMAIn.Data <= data; + DMAIn.Beat <= (OTHERS => '0'); + DMAIn.Size <= HSIZE32; + DMAIn.Burst <= '0'; + + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + state <= IDLE; + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Lock <= '0'; + ren <= '1'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + ren <= '1'; + CASE state IS + WHEN IDLE => + DMAIn.Store <= '1'; + DMAIn.Request <= '0'; + send_ok <= '0'; + send_ko <= '0'; + DMAIn.Lock <= '0'; + IF send = '1' THEN + DMAIn.Request <= '1'; + DMAIn.Lock <= '1'; + state <= REQUEST_BUS; + END IF; + WHEN REQUEST_BUS => + IF DMAOut.Grant = '1' THEN + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + state <= SEND_DATA; + ren <= '0'; + END IF; + WHEN SEND_DATA => + IF DMAOut.Fault = '1' THEN + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + state <= ERROR0; + ELSIF DMAOut.Ready = '1' THEN + DMAIn.Request <= '0'; + DMAIn.Store <= '0'; + send_ok <= '1'; + send_ko <= '0'; + state <= IDLE; + END IF; + WHEN ERROR0 => + state <= ERROR1; + WHEN ERROR1 => + send_ok <= '0'; + send_ko <= '1'; + state <= IDLE; + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS; + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_singleOrBurst.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_singleOrBurst.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/AHB_DMA/lpp_dma_singleOrBurst.vhd @@ -0,0 +1,187 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY staging; +USE staging.lpp_dma_pkg_LPP_JCP.ALL; + + +ENTITY lpp_dma_singleOrBurst_LPP_JCP IS + GENERIC ( + tech : INTEGER := inferred; + hindex : INTEGER := 2 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + -- + run : IN STD_LOGIC; + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE) + done : OUT STD_LOGIC; + ren : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + -- + debug_dmaout_okay : OUT STD_LOGIC + + ); +END; + +ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst_LPP_JCP IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + -- CONTROL + SIGNAL single_send : STD_LOGIC; + SIGNAL burst_send : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- SEND SINGLE MODULE + SIGNAL single_dmai : DMA_In_Type; + + SIGNAL single_send_ok : STD_LOGIC; + SIGNAL single_send_ko : STD_LOGIC; + SIGNAL single_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND SINGLE MODULE + SIGNAL burst_dmai : DMA_In_Type; + + SIGNAL burst_send_ok : STD_LOGIC; + SIGNAL burst_send_ko : STD_LOGIC; + SIGNAL burst_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_reg : STD_LOGIC; + SIGNAL send_s : STD_LOGIC; + + +BEGIN + + debug_dmaout_okay <= DMAOut.OKAY; + + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 10, + version => 0, + syncrst => 1, + boundary => 1) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + send_reg <= '0'; + ELSIF HCLK'event AND HCLK = '1' THEN + send_reg <= send; + END IF; + END PROCESS; + send_s <= send_reg; + + single_send <= send_s WHEN valid_burst = '0' ELSE '0'; + burst_send <= send_s WHEN valid_burst = '1' ELSE '0'; + + DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai; + + done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko; + + ren <= burst_ren WHEN valid_burst = '1' ELSE + single_ren; + + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word_LPP_JCP + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => single_dmai, + DMAOut => DMAOut, + + send => single_send, + address => address, + data => data_2_halfword, + ren => single_ren, + + send_ok => single_send_ok, + send_ko => single_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16); + + lpp_dma_send_16word_1 : lpp_dma_send_16word_LPP_JCP + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => burst_dmai, + DMAOut => DMAOut, + + send => burst_send, + address => address, + data => data_2_halfword, + ren => burst_ren, + + send_ok => burst_send_ok, + send_ko => burst_send_ko); + +END Behavioral; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/AMBA_Peripherals.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/AMBA_Peripherals.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/AMBA_Peripherals.vhd @@ -0,0 +1,108 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY staging; +USE staging.sample_type.ALL; + +PACKAGE AMBA_Peripherals_LPP_JCP IS + + COMPONENT apb_lfr_time_management_LPP_JCP IS + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used + nb_wait_period : INTEGER := 375 --! nb perdiod at clk49_152MHz + -- to wait before incremented the + -- fine time counter + ); + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time + ); + END COMPONENT; + + COMPONENT lpp_lfr_LPP_JCP + GENERIC ( + Mem_use : INTEGER; + nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER; + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq_ms : INTEGER; + pirq_wfp : INTEGER; + hindex : INTEGER; + top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sample_B : IN Samples14v(2 DOWNTO 0); + sample_E : IN Samples14v(4 DOWNTO 0); + sample_val : IN STD_LOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ahbi : IN AHB_Mst_In_Type; + ahbo : OUT AHB_Mst_Out_Type; + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + data_shaping_BW : OUT STD_LOGIC; + observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT lpp_dma_singleOrBurst_LPP_JCP + GENERIC ( + tech : INTEGER; + hindex : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + run : IN STD_LOGIC; + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + send : IN STD_LOGIC; + valid_burst : IN STD_LOGIC; + done : OUT STD_LOGIC; + ren : OUT STD_LOGIC; + address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + debug_dmaout_okay : OUT STD_LOGIC); + END COMPONENT; + +END; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/apb_lfr_time_management.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/apb_lfr_time_management.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/apb_lfr_time_management.vhd @@ -0,0 +1,268 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +LIBRARY staging; +USE staging.apb_devices_list_LPP_JCP.ALL; +USE staging.general_purpose_LPP_JCP.ALL; +USE staging.lpp_lfr_time_management_LPP_JCP.ALL; + +ENTITY apb_lfr_time_management_LPP_JCP IS + + GENERIC( + pindex : INTEGER := 0; --! APB slave index + paddr : INTEGER := 0; --! ADDR field of the APB BAR + pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR + pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used + nb_wait_period : INTEGER := 375 + ); + + PORT ( + clk25MHz : IN STD_LOGIC; --! Clock + clk49_152MHz : IN STD_LOGIC; --! secondary clock + resetn : IN STD_LOGIC; --! Reset + + grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received + apbi : IN apb_slv_in_type; --! APB slave input signals + apbo : OUT apb_slv_out_type; --! APB slave output signals + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time + ); + +END apb_lfr_time_management_LPP_JCP; + +ARCHITECTURE Behavioral OF apb_lfr_time_management_LPP_JCP IS + + CONSTANT REVISION : INTEGER := 1; + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask) + ); + + TYPE apb_lfr_time_management_Reg IS RECORD + ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + END RECORD; + + SIGNAL r : apb_lfr_time_management_Reg; + SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL force_tick : STD_LOGIC; + SIGNAL previous_force_tick : STD_LOGIC; + SIGNAL soft_tick : STD_LOGIC; + + SIGNAL irq1 : STD_LOGIC; + SIGNAL irq2 : STD_LOGIC; + + SIGNAL coarsetime_reg_updated : STD_LOGIC; + SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL coarse_time_new : STD_LOGIC; + SIGNAL coarse_time_new_49 : STD_LOGIC; + SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL fine_time_new : STD_LOGIC; + SIGNAL fine_time_new_temp : STD_LOGIC; + SIGNAL fine_time_new_49 : STD_LOGIC; + SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL tick : STD_LOGIC; + SIGNAL new_timecode : STD_LOGIC; + SIGNAL new_coarsetime : STD_LOGIC; + +BEGIN + ----------------------------------------------------------------------------- + -- TODO + -- IRQ 1 & 2 + ----------------------------------------------------------------------------- + irq2 <= '0'; + irq1 <= '0'; + + apbo.pirq(pirq) <= irq1; + apbo.pirq(pirq+1) <= irq2; + + PROCESS(resetn, clk25MHz) + BEGIN + + IF resetn = '0' THEN + Rdata <= (OTHERS => '0'); + r.coarse_time_load <= x"80000000"; + r.ctrl <= x"00000000"; + force_tick <= '0'; + previous_force_tick <= '0'; + soft_tick <= '0'; + + coarsetime_reg_updated <= '0'; + + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN + coarsetime_reg_updated <= '0'; + + force_tick <= r.ctrl(0); + previous_force_tick <= force_tick; + IF (previous_force_tick = '0') AND (force_tick = '1') THEN + soft_tick <= '1'; + ELSE + soft_tick <= '0'; + END IF; + +--APB Write OP + IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + r.ctrl <= apbi.pwdata(31 DOWNTO 0); + WHEN "000001" => + r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); + coarsetime_reg_updated <= '1'; + WHEN OTHERS => + END CASE; + ELSIF r.ctrl(0) = '1' THEN + r.ctrl(0) <= '0'; + END IF; + +--APB READ OP + IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN + CASE apbi.paddr(7 DOWNTO 2) IS + WHEN "000000" => + Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0); + WHEN "000001" => + Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); + WHEN "000010" => + Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); + WHEN "000011" => + Rdata(31 DOWNTO 16) <= (OTHERS => '0'); + Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0); + WHEN OTHERS => + Rdata(31 DOWNTO 0) <= x"00000000"; + END CASE; + END IF; + + END IF; + END PROCESS; + + apbo.prdata <= Rdata; + apbo.pconfig <= pconfig; + apbo.pindex <= pindex; + + coarse_time <= r.coarse_time; + fine_time <= r.fine_time; + ----------------------------------------------------------------------------- + + coarsetime_reg <= r.coarse_time_load; + r.coarse_time <= coarse_time_s; + r.fine_time <= fine_time_s; + ----------------------------------------------------------------------------- + + tick <= grspw_tick OR soft_tick; + + SYNC_VALID_BI_1 : SYNC_VALID_BIT_LPP_JCP + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk25MHz, + clk_out => clk49_152MHz, + rstn => resetn, + sin => tick, + sout => new_timecode); + + SYNC_VALID_BIT_2 : SYNC_VALID_BIT_LPP_JCP + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk25MHz, + clk_out => clk49_152MHz, + rstn => resetn, + sin => coarsetime_reg_updated, + sout => new_coarsetime); + + SYNC_FF_1 : SYNC_FF_LPP_JCP + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk25MHz, + rstn => resetn, + A => fine_time_new_49, + A_sync => fine_time_new_temp); + + lpp_edge_detection_1 : lpp_edge_detection_LPP_JCP + PORT MAP ( + clk => clk25MHz, + rstn => resetn, + sin => fine_time_new_temp, + sout => fine_time_new); + + SYNC_VALID_BIT_4 : SYNC_VALID_BIT_LPP_JCP + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk49_152MHz, + clk_out => clk25MHz, + rstn => resetn, + sin => coarse_time_new_49, + sout => coarse_time_new); + + PROCESS (clk25MHz, resetn) + BEGIN -- PROCESS + IF resetn = '0' THEN -- asynchronous reset (active low) + fine_time_s <= (OTHERS => '0'); + coarse_time_s <= (OTHERS => '0'); + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + IF fine_time_new = '1' THEN + fine_time_s <= fine_time_49; + END IF; + IF coarse_time_new = '1' THEN + coarse_time_s <= coarse_time_49; + END IF; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + -- LFR_TIME_MANAGMENT + ----------------------------------------------------------------------------- + lfr_time_management_1 : lfr_time_management_LPP_JCP + GENERIC MAP ( + nb_time_code_missing_limit => 60, + nb_wait_period => 375) + PORT MAP ( + clk => clk49_152MHz, + rstn => resetn, + + new_timecode => new_timecode, + new_coarsetime => new_coarsetime, + coarsetime_reg => coarsetime_reg, + + fine_time => fine_time_49, + fine_time_new => fine_time_new_49, + coarse_time => coarse_time_49, + coarse_time_new => coarse_time_new_49); + +END Behavioral; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lfr_time_management.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lfr_time_management.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lfr_time_management.vhd @@ -0,0 +1,116 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; +LIBRARY staging; +USE staging.lpp_lfr_time_management_LPP_JCP.ALL; + +ENTITY lfr_time_management_LPP_JCP IS + GENERIC ( + nb_time_code_missing_limit : INTEGER := 60; + nb_wait_pediod : INTEGER := 375 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + new_timecode : IN STD_LOGIC; -- transition signal information + new_coarsetime : IN STD_LOGIC; -- transition signal information + coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC + ); +END lfr_time_management_LPP_JCP; + +ARCHITECTURE Behavioral OF lfr_time_management_LPP_JCP IS + + SIGNAL counter_clear : STD_LOGIC; + SIGNAL counter_full : STD_LOGIC; + + SIGNAL nb_time_code_missing : INTEGER; + SIGNAL coarse_time_s : INTEGER; + + SIGNAL new_coarsetime_s : STD_LOGIC; + +BEGIN + + lpp_counter_1 : lpp_counter_LPP_JCP + GENERIC MAP ( + nb_wait_period => nb_wait_pediod, + nb_bit_of_data => 16) + PORT MAP ( + clk => clk, + rstn => rstn, + clear => counter_clear, + full => counter_full, + data => fine_time, + new_data => fine_time_new); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + nb_time_code_missing <= 0; + counter_clear <= '0'; + coarse_time_s <= 0; + coarse_time_new <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF new_coarsetime = '1' THEN + new_coarsetime_s <= '1'; + ELSIF new_timecode = '1' THEN + new_coarsetime_s <= '0'; + END IF; + + IF new_timecode = '1' THEN + coarse_time_new <= '1'; + IF new_coarsetime_s = '1' THEN + coarse_time_s <= to_integer(unsigned(coarsetime_reg)); + ELSE + coarse_time_s <= coarse_time_s + 1; + END IF; + nb_time_code_missing <= 0; + counter_clear <= '1'; + ELSE + coarse_time_new <= '0'; + counter_clear <= '0'; + IF counter_full = '1' THEN + coarse_time_new <= '1'; + coarse_time_s <= coarse_time_s + 1; + IF nb_time_code_missing = nb_time_code_missing_limit THEN + nb_time_code_missing <= nb_time_code_missing_limit; + ELSE + nb_time_code_missing <= nb_time_code_missing + 1; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + + coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31)); + coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0'; + +END Behavioral; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_counter.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_counter.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_counter.vhd @@ -0,0 +1,88 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +ENTITY lpp_counter_LPP_JCP IS + + GENERIC ( + nb_wait_period : INTEGER := 750; + nb_bit_of_data : INTEGER := 16 + ); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + clear : IN STD_LOGIC; + full : OUT STD_LOGIC; + data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0); + new_data : OUT STD_LOGIC + ); + +END lpp_counter_LPP_JCP; + +ARCHITECTURE beh OF lpp_counter_LPP_JCP IS + + SIGNAL counter_wait : INTEGER; + SIGNAL counter_data : INTEGER; + + SIGNAL new_data_s : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + counter_wait <= 0; + counter_data <= 0; + full <= '0'; + new_data_s <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF clear = '1' THEN + counter_wait <= 0; + counter_data <= 0; + full <= '0'; + new_data_s <= NOT new_data_s; + ELSE + IF counter_wait = nb_wait_period-1 THEN + counter_wait <= 0; + new_data_s <= NOT new_data_s; + IF counter_data = (2**nb_bit_of_data)-1 THEN + full <= '1'; + counter_data <= 0; + ELSE + full <= '0'; + counter_data <= counter_data +1; + END IF; + ELSE + full <= '0'; + counter_wait <= counter_wait +1; + END IF; + END IF; + END IF; + END PROCESS; + + data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data)); + new_data <= new_data_s; + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_lfr_time_management.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_lfr_time_management.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/apb_lfr_time_managment/lpp_lfr_time_management.vhd @@ -0,0 +1,64 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2013, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; + +PACKAGE lpp_lfr_time_management_LPP_JCP IS + + COMPONENT lfr_time_management_LPP_JCP + GENERIC ( + nb_time_code_missing_limit : INTEGER; + nb_wait_pediod : INTEGER := 375); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + new_timecode : IN STD_LOGIC; + new_coarsetime : IN STD_LOGIC; + coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + fine_time_new : OUT STD_LOGIC; + coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + coarse_time_new : OUT STD_LOGIC + ); + END COMPONENT; + + COMPONENT lpp_counter_LPP_JCP + GENERIC ( + nb_wait_period : INTEGER; + nb_bit_of_data : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + clear : IN STD_LOGIC; + full : OUT STD_LOGIC; + data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0); + new_data : OUT STD_LOGIC); + END COMPONENT; + +END lpp_lfr_time_management__LPP_JCP; + diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr.vhd --- a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr.vhd +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr.vhd @@ -14,6 +14,7 @@ USE GRLIB.DMA2AHB_Package.ALL; LIBRARY staging; USE staging.sample_type_LPP_JCP.ALL; USE staging.lpp_lfr_pkg_LPP_JCP.ALL; +USE staging.general_purpose_LPP_JCP.ALL; USE staging.memory_LPP_JCP.ALL; ENTITY lpp_lfr_LPP_JCP IS diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_pkg.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_pkg.vhd --- a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_pkg.vhd +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_lfr_pkg.vhd @@ -134,5 +134,78 @@ PACKAGE lpp_lfr_pkg_LPP_JCP IS sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0)); END COMPONENT; + + ----------------------------------------------------------------------------- + -- lpp_waveform + ----------------------------------------------------------------------------- + COMPONENT lpp_waveform_LPP_JCP + GENERIC ( + tech : INTEGER; + data_size : INTEGER; + nb_data_by_buffer_size : INTEGER; + nb_word_by_buffer_size : INTEGER; + nb_snapshot_param_size : INTEGER; + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_in_valid : IN STD_LOGIC; + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_in_valid : IN STD_LOGIC; + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_in_valid : IN STD_LOGIC; + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out_valid : OUT STD_LOGIC; + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f0_data_out_ren : IN STD_LOGIC; + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_ren : IN STD_LOGIC; + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_ren : IN STD_LOGIC; + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_ren : IN STD_LOGIC; + observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; END; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform.vhd @@ -0,0 +1,463 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY staging; +USE staging.lpp_waveform_pkg_LPP_JCP.ALL; +USE staging.general_purpose_LPP_JCP.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_LPP_JCP IS + + GENERIC ( + tech : INTEGER := inferred; + data_size : INTEGER := 96; --16*6 + nb_data_by_buffer_size : INTEGER := 11; + nb_word_by_buffer_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + ---- AMBA AHB Master Interface + --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO + --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO + + --config + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + + enable_f0 : IN STD_LOGIC; + enable_f1 : IN STD_LOGIC; + enable_f2 : IN STD_LOGIC; + enable_f3 : IN STD_LOGIC; + + burst_f0 : IN STD_LOGIC; + burst_f1 : IN STD_LOGIC; + burst_f2 : IN STD_LOGIC; + + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + --------------------------------------------------------------------------- + -- INPUT + coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + + --f0 + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_in_valid : IN STD_LOGIC; + data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f1 + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_in_valid : IN STD_LOGIC; + data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f2 + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_in_valid : IN STD_LOGIC; + data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + --f3 + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_in_valid : IN STD_LOGIC; + data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + --------------------------------------------------------------------------- + -- OUTPUT + --f0 + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f0_data_out_valid : OUT STD_LOGIC; + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f0_data_out_ren : IN STD_LOGIC; + --f1 + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_ren : IN STD_LOGIC; + --f2 + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_ren : IN STD_LOGIC; + --f3 + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_ren : IN STD_LOGIC; + + --------------------------------------------------------------------------- + -- + observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END lpp_waveform_LPP_JCP; + +ARCHITECTURE beh OF lpp_waveform_LPP_JCP IS + SIGNAL start_snapshot_f0 : STD_LOGIC; + SIGNAL start_snapshot_f1 : STD_LOGIC; + SIGNAL start_snapshot_f2 : STD_LOGIC; + + SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + + SIGNAL data_f0_out_valid : STD_LOGIC; + SIGNAL data_f1_out_valid : STD_LOGIC; + SIGNAL data_f2_out_valid : STD_LOGIC; + SIGNAL data_f3_out_valid : STD_LOGIC; + SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0); + -- + SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0); + -- + SIGNAL run : STD_LOGIC; + -- + TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0); + SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug + SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0); + SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0); + -- + + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- + + SIGNAL observation_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- DEBUG + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + observation_reg <= (OTHERS => '0'); + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + observation_reg <= observation_reg_s; + END IF; + END PROCESS; + observation_reg_s( 2 DOWNTO 0) <= start_snapshot_f2 & start_snapshot_f1 & start_snapshot_f0; + observation_reg_s( 5 DOWNTO 3) <= data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + observation_reg_s( 8 DOWNTO 6) <= status_full_s(2 DOWNTO 0) ; + observation_reg_s(11 DOWNTO 9) <= status_full_ack(2 DOWNTO 0); + observation_reg_s(14 DOWNTO 12) <= data_wen(2 DOWNTO 0); + observation_reg_s(31 DOWNTO 15) <= (OTHERS => '0'); + ----------------------------------------------------------------------------- + + lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler_LPP_JCP + GENERIC MAP ( + delta_vector_size => delta_vector_size, + delta_vector_size_f0_2 => delta_vector_size_f0_2 + ) + PORT MAP ( + clk => clk, + rstn => rstn, + reg_run => reg_run, + reg_start_date => reg_start_date, + reg_delta_snapshot => reg_delta_snapshot, + reg_delta_f0 => reg_delta_f0, + reg_delta_f0_2 => reg_delta_f0_2, + reg_delta_f1 => reg_delta_f1, + reg_delta_f2 => reg_delta_f2, + coarse_time => coarse_time(30 DOWNTO 0), + data_f0_valid => data_f0_in_valid, + data_f2_valid => data_f2_in_valid, + start_snapshot_f0 => start_snapshot_f0, + start_snapshot_f1 => start_snapshot_f1, + start_snapshot_f2 => start_snapshot_f2, + wfp_on => run); + + lpp_waveform_snapshot_f0 : lpp_waveform_snapshot_LPP_JCP + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f0, + burst_enable => burst_f0, + nb_snapshot_param => nb_snapshot_param, + start_snapshot => start_snapshot_f0, + data_in => data_f0_in, + data_in_valid => data_f0_in_valid, + data_out => data_f0_out, + data_out_valid => data_f0_out_valid); + + nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1; + + lpp_waveform_snapshot_f1 : lpp_waveform_snapshot_LPP_JCP + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f1, + burst_enable => burst_f1, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f1, + data_in => data_f1_in, + data_in_valid => data_f1_in_valid, + data_out => data_f1_out, + data_out_valid => data_f1_out_valid); + + lpp_waveform_snapshot_f2 : lpp_waveform_snapshot_LPP_JCP + GENERIC MAP ( + data_size => data_size, + nb_snapshot_param_size => nb_snapshot_param_size+1) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f2, + burst_enable => burst_f2, + nb_snapshot_param => nb_snapshot_param_more_one, + start_snapshot => start_snapshot_f2, + data_in => data_f2_in, + data_in_valid => data_f2_in_valid, + data_out => data_f2_out, + data_out_valid => data_f2_out_valid); + + lpp_waveform_burst_f3 : lpp_waveform_burst_LPP_JCP + GENERIC MAP ( + data_size => data_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + enable => enable_f3, + data_in => data_f3_in, + data_in_valid => data_f3_in_valid, + data_out => data_f3_out, + data_out_valid => data_f3_out_valid); + ----------------------------------------------------------------------------- + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + time_reg1 <= (OTHERS => '0'); + time_reg2 <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + time_reg1 <= fine_time & coarse_time; + time_reg2 <= time_reg1; + END IF; + END PROCESS; + + valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid; + all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE + lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid_LPP_JCP + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + run => run, + valid_in => valid_in(I), + ack_in => valid_ack(I), + time_in => time_reg2, -- Todo + valid_out => valid_out(I), + time_out => time_out(I), -- Todo + error => status_new_err(I)); + END GENERATE all_input_valid; + + all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE + data_out(0, I) <= data_f0_out(I); + data_out(1, I) <= data_f1_out(I); + data_out(2, I) <= data_f2_out(I); + data_out(3, I) <= data_f3_out(I); + END GENERATE all_bit_of_data_out; + + ----------------------------------------------------------------------------- + all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE + all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE + time_out_2(J, I) <= time_out(J)(I); + END GENERATE all_sample_of_time_out; + END GENERATE all_bit_of_time_out; + + lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter_LPP_JCP + GENERIC MAP (tech => tech, + nb_data_by_buffer_size => nb_data_by_buffer_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + nb_data_by_buffer => nb_data_by_buffer, + data_in_valid => valid_out, + data_in_ack => valid_ack, + data_in => data_out, + time_in => time_out_2, + + data_out => wdata, + data_out_wen => data_wen, + full_almost => full_almost, + full => full); + + ----------------------------------------------------------------------------- + + lpp_waveform_fifo_1 : FIFO_shared_memory_4channel_LPP_JCP + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + empty => s_empty, + empty_almost => s_empty_almost, + data_ren => s_data_ren, + rdata => s_rdata, + + + full_almost => full_almost, + full => full, + data_wen => data_wen, + wdata => wdata); + + lpp_waveform_fifo_headreg_1 : FIFO_shared_memory_4channel_headreg_LPP_JCP + GENERIC MAP (tech => tech) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + o_empty_almost => empty_almost, + o_empty => empty, + + o_data_ren => data_ren, + o_rdata_0 => data_f0_data_out, + o_rdata_1 => data_f1_data_out, + o_rdata_2 => data_f2_data_out, + o_rdata_3 => data_f3_data_out, + + i_empty_almost => s_empty_almost, + i_empty => s_empty, + i_data_ren => s_data_ren, + i_rdata => s_rdata); + + data_ren <= data_f3_data_out_ren & + data_f2_data_out_ren & + data_f1_data_out_ren & + data_f0_data_out_ren; + + lpp_waveform_gen_address_1 : lpp_waveform_genaddress_LPP_JCP + GENERIC MAP ( + nb_data_by_buffer_size => nb_word_by_buffer_size) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + + ------------------------------------------------------------------------- + -- CONFIG + ------------------------------------------------------------------------- + nb_data_by_buffer => nb_word_by_buffer, + + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3, + ------------------------------------------------------------------------- + -- CTRL + ------------------------------------------------------------------------- + -- IN + empty => empty, + empty_almost => empty_almost, + data_ren => data_ren, + + ------------------------------------------------------------------------- + -- STATUS + ------------------------------------------------------------------------- + status_full => status_full_s, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + + ------------------------------------------------------------------------- + -- ADDR DATA OUT + ------------------------------------------------------------------------- + data_f0_data_out_valid_burst => data_f0_data_out_valid_burst, + data_f1_data_out_valid_burst => data_f1_data_out_valid_burst, + data_f2_data_out_valid_burst => data_f2_data_out_valid_burst, + data_f3_data_out_valid_burst => data_f3_data_out_valid_burst, + + data_f0_data_out_valid => data_f0_data_out_valid, + data_f1_data_out_valid => data_f1_data_out_valid, + data_f2_data_out_valid => data_f2_data_out_valid, + data_f3_data_out_valid => data_f3_data_out_valid, + + data_f0_addr_out => data_f0_addr_out, + data_f1_addr_out => data_f1_addr_out, + data_f2_addr_out => data_f2_addr_out, + data_f3_addr_out => data_f3_addr_out + ); + + status_full <= status_full_s; + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd @@ -0,0 +1,43 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY lpp_waveform_burst_LPP_JCP IS + + GENERIC ( + data_size : INTEGER := 16); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + enable : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_burst_LPP_JCP; + +ARCHITECTURE beh OF lpp_waveform_burst_LPP_JCP IS +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' OR run = '0' THEN + data_out_valid <= '0'; + ELSE + data_out_valid <= data_in_valid; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd @@ -0,0 +1,98 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + + +ENTITY lpp_waveform_dma_genvalid_LPP_JCP IS + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + run : IN STD_LOGIC; + + valid_in : IN STD_LOGIC; + time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + + ack_in : IN STD_LOGIC; + valid_out : OUT STD_LOGIC; + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error : OUT STD_LOGIC + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid_LPP_JCP IS + TYPE state_fsm IS (IDLE, VALID); + SIGNAL state : state_fsm; +BEGIN + + FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn) + BEGIN + IF HRESETn = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + time_out <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN + CASE state IS + WHEN IDLE => + + valid_out <= '0'; + error <= '0'; + IF run = '1' AND valid_in = '1' THEN + state <= VALID; + valid_out <= '1'; + time_out <= time_in; + END IF; + + WHEN VALID => + IF run = '0' THEN + state <= IDLE; + valid_out <= '0'; + error <= '0'; + ELSE + IF valid_in = '1' THEN + IF ack_in = '1' THEN + state <= VALID; + valid_out <= '1'; + time_out <= time_in; + ELSE + state <= IDLE; + error <= '1'; + valid_out <= '0'; + END IF; + ELSIF ack_in = '1' THEN + state <= IDLE; + valid_out <= '0'; + END IF; + END IF; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END PROCESS FSM_SELECT_ADDRESS; + +END Behavioral; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd @@ -0,0 +1,277 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ + +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY staging; +USE staging.lpp_waveform_pkg_LPP_JCP.ALL; +USE staging.general_purpose_LPP_JCP.ALL; + +ENTITY lpp_waveform_fifo_arbiter_LPP_JCP IS + GENERIC( + tech : INTEGER := 0; + nb_data_by_buffer_size : INTEGER := 11 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); + --------------------------------------------------------------------------- + -- SNAPSHOT INTERFACE (INPUT) + --------------------------------------------------------------------------- + data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + + --------------------------------------------------------------------------- + -- FIFO INTERFACE (OUTPUT) + --------------------------------------------------------------------------- + data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + full : IN STD_LOGIC_VECTOR(3 DOWNTO 0) + + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter_LPP_JCP IS + TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST); + SIGNAL state : state_type_fifo_arbiter; + + ----------------------------------------------------------------------------- + -- DATA MUX + ----------------------------------------------------------------------------- + SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); + TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0); + SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- RR and SELECTION + ----------------------------------------------------------------------------- + SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL sel_reg : STD_LOGIC; + SIGNAL sel_ack : STD_LOGIC; + SIGNAL no_sel : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- REG + ----------------------------------------------------------------------------- + SIGNAL count_enable : STD_LOGIC; + SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- CONTROL + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + count_enable <= '0'; + data_in_ack <= (OTHERS => '0'); + data_out_wen <= (OTHERS => '1'); + sel_ack <= '0'; + state <= IDLE; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + count_enable <= '0'; + data_in_ack <= (OTHERS => '0'); + data_out_wen <= (OTHERS => '1'); + sel_ack <= '0'; + IF run = '0' THEN + state <= IDLE; + ELSE + CASE state IS + WHEN IDLE => + IF no_sel = '0' THEN + state <= TIME1; + END IF; + WHEN TIME1 => + count_enable <= '1'; + IF UNSIGNED(count) = 0 THEN + state <= TIME2; + data_out_wen <= NOT sel; + data_out <= data_sel(0); + ELSE + state <= DATA1; + END IF; + WHEN TIME2 => + data_out_wen <= NOT sel; + data_out <= data_sel(1) ; + state <= DATA1; + WHEN DATA1 => + data_out_wen <= NOT sel; + data_out <= data_sel(2); + state <= DATA2; + WHEN DATA2 => + data_out_wen <= NOT sel; + data_out <= data_sel(3); + state <= DATA3; + WHEN DATA3 => + data_out_wen <= NOT sel; + data_out <= data_sel(4); + state <= LAST; + data_in_ack <= sel; + WHEN LAST => + state <= IDLE; + sel_ack <= '1'; + + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + ----------------------------------------------------------------------------- + -- DATA MUX + ----------------------------------------------------------------------------- + all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE + I_time_in: IF I < 48 GENERATE + data_0_v(I) <= time_in(0,I); + data_1_v(I) <= time_in(1,I); + data_2_v(I) <= time_in(2,I); + data_3_v(I) <= time_in(3,I); + END GENERATE I_time_in; + I_null: IF (I > 47) AND (I < 32*2) GENERATE + data_0_v(I) <= '0'; + data_1_v(I) <= '0'; + data_2_v(I) <= '0'; + data_3_v(I) <= '0'; + END GENERATE I_null; + I_data_in: IF I > 32*2-1 GENERATE + data_0_v(I) <= data_in(0,I-32*2); + data_1_v(I) <= data_in(1,I-32*2); + data_2_v(I) <= data_in(2,I-32*2); + data_3_v(I) <= data_in(3,I-32*2); + END GENERATE I_data_in; + END GENERATE all_bit_data_in; + + all_word: FOR J IN 4 DOWNTO 0 GENERATE + all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE + data_0(J)(I) <= data_0_v(J*32+I); + data_1(J)(I) <= data_1_v(J*32+I); + data_2(J)(I) <= data_2_v(J*32+I); + data_3(J)(I) <= data_3_v(J*32+I); + END GENERATE all_data_bit; + END GENERATE all_word; + + data_sel <= data_0 WHEN sel(0) = '1' ELSE + data_1 WHEN sel(1) = '1' ELSE + data_2 WHEN sel(2) = '1' ELSE + data_3; + + + ----------------------------------------------------------------------------- + -- RR and SELECTION + ----------------------------------------------------------------------------- + all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE + valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I); + END GENERATE all_input_rr; + + RR_Arbiter_4_1 : RR_Arbiter_4_LPP_JCP + PORT MAP ( + clk => clk, + rstn => rstn, + in_valid => valid_in_rr, + out_grant => sel_s); + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + sel <= "0000"; + sel_reg <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF sel_reg = '0' OR sel_ack = '1' THEN + sel <= sel_s; + IF sel_s = "0000" THEN + sel_reg <= '0'; + ELSE + sel_reg <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + no_sel <= '1' WHEN sel = "0000" ELSE '0'; + + ----------------------------------------------------------------------------- + -- REG + ----------------------------------------------------------------------------- + reg_count_i: lpp_waveform_fifo_arbiter_reg_LPP_JCP + GENERIC MAP ( + data_size => nb_data_by_buffer_size, + data_nb => 4) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + max_count => nb_data_by_buffer, + enable => count_enable, + sel => sel, + data => count, + data_s => count_s); + + + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd @@ -0,0 +1,113 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY lpp_waveform_fifo_arbiter_reg_LPP_JCP IS + GENERIC( + data_size : INTEGER; + data_nb : INTEGER + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); + + enable : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); + + data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg_LPP_JCP IS + + TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; + SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0); + + SIGNAL reg_sel : INTEGER := 0; + SIGNAL reg_sel_s : INTEGER := 0; + +BEGIN + + all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + reg(I) <= 0; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '0' THEN + reg(I) <= 0; + ELSE + IF sel(I) = '1' THEN + reg(I) <= reg_sel_s; + END IF; + END IF; + END IF; + END PROCESS; + END GENERATE all_reg; + + reg_sel <= reg(0) WHEN sel(0) = '1' ELSE + reg(1) WHEN sel(1) = '1' ELSE + reg(2) WHEN sel(2) = '1' ELSE + reg(3); + + reg_sel_s <= reg_sel WHEN enable = '0' ELSE + reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE + 0; + + data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size)); + data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size)); + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd @@ -0,0 +1,255 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY staging; +USE staging.lpp_waveform_pkg_LPP_JCP .ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_waveform_genaddress_LPP_JCP IS + + GENERIC ( + nb_data_by_buffer_size : INTEGER); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + ------------------------------------------------------------------------- + -- CONFIG + ------------------------------------------------------------------------- + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + ------------------------------------------------------------------------- + -- CTRL + ------------------------------------------------------------------------- + empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + + ------------------------------------------------------------------------- + -- STATUS + ------------------------------------------------------------------------- + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + + ------------------------------------------------------------------------- + -- ADDR DATA OUT + ------------------------------------------------------------------------- + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + + data_f0_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid : OUT STD_LOGIC; + + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + + ); + +END lpp_waveform_genaddress_LPP_JCP; + +ARCHITECTURE beh OF lpp_waveform_genaddress_LPP_JCP IS + SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0); + ----------------------------------------------------------------------------- + -- Valid gen + ----------------------------------------------------------------------------- + SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0); + + ----------------------------------------------------------------------------- + -- Register + ----------------------------------------------------------------------------- + SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0); + SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + + TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0); + SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0); + SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0); + + SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0); + +BEGIN -- beh + + ----------------------------------------------------------------------------- + -- valid gen + ----------------------------------------------------------------------------- + data_f0_data_out_valid <= data_out_valid(0); + data_f1_data_out_valid <= data_out_valid(1); + data_f2_data_out_valid <= data_out_valid(2); + data_f3_data_out_valid <= data_out_valid(3); + + data_f0_data_out_valid_burst <= data_out_valid_burst(0); + data_f1_data_out_valid_burst <= data_out_valid_burst(1); + data_f2_data_out_valid_burst <= data_out_valid_burst(2); + data_f3_data_out_valid_burst <= data_out_valid_burst(3); + + + + all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE + addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I)); + + addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000") + AND (UNSIGNED(addr_avail(I)) > 15) + ELSE '0'; + + data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE + '0' WHEN empty(I) = '1' ELSE + '0' WHEN addr_burst_avail(I) = '1' ELSE + '0' WHEN (run = '0') ELSE + '1'; + + data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE + '0' WHEN empty(I) = '1' ELSE + '0' WHEN addr_burst_avail(I) = '0' ELSE + '0' WHEN empty_almost(I) = '1' ELSE + '0' WHEN (run = '0') ELSE + '1'; + END GENERATE all_bit_data_valid_out; + + ----------------------------------------------------------------------------- + -- Register + ----------------------------------------------------------------------------- + all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE + all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + data_addr_v_reg(I, J) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '1' AND status_full_ack(I) = '0' THEN + data_addr_v_reg(I, J) <= data_addr_v_pre(I, J); + ELSE + data_addr_v_reg(I, J) <= data_addr_v_base(I, J); + END IF; + END IF; + END PROCESS; + + data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J); + + END GENERATE all_data_addr; + + data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE + data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE + data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE + data_addr_v_reg(3, J); + + data_addr_v_base(0, J) <= addr_data_f0_s(J); + data_addr_v_base(1, J) <= addr_data_f1_s(J); + data_addr_v_base(2, J) <= addr_data_f2_s(J); + data_addr_v_base(3, J) <= addr_data_f3_s(J); + + data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ; + data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ; + data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ; + data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ; + + END GENERATE all_data_bit; + + addr_data_f0_s <= addr_data_f0(31 DOWNTO 2); + addr_data_f1_s <= addr_data_f1(31 DOWNTO 2); + addr_data_f2_s <= addr_data_f2(31 DOWNTO 2); + addr_data_f3_s <= addr_data_f3(31 DOWNTO 2); + + data_f0_addr_out(1 DOWNTO 0) <= "00"; + data_f1_addr_out(1 DOWNTO 0) <= "00"; + data_f2_addr_out(1 DOWNTO 0) <= "00"; + data_f3_addr_out(1 DOWNTO 0) <= "00"; + + + + + ----------------------------------------------------------------------------- + -- ADDER + ----------------------------------------------------------------------------- + + data_addr_pre <= data_addr_reg + 1; + + ----------------------------------------------------------------------------- + -- FULL STATUS + ----------------------------------------------------------------------------- + all_status : FOR I IN 3 DOWNTO 0 GENERATE + all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE + addr_v_p(I)(J) <= data_addr_v_pre(I, J); + addr_v_b(I)(J) <= data_addr_v_base(I, J); + END GENERATE all_bit_addr; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + status_full_s(I) <= '0'; + status_full_err(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF run = '1' AND status_full_ack(I) = '0' THEN + IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN + status_full_s(I) <= '1'; + IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN + status_full_err(I) <= '1'; + END IF; + END IF; + ELSE + status_full_s(I) <= '0'; + status_full_err(I) <= '0'; + END IF; + END IF; + END PROCESS; + + END GENERATE all_status; + + status_full <= status_full_s; + + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd @@ -0,0 +1,186 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +PACKAGE lpp_waveform_pkg_LPP_JCP IS + + TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; + + ----------------------------------------------------------------------------- + -- SNAPSHOT + ----------------------------------------------------------------------------- + + COMPONENT lpp_waveform_snapshot_LPP_JCP + GENERIC ( + data_size : INTEGER; + nb_snapshot_param_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + start_snapshot : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_burst_LPP_JCP + GENERIC ( + data_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + enable : IN STD_LOGIC; + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_snapshot_controler_LPP_JCP + GENERIC ( + delta_vector_size : INTEGER; + delta_vector_size_f0_2 : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + data_f0_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC; + wfp_on : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_waveform_dma_genvalid_LPP_JCP + PORT ( + HCLK : IN STD_LOGIC; + HRESETn : IN STD_LOGIC; + run : IN STD_LOGIC; + valid_in : IN STD_LOGIC; + ack_in : IN STD_LOGIC; + time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + valid_out : OUT STD_LOGIC; + time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); + error : OUT STD_LOGIC); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- FIFO + ----------------------------------------------------------------------------- + COMPONENT lpp_waveform_fifo_arbiter_LPP_JCP + GENERIC ( + tech : INTEGER; + nb_data_by_buffer_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0); + data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0); + time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0); + data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- GEN ADDRESS + ----------------------------------------------------------------------------- + COMPONENT lpp_waveform_genaddress_LPP_JCP + GENERIC ( + nb_data_by_buffer_size : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_f0_data_out_valid_burst : OUT STD_LOGIC; + data_f1_data_out_valid_burst : OUT STD_LOGIC; + data_f2_data_out_valid_burst : OUT STD_LOGIC; + data_f3_data_out_valid_burst : OUT STD_LOGIC; + data_f0_data_out_valid : OUT STD_LOGIC; + data_f1_data_out_valid : OUT STD_LOGIC; + data_f2_data_out_valid : OUT STD_LOGIC; + data_f3_data_out_valid : OUT STD_LOGIC; + data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- lpp_waveform_fifo_arbiter_reg + ----------------------------------------------------------------------------- + COMPONENT lpp_waveform_fifo_arbiter_reg_LPP_JCP + GENERIC ( + data_size : INTEGER; + data_nb : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0); + enable : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0); + data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)); + END COMPONENT; + +END lpp_waveform_pkg_LPP_JCP; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd @@ -0,0 +1,81 @@ +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot_LPP_JCP IS + + GENERIC ( + data_size : INTEGER := 16; + nb_snapshot_param_size : INTEGER := 11); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + + enable : IN STD_LOGIC; + burst_enable : IN STD_LOGIC; + nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + + start_snapshot : IN STD_LOGIC; + + data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_in_valid : IN STD_LOGIC; + + data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + data_out_valid : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot_LPP_JCP; + +ARCHITECTURE beh OF lpp_waveform_snapshot_LPP_JCP IS + SIGNAL counter_points_snapshot : INTEGER; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + data_out <= (OTHERS => '0'); + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSIF clk'EVENT AND clk = '1' THEN + data_out <= data_in; + IF enable = '0' OR run = '0' THEN + data_out_valid <= '0'; + counter_points_snapshot <= 0; + ELSE + IF burst_enable = '1' THEN + -- BURST ModE -- + data_out_valid <= data_in_valid; + counter_points_snapshot <= 0; + ELSE + -- SNAPShOT MODE -- + IF start_snapshot = '1' THEN + IF data_in_valid = '1' THEN + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)) - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= to_integer(unsigned(nb_snapshot_param)); + data_out_valid <= '0'; + END IF; + ELSE + IF data_in_valid = '1' THEN + IF counter_points_snapshot > 0 THEN + counter_points_snapshot <= counter_points_snapshot - 1; + data_out_valid <= '1'; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + ELSE + counter_points_snapshot <= counter_points_snapshot; + data_out_valid <= '0'; + END IF; + END IF; + + END IF; + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -0,0 +1,223 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot_controler_LPP_JCP IS + + GENERIC ( + delta_vector_size : INTEGER := 20; + delta_vector_size_f0_2 : INTEGER := 3 + ); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + --REGISTER CONTROL + reg_run : IN STD_LOGIC; + reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + --------------------------------------------------------------------------- + -- INPUT + coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0); + data_f0_valid : IN STD_LOGIC; + data_f2_valid : IN STD_LOGIC; + --------------------------------------------------------------------------- + -- OUTPUT + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC; + wfp_on : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot_controler_LPP_JCP; + +ARCHITECTURE beh OF lpp_waveform_snapshot_controler_LPP_JCP IS + ----------------------------------------------------------------------------- + -- WAVEFORM ON/OFF FSM + SIGNAL state_on : STD_LOGIC; + SIGNAL wfp_on_s : STD_LOGIC; + ----------------------------------------------------------------------------- + -- StartSnapshot Generator for f2, f1 and f0_pre + SIGNAL start_snapshot_f0_pre : STD_LOGIC; +-- SIGNAL first_decount_s : STD_LOGIC; + SIGNAL first_decount : STD_LOGIC; + SIGNAL first_init : STD_LOGIC; + SIGNAL counter_delta_snapshot : INTEGER; + ----------------------------------------------------------------------------- + -- StartSnapshot Generator for f0 + SIGNAL counter_delta_f0 : INTEGER; + SIGNAL send_start_snapshot_f0 : STD_LOGIC; +BEGIN -- beh + wfp_on <= wfp_on_s; + + ----------------------------------------------------------------------------- + -- WAVEFORM ON/OFF FSM + ----------------------------------------------------------------------------- + -- INPUT reg_run + -- coarse_time + -- reg_start_date + -- OUTPUT wfp_on_s + ----------------------------------------------------------------------------- + waveform_on_off_fsm : PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + state_on <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF state_on = '1' THEN -- Waveform Picker ON + state_on <= reg_run; + ELSE -- Waveform Picker OFF + IF coarse_time = reg_start_date THEN + state_on <= reg_run; + END IF; + END IF; + END IF; + END PROCESS waveform_on_off_fsm; + wfp_on_s <= state_on; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- StartSnapshot Generator for f2, f1 and f0_pre + ----------------------------------------------------------------------------- + -- INPUT wfp_on_s + -- reg_delta_snapshot + -- reg_delta_f0 + -- reg_delta_f1 + -- reg_delta_f2 + -- data_f2_valid + -- OUTPUT start_snapshot_f0_pre + -- start_snapshot_f1 + -- start_snapshot_f2 + ----------------------------------------------------------------------------- + --lpp_front_positive_detection_1 : lpp_front_positive_detection + -- PORT MAP ( + -- clk => clk, + -- rstn => rstn, + -- sin => wfp_on_s, + -- sout => first_decount_s); + + Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn) + BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot + IF rstn = '0' THEN -- asynchronous reset (active low) + counter_delta_snapshot <= 0; + first_decount <= '1'; + first_init <= '1'; + start_snapshot_f0_pre <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF wfp_on_s = '0' THEN + counter_delta_snapshot <= 0; + first_decount <= '1'; + first_init <= '1'; + start_snapshot_f0_pre <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + ELSE + start_snapshot_f0_pre <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + + IF data_f2_valid = '1' THEN + IF first_init = '1' THEN + counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2)); + first_init <= '0'; + ELSE + IF counter_delta_snapshot > 0 THEN + counter_delta_snapshot <= counter_delta_snapshot - 1; + ELSE + counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot)); + first_decount <= '0'; + END IF; + + IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN + IF first_decount = '0' THEN + start_snapshot_f0_pre <= '1'; + END IF; + END IF; + + IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN + IF first_decount = '0' THEN + start_snapshot_f1 <= '1'; + END IF; + END IF; + + IF counter_delta_snapshot = 0 THEN + start_snapshot_f2 <= '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS Decounter_Cyclic_DeltaSnapshot; + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- StartSnapshot Generator for f0 + ----------------------------------------------------------------------------- + -- INPUT wfp_on_s + -- start_snapshot_f0_pre + -- reg_delta_snapshot + -- reg_delta_f0_2 + -- data_f0_valid + -- OUTPUT start_snapshot_f0 + ----------------------------------------------------------------------------- + Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn) + BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot + IF rstn = '0' THEN -- asynchronous reset (active low) + counter_delta_f0 <= 0; + start_snapshot_f0 <= '0'; + send_start_snapshot_f0 <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + start_snapshot_f0 <= '0'; + IF wfp_on_s = '0' THEN + counter_delta_f0 <= 0; + send_start_snapshot_f0 <= '1'; + ELSE + IF start_snapshot_f0_pre = '1' THEN + send_start_snapshot_f0 <= '0'; + counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2)); + ELSIF data_f0_valid = '1' THEN + IF counter_delta_f0 > 0 THEN + send_start_snapshot_f0 <= '0'; + counter_delta_f0 <= counter_delta_f0 - 1; + ELSE + IF send_start_snapshot_f0 = '0' THEN + send_start_snapshot_f0 <= '1'; + start_snapshot_f0 <= '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS Decounter_DeltaSnapshot_f0; + ----------------------------------------------------------------------------- + +END beh; diff --git a/lib/staging/LPP/JCP/AMBA_Peripherals/vhdlsyn.txt b/lib/staging/LPP/JCP/AMBA_Peripherals/vhdlsyn.txt --- a/lib/staging/LPP/JCP/AMBA_Peripherals/vhdlsyn.txt +++ b/lib/staging/LPP/JCP/AMBA_Peripherals/vhdlsyn.txt @@ -8,3 +8,18 @@ lpp_lfr/lpp_lfr.vhd lpp_lfr/lpp_lfr_apbreg.vhd lpp_lfr/lpp_filter/FILTERcfg.vhd lpp_lfr/lpp_filter/lpp_lfr_filter.vhd +lpp_lfr/lpp_waveform/lpp_waveform_pkg.vhd +lpp_lfr/lpp_waveform/lpp_waveform.vhd +lpp_lfr/lpp_waveform/lpp_waveform_burst.vhd +lpp_lfr/lpp_waveform/lpp_waveform_snapshot.vhd +lpp_lfr/lpp_waveform/lpp_waveform_snapshot_controler.vhd +lpp_lfr/lpp_waveform/lpp_waveform_dma_genvalid.vhd +lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +lpp_lfr/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd +lpp_lfr/lpp_waveform/lpp_waveform_genaddress.vhd +AHB_DMA/lpp_dma_pkg.vhd +AHB_DMA/lpp_dma_send_1word.vhd +AHB_DMA/lpp_dma_send_16word.vhd +AHB_DMA/lpp_dma_singleOrBurst.vhd + + diff --git a/lib/staging/LPP/JCP/general_purpose/Arbiter/RR_Arbiter_4.vhd b/lib/staging/LPP/JCP/general_purpose/Arbiter/RR_Arbiter_4.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/Arbiter/RR_Arbiter_4.vhd @@ -0,0 +1,80 @@ + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; + +ENTITY RR_Arbiter_4_LPP_JCP IS + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) + ); + +END RR_Arbiter_4_LPP_JCP; + +ARCHITECTURE beh OF RR_Arbiter_4_LPP_JCP IS + + SIGNAL out_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL grant_sel : STD_LOGIC_VECTOR(1 DOWNTO 0); + +BEGIN -- beh + + out_grant <= out_grant_s; + + out_grant_s <= "0001" WHEN grant_sel = "00" AND in_valid(0) = '1' ELSE + "0010" WHEN grant_sel = "00" AND in_valid(1) = '1' ELSE + "0100" WHEN grant_sel = "00" AND in_valid(2) = '1' ELSE + "1000" WHEN grant_sel = "00" AND in_valid(3) = '1' ELSE + "0010" WHEN grant_sel = "01" AND in_valid(1) = '1' ELSE + "0100" WHEN grant_sel = "01" AND in_valid(2) = '1' ELSE + "1000" WHEN grant_sel = "01" AND in_valid(3) = '1' ELSE + "0001" WHEN grant_sel = "01" AND in_valid(0) = '1' ELSE + "0100" WHEN grant_sel = "10" AND in_valid(2) = '1' ELSE + "1000" WHEN grant_sel = "10" AND in_valid(3) = '1' ELSE + "0001" WHEN grant_sel = "10" AND in_valid(0) = '1' ELSE + "0010" WHEN grant_sel = "10" AND in_valid(1) = '1' ELSE + "1000" WHEN grant_sel = "11" AND in_valid(3) = '1' ELSE + "0001" WHEN grant_sel = "11" AND in_valid(0) = '1' ELSE + "0010" WHEN grant_sel = "11" AND in_valid(1) = '1' ELSE + "0100" WHEN grant_sel = "11" AND in_valid(2) = '1' ELSE + "0000"; + + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + grant_sel <= "00"; + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + CASE out_grant_s IS + WHEN "0001" => grant_sel <= "01"; + WHEN "0010" => grant_sel <= "10"; + WHEN "0100" => grant_sel <= "11"; + WHEN "1000" => grant_sel <= "00"; + WHEN OTHERS => grant_sel <= grant_sel; + END CASE; + END IF; + END PROCESS; + +END beh; diff --git a/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel.vhd b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel.vhd @@ -0,0 +1,147 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY staging; +USE staging.FIFO_shared_memory_4channel_pkg_LPP_JCP.ALL; + +ENTITY FIFO_shared_memory_4channel_LPP_JCP IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + + --------------------------------------------------------------------------- + empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + + --------------------------------------------------------------------------- + full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b + full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_FIFO_shared_memory_4channel OF FIFO_shared_memory_4channel_LPP_JCP IS + + + SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0); + SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0); + + SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL re : STD_LOGIC; + SIGNAL we : STD_LOGIC; + +BEGIN + + SRAM : syncram_2p + GENERIC MAP(tech, 7, 32) + PORT MAP(clk, re, data_addr_r, rdata, + clk, we, data_addr_w, wdata); + + re <= data_mem_re(3) OR + data_mem_re(2) OR + data_mem_re(1) OR + data_mem_re(0); + + we <= data_mem_we(3) OR + data_mem_we(2) OR + data_mem_we(1) OR + data_mem_we(0); + + data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE + data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE + data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE + data_mem_addr_r(3); + + data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE + data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE + data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE + data_mem_addr_w(3); + + gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE + FIFO_shared_memory_4channel_ctrl_data: FIFO_shared_memory_4channel_ctrl_LPP_JCP + GENERIC MAP ( + offset => 32*I, + length => 32) + PORT MAP ( + clk => clk, + rstn => rstn, + run => run, + ren => data_ren(I), + wen => data_wen(I), + mem_re => data_mem_re(I), + mem_we => data_mem_we(I), + mem_addr_ren => data_mem_addr_r(I), + mem_addr_wen => data_mem_addr_w(I), + empty_almost => empty_almost(I), + empty => empty(I), + full_almost => full_almost(I), + full => full(I) + ); + END GENERATE gen_fifo_ctrl_data; + + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_ctrl.vhd b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_ctrl.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_ctrl.vhd @@ -0,0 +1,187 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY FIFO_shared_memory_4channel_ctrl_LPP_JCP IS + generic( + offset : INTEGER := 0; + length : INTEGER := 20 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + + run : IN STD_LOGIC; + + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + --------------------------------------------------------------------------- + empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b + empty : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; --occupancy is greater than MAX - 5 * 32b + full : OUT STD_LOGIC + + ); +END ENTITY; + + +ARCHITECTURE ar_FIFO_shared_memory_4channel_ctrl OF FIFO_shared_memory_4channel_ctrl_LPP_JCP IS + + SIGNAL sFull : STD_LOGIC; + SIGNAL sFull_s : STD_LOGIC; + SIGNAL sEmpty_s : STD_LOGIC; + + SIGNAL sEmpty : STD_LOGIC; + SIGNAL sREN : STD_LOGIC; + SIGNAL sWEN : STD_LOGIC; + SIGNAL sRE : STD_LOGIC; + SIGNAL sWE : STD_LOGIC; + + SIGNAL Waddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect : INTEGER RANGE 0 TO length := 0; + SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0; + SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0; + + SIGNAL space_busy : INTEGER RANGE 0 TO length := 0; + SIGNAL space_free : INTEGER RANGE 0 TO length := 0; + +BEGIN + mem_re <= sRE; + mem_we <= sWE; +--============================= +-- Read section +--============================= + sREN <= REN OR sEmpty; + sRE <= NOT sREN; + + sEmpty_s <= '1' WHEN sEmpty = '1' AND Wen = '1' ELSE + '1' WHEN sEmpty = '0' AND (Wen = '1' AND Ren = '0' AND Raddr_vect_s = Waddr_vect) ELSE + '0'; + + Raddr_vect_s <= Raddr_vect +1 WHEN Raddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Raddr_vect <= 0; + sempty <= '1'; + ELSIF(clk'EVENT AND clk = '1')then + IF run = '0' THEN + Raddr_vect <= 0; + sempty <= '1'; + ELSE + sEmpty <= sempty_s; + IF(sREN = '0' and sempty = '0')then + Raddr_vect <= Raddr_vect_s; + END IF; + END IF; + END IF; + END PROCESS; + +--============================= +-- Write section +--============================= + sWEN <= WEN OR sFull; + sWE <= NOT sWEN; + + sFull_s <= '1' WHEN Waddr_vect_s = Raddr_vect AND REN = '1' AND WEN = '0' ELSE + '1' WHEN sFull = '1' AND REN = '1' ELSE + '0'; + + Waddr_vect_s <= Waddr_vect +1 WHEN Waddr_vect < length -1 ELSE 0 ; + + PROCESS (clk, rstn) + BEGIN + IF(rstn = '0')then + Waddr_vect <= 0; + sfull <= '0'; + ELSIF(clk'EVENT AND clk = '1')THEN + IF run = '0' THEN + Waddr_vect <= 0; + sfull <= '0'; + ELSE + sfull <= sfull_s; + IF(sWEN = '0' and sfull = '0')THEN + Waddr_vect <= Waddr_vect_s; + END IF; + END IF; + END IF; + END PROCESS; + + + mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length)); + mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length)); + + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + empty_almost <= '0' WHEN space_busy > 15 ELSE '1'; + empty <= sEmpty; + + full_almost <= '0' WHEN space_free > 4 ELSE '1'; + full <= sfull; + + ----------------------------------------------------------------------------- + -- + ----------------------------------------------------------------------------- + space_busy <= length WHEN sfull = '1' ELSE + length + Waddr_vect - Raddr_vect WHEN Waddr_vect < Raddr_vect ELSE + Waddr_vect - Raddr_vect; + + space_free <= length - space_busy; + + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_headreg.vhd b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_headreg.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_headreg.vhd @@ -0,0 +1,211 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Jean-christophe PELLION +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; + +ENTITY FIFO_shared_memory_4channel_headreg_LPP_JCP IS + GENERIC( + tech : INTEGER := 0 + ); + PORT( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --------------------------------------------------------------------------- + run : IN STD_LOGIC; + --------------------------------------------------------------------------- + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- + --------------------------------------------------------------------------- + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END ENTITY; + + +ARCHITECTURE ar_FIFO_shared_memory_4channel_headreg OF FIFO_shared_memory_4channel_headreg_LPP_JCP IS + SIGNAL reg_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_ren : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_ren_reg : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL one_ren_and_notEmpty : STD_LOGIC; + SIGNAL ren_and_notEmpty : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL s_rdata_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL s_rdata_3 : STD_LOGIC_VECTOR(31 DOWNTO 0); +BEGIN + + ----------------------------------------------------------------------------- + -- DATA_REN_FIFO + ----------------------------------------------------------------------------- + i_data_ren <= s_ren; + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + s_ren_reg <= (OTHERS => '1'); + ELSIF clk'EVENT AND clk = '1' THEN + IF run = '1' THEN + s_ren_reg <= s_ren; + ELSE + s_ren_reg <= (OTHERS => '1'); + END IF; + END IF; + END PROCESS; + + s_ren(0) <= o_data_ren(0) WHEN one_ren_and_notEmpty = '1' ELSE + NOT ((NOT i_empty(0)) AND (NOT reg_full(0))); + s_ren(1) <= o_data_ren(1) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + NOT ((NOT i_empty(1)) AND (NOT reg_full(1))); + s_ren(2) <= o_data_ren(2) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + '1' WHEN s_ren(1) = '0' ELSE + NOT ((NOT i_empty(2)) AND (NOT reg_full(2))); + s_ren(3) <= o_data_ren(3) WHEN one_ren_and_notEmpty = '1' ELSE + '1' WHEN s_ren(0) = '0' ELSE + '1' WHEN s_ren(1) = '0' ELSE + '1' WHEN s_ren(2) = '0' ELSE + NOT ((NOT i_empty(3)) AND (NOT reg_full(3))); + ----------------------------------------------------------------------------- + all_ren : FOR I IN 3 DOWNTO 0 GENERATE + ren_and_notEmpty(I) <= (NOT o_data_ren(I)) AND (NOT i_empty(I)); + END GENERATE all_ren; + one_ren_and_notEmpty <= '0' WHEN ren_and_notEmpty = "0000" ELSE '1'; + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + o_rdata_0 <= i_rdata WHEN s_ren_reg(0) = '0' AND s_ren(0) = '0' ELSE s_rdata_0; + o_rdata_1 <= i_rdata WHEN s_ren_reg(1) = '0' AND s_ren(1) = '0' ELSE s_rdata_1; + o_rdata_2 <= i_rdata WHEN s_ren_reg(2) = '0' AND s_ren(2) = '0' ELSE s_rdata_2; + o_rdata_3 <= i_rdata WHEN s_ren_reg(3) = '0' AND s_ren(3) = '0' ELSE s_rdata_3; + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + s_rdata_0 <= (OTHERS => '0'); + s_rdata_1 <= (OTHERS => '0'); + s_rdata_2 <= (OTHERS => '0'); + s_rdata_3 <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN + IF run = '1' THEN + IF s_ren_reg(0) = '0' THEN s_rdata_0 <= i_rdata; END IF; + IF s_ren_reg(1) = '0' THEN s_rdata_1 <= i_rdata; END IF; + IF s_ren_reg(2) = '0' THEN s_rdata_2 <= i_rdata; END IF; + IF s_ren_reg(3) = '0' THEN s_rdata_3 <= i_rdata; END IF; + ELSE + s_rdata_0 <= (OTHERS => '0'); + s_rdata_1 <= (OTHERS => '0'); + s_rdata_2 <= (OTHERS => '0'); + s_rdata_3 <= (OTHERS => '0'); + END IF; + END IF; + END PROCESS; + + all_reg_full : FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + reg_full(I) <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN +-- IF s_ren_reg(I) = '0' THEN + IF run = '1' THEN + IF s_ren(I) = '0' THEN + reg_full(I) <= '1'; + ELSIF o_data_ren(I) = '0' THEN + reg_full(I) <= '0'; + END IF; + ELSE + reg_full(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_reg_full; + + ----------------------------------------------------------------------------- + -- EMPTY + ----------------------------------------------------------------------------- + o_empty <= NOT reg_full; + + ----------------------------------------------------------------------------- + -- EMPTY_ALMOST + ----------------------------------------------------------------------------- + o_empty_almost <= s_empty_almost; + + all_empty_almost: FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + s_empty_almost(I) <= '1'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + IF run = '1' THEN + IF s_ren(I) = '0' THEN + s_empty_almost(I) <= i_empty_almost(I); + ELSIF o_data_ren(I) = '0' THEN + s_empty_almost(I) <= '1'; + ELSE + IF i_empty_almost(I) = '0' THEN + s_empty_almost(I) <= '0'; + END IF; + END IF; + ELSE + s_empty_almost(I) <= '1'; + END IF; + END IF; + END PROCESS; + END GENERATE all_empty_almost; + +END ARCHITECTURE; + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_pkg.vhd b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_pkg.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/FIFO/FIFO_shared_memory_4channel_pkg.vhd @@ -0,0 +1,71 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; + +PACKAGE FIFO_shared_memory_4channel_pkg_LPP_JCP IS + + TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0); + + COMPONENT FIFO_shared_memory_4channel_headreg_LPP_JCP + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT FIFO_shared_memory_4channel_ctrl_LPP_JCP + GENERIC ( + offset : INTEGER; + length : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + ren : IN STD_LOGIC; + wen : IN STD_LOGIC; + mem_re : OUT STD_LOGIC; + mem_we : OUT STD_LOGIC; + mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0); + mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0); + empty_almost : OUT STD_LOGIC; + empty : OUT STD_LOGIC; + full_almost : OUT STD_LOGIC; + full : OUT STD_LOGIC); + END COMPONENT; + + +END FIFO_shared_memory_4channel_pkg_LPP_JCP; diff --git a/lib/staging/LPP/JCP/general_purpose/general_purpose.vhd b/lib/staging/LPP/JCP/general_purpose/general_purpose.vhd new file mode 100644 --- /dev/null +++ b/lib/staging/LPP/JCP/general_purpose/general_purpose.vhd @@ -0,0 +1,250 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- + + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +PACKAGE general_purpose_LPP_JCP IS + + ----------------------------------------------------------------------------- + -- SYNCHRONIZER + ----------------------------------------------------------------------------- + COMPONENT SYNC_FF_LPP_JCP + GENERIC ( + NB_FF_OF_SYNC : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + A : IN STD_LOGIC; + A_sync : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT SYNC_VALID_BIT_LPP_JCP + GENERIC ( + NB_FF_OF_SYNC : INTEGER); + PORT ( + clk_in : IN STD_LOGIC; + clk_out : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- EDGE DETECTION + ----------------------------------------------------------------------------- + COMPONENT lpp_edge_detection_LPP_JCP + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + + COMPONENT lpp_edge_to_level_LPP_JCP + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sin : IN STD_LOGIC; + sout : OUT STD_LOGIC); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- COMPUTING + ----------------------------------------------------------------------------- + COMPONENT ALU_LPP_JCP + GENERIC ( + Arith_en : INTEGER; + Logic_en : INTEGER; + Input_SZ_1 : INTEGER; + Input_SZ_2 : INTEGER; + COMP_EN : INTEGER); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT MAC_LPP_JCP + GENERIC ( + Input_SZ_A : INTEGER; + Input_SZ_B : INTEGER; + COMP_EN : INTEGER); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr_MAC : IN STD_LOGIC; + MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- COMMON + ----------------------------------------------------------------------------- + COMPONENT Multiplier_LPP_JCP + GENERIC ( + Input_SZ_A : INTEGER; + Input_SZ_B : INTEGER); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + mult : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT Adder_LPP_JCP + GENERIC ( + Input_SZ_A : INTEGER; + Input_SZ_B : INTEGER); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + load : IN STD_LOGIC; + add : IN STD_LOGIC; + OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT TwoComplementer_LPP_JCP + GENERIC ( + Input_SZ : INTEGER); + PORT ( + clk : IN STD_LOGIC; + reset : IN STD_LOGIC; + clr : IN STD_LOGIC; + TwoComp : IN STD_LOGIC; + OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0); + RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT Register_LPP_JCP + GENERIC ( + size : INTEGER); + PORT ( + reset : IN STD_LOGIC; + clk : IN STD_LOGIC; + D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0); + Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT MUX_LPP_JCP + GENERIC ( + Input_SZ_A : INTEGER; + Input_SZ_B : INTEGER); + PORT ( + sel : IN STD_LOGIC; + INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0); + OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0); + OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)); + END COMPONENT; + + COMPONENT MUX2_LPP_JCP + GENERIC ( + Input_SZ : integer); + PORT ( + sel : in std_logic; + RES1 : in std_logic_vector(Input_SZ-1 downto 0); + RES2 : in std_logic_vector(Input_SZ-1 downto 0); + RES : out std_logic_vector(Input_SZ-1 downto 0)); + END COMPONENT; + + TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC; + TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC; + + COMPONENT MUXN_LPP_JCP + GENERIC ( + Input_SZ : INTEGER; + NbStage : INTEGER); + PORT ( + sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0); + INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1, Input_SZ-1 DOWNTO 0); + RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- ARBITER + ----------------------------------------------------------------------------- + COMPONENT RR_Arbiter_4_LPP_JCP + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); + END COMPONENT; + + ----------------------------------------------------------------------------- + -- FIFO + ----------------------------------------------------------------------------- + COMPONENT FIFO_shared_memory_4channel_LPP_JCP + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + + COMPONENT FIFO_shared_memory_4channel_headreg_LPP_JCP + GENERIC ( + tech : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + run : IN STD_LOGIC; + o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + +END; diff --git a/lib/staging/LPP/JCP/general_purpose/vhdlsyn.txt b/lib/staging/LPP/JCP/general_purpose/vhdlsyn.txt --- a/lib/staging/LPP/JCP/general_purpose/vhdlsyn.txt +++ b/lib/staging/LPP/JCP/general_purpose/vhdlsyn.txt @@ -13,3 +13,8 @@ Common/Register.vhd Common/MUX.vhd Common/MUX2.vhd Common/MUXN.vhd +Arbiter/RR_Arbiter_4.vhd +FIFO/FIFO_shared_memory_4channel_pkg.vhd +FIFO/FIFO_shared_memory_4channel.vhd +FIFO/FIFO_shared_memory_4channel_ctrl.vhd +FIFO/FIFO_shared_memory_4channel_headreg.vhd