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Corrections des vecteurs entrant dans la FFT.
pellion -
r553:f7426aef3b86 (MINI-LFR) WFP_MS-0-1-65 JC
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@@ -522,7 +522,7 BEGIN -- beh
522 pirq_ms => 6,
522 pirq_ms => 6,
523 pirq_wfp => 14,
523 pirq_wfp => 14,
524 hindex => 2,
524 hindex => 2,
525 top_lfr_version => X"000140") -- aa.bb.cc version
525 top_lfr_version => X"000141") -- aa.bb.cc version
526 PORT MAP (
526 PORT MAP (
527 clk => clk_25,
527 clk => clk_25,
528 rstn => LFR_rstn,
528 rstn => LFR_rstn,
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@@ -179,9 +179,24 add wave -noupdate -expand -group TOP_IN
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
179 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
180 add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
181 add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid
182 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_pong
183 add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_ready
184 add wave -noupdate -expand -group FFT -expand -group IN -format Analog-Step -height 74 -max 4096.0 -min -1800.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_data
185 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_load
186 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_read
187 add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_valid
188 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_im
189 add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_re
190 add wave -noupdate -expand -group FFT -expand -group OUT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_valid
191 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid
192 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_delay
193 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_r
194 add wave -noupdate /testbench/lpp_lfr_ms_1/state_fsm_load_FFT
195 add wave -noupdate -expand /testbench/lpp_lfr_ms_1/sample_f0_A_ren
196 add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_B_ren
182 TreeUpdate [SetDefaultTree]
197 TreeUpdate [SetDefaultTree]
183 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
198 WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10490580000 ps} 0} {{Cursor 10} {6346220000 ps} 0}
184 quietly wave cursor active 6
199 quietly wave cursor active 5
185 configure wave -namecolwidth 573
200 configure wave -namecolwidth 573
186 configure wave -valuecolwidth 108
201 configure wave -valuecolwidth 108
187 configure wave -justifyvalue left
202 configure wave -justifyvalue left
@@ -196,4 +211,4 configure wave -griddelta 40
196 configure wave -timeline 0
211 configure wave -timeline 0
197 configure wave -timelineunits ns
212 configure wave -timelineunits ns
198 update
213 update
199 WaveRestoreZoom {0 ps} {14085099 ns}
214 WaveRestoreZoom {10489250172 ps} {10491702980 ps}
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@@ -136,9 +136,9 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 -- FSM LOAD FFT
137 -- FSM LOAD FFT
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
139 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2);
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
140 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
141 -- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
141 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
142 SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
143 SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
144
144
@@ -146,6 +146,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
146 SIGNAL sample_load : STD_LOGIC;
146 SIGNAL sample_load : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
147 SIGNAL sample_valid : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
148 SIGNAL sample_valid_r : STD_LOGIC;
149 SIGNAL sample_valid_delay : STD_LOGIC;
149 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
150
151
151
152
@@ -157,6 +158,7 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
157 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
158 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
159 SIGNAL fft_data_valid : STD_LOGIC;
160 SIGNAL fft_data_valid : STD_LOGIC;
161 SIGNAL fft_data_valid_pre : STD_LOGIC;
160 SIGNAL fft_ready : STD_LOGIC;
162 SIGNAL fft_ready : STD_LOGIC;
161 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
162 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -597,40 +599,45 BEGIN
597 --sample_valid <= '0';
599 --sample_valid <= '0';
598 sample_ren_s <= (OTHERS => '1');
600 sample_ren_s <= (OTHERS => '1');
599 IF sample_full = "11111" AND sample_load = '1' THEN
601 IF sample_full = "11111" AND sample_load = '1' THEN
602 sample_ren_s <= "11111";
600 state_fsm_load_FFT <= FIFO_1;
603 state_fsm_load_FFT <= FIFO_1;
601 status_MS_input <= status_channel;
604 status_MS_input <= status_channel;
602 select_fifo <= "000";
605 select_fifo <= "000";
603 END IF;
606 END IF;
604
607
605 WHEN FIFO_1 =>
608 WHEN FIFO_1 =>
606 sample_ren_s <= "1111" & NOT(sample_load);
609 sample_ren_s <= "1111" & NOT(sample_load);
607 IF sample_empty(0) = '1' THEN
610 IF sample_empty(0) = '1' THEN
608 sample_ren_s <= (OTHERS => '1');
611 sample_ren_s <= "11111";
609 state_fsm_load_FFT <= FIFO_2;
612 state_fsm_load_FFT <= WAIT_STATE;
613 next_state_fsm_load_FFT <= FIFO_2;
610 select_fifo <= "001";
614 select_fifo <= "001";
611 END IF;
615 END IF;
612
616
613 WHEN FIFO_2 =>
617 WHEN FIFO_2 =>
614 sample_ren_s <= "111" & NOT(sample_load) & '1';
618 sample_ren_s <= "111" & NOT(sample_load) & '1';
615 IF sample_empty(1) = '1' THEN
619 IF sample_empty(1) = '1' THEN
616 sample_ren_s <= (OTHERS => '1');
620 sample_ren_s <= "11111";
617 state_fsm_load_FFT <= FIFO_3;
621 state_fsm_load_FFT <= WAIT_STATE;
622 next_state_fsm_load_FFT <= FIFO_3;
618 select_fifo <= "010";
623 select_fifo <= "010";
619 END IF;
624 END IF;
620
625
621 WHEN FIFO_3 =>
626 WHEN FIFO_3 =>
622 sample_ren_s <= "11" & NOT(sample_load) & "11";
627 sample_ren_s <= "11" & NOT(sample_load) & "11";
623 IF sample_empty(2) = '1' THEN
628 IF sample_empty(2) = '1' THEN
624 sample_ren_s <= (OTHERS => '1');
629 sample_ren_s <= "11111";
625 state_fsm_load_FFT <= FIFO_4;
630 state_fsm_load_FFT <= WAIT_STATE;
631 next_state_fsm_load_FFT <= FIFO_4;
626 select_fifo <= "011";
632 select_fifo <= "011";
627 END IF;
633 END IF;
628
634
629 WHEN FIFO_4 =>
635 WHEN FIFO_4 =>
630 sample_ren_s <= '1' & NOT(sample_load) & "111";
636 sample_ren_s <= '1' & NOT(sample_load) & "111";
631 IF sample_empty(3) = '1' THEN
637 IF sample_empty(3) = '1' THEN
632 sample_ren_s <= (OTHERS => '1');
638 sample_ren_s <= "11111";
633 state_fsm_load_FFT <= FIFO_5;
639 state_fsm_load_FFT <= WAIT_STATE;
640 next_state_fsm_load_FFT <= FIFO_5;
634 select_fifo <= "100";
641 select_fifo <= "100";
635 END IF;
642 END IF;
636
643
@@ -641,12 +648,34 BEGIN
641 state_fsm_load_FFT <= IDLE;
648 state_fsm_load_FFT <= IDLE;
642 select_fifo <= "000";
649 select_fifo <= "000";
643 END IF;
650 END IF;
651
652 WHEN WAIT_STATE =>
653 sample_ren_s <= (OTHERS => '1');
654 IF sample_load = '1' THEN
655 state_fsm_load_FFT <= WAIT_STATE_2 ;
656 END IF;
657
658 WHEN WAIT_STATE_2 =>
659 sample_ren_s <= (OTHERS => '1');
660 IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN
661 state_fsm_load_FFT <= next_state_fsm_load_FFT;
662 END IF;
663
644 WHEN OTHERS => NULL;
664 WHEN OTHERS => NULL;
645 END CASE;
665 END CASE;
646 END IF;
666 END IF;
647 END PROCESS;
667 END PROCESS;
648
668
649 PROCESS (clk, rstn)
669 PROCESS (clk, rstn)
670 BEGIN -- PROCESS
671 IF rstn = '0' THEN -- asynchronous reset (active low)
672 fft_data_valid_pre <= '0';
673 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
674 fft_data_valid_pre <= fft_data_valid;
675 END IF;
676 END PROCESS;
677
678 PROCESS (clk, rstn)
650 BEGIN
679 BEGIN
651 IF rstn = '0' THEN
680 IF rstn = '0' THEN
652 sample_valid_r <= '0';
681 sample_valid_r <= '0';
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