# HG changeset patch # User pellion # Date 2015-03-11 15:51:37 # Node ID f7426aef3b86c6a151eff6e46b77ab73bd0bfef9 # Parent c10ebde1bf882a8a9cb4c5ba863cd51fb579a9d8 Corrections des vecteurs entrant dans la FFT. diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -522,7 +522,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000140") -- aa.bb.cc version + top_lfr_version => X"000141") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => LFR_rstn, diff --git a/designs/Validation_MS_auto/wave.do b/designs/Validation_MS_auto/wave.do --- a/designs/Validation_MS_auto/wave.do +++ b/designs/Validation_MS_auto/wave.do @@ -179,9 +179,24 @@ add wave -noupdate -expand -group TOP_IN add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_buffer_new add wave -noupdate -expand -group TOP_IN_OUT -radix decimal /testbench/lpp_lfr_ms_1/dma_fifo_data add wave -noupdate -expand -group TOP_IN_OUT /testbench/lpp_lfr_ms_1/dma_fifo_burst_valid +add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_pong +add wave -noupdate -expand -group FFT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_ready +add wave -noupdate -expand -group FFT -expand -group IN -format Analog-Step -height 74 -max 4096.0 -min -1800.0 -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_data +add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_load +add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_read +add wave -noupdate -expand -group FFT -expand -group IN /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/sample_valid +add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_im +add wave -noupdate -expand -group FFT -expand -group OUT -radix decimal /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_re +add wave -noupdate -expand -group FFT -expand -group OUT /testbench/lpp_lfr_ms_1/lpp_lfr_ms_FFT_1/fft_data_valid +add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid +add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_delay +add wave -noupdate /testbench/lpp_lfr_ms_1/sample_valid_r +add wave -noupdate /testbench/lpp_lfr_ms_1/state_fsm_load_FFT +add wave -noupdate -expand /testbench/lpp_lfr_ms_1/sample_f0_A_ren +add wave -noupdate /testbench/lpp_lfr_ms_1/sample_f0_B_ren TreeUpdate [SetDefaultTree] -WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10572740000 ps} 0} {{Cursor 10} {6346220000 ps} 0} -quietly wave cursor active 6 +WaveRestoreCursors {WDATA_1 {10541340000 ps} 1} {WDATA_2 {10541500000 ps} 1} {WDATA_8 {10542460000 ps} 1} {WDATA_16 {10543740000 ps} 1} {{Cursor 9} {10490580000 ps} 0} {{Cursor 10} {6346220000 ps} 0} +quietly wave cursor active 5 configure wave -namecolwidth 573 configure wave -valuecolwidth 108 configure wave -justifyvalue left @@ -196,4 +211,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {0 ps} {14085099 ns} +WaveRestoreZoom {10489250172 ps} {10491702980 ps} diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd --- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd @@ -136,9 +136,9 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS ----------------------------------------------------------------------------- -- FSM LOAD FFT ----------------------------------------------------------------------------- - TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5); + TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5, WAIT_STATE, WAIT_STATE_2); SIGNAL state_fsm_load_FFT : fsm_load_FFT; --- SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; + SIGNAL next_state_fsm_load_FFT : fsm_load_FFT; SIGNAL select_fifo : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0); @@ -146,6 +146,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL sample_load : STD_LOGIC; SIGNAL sample_valid : STD_LOGIC; SIGNAL sample_valid_r : STD_LOGIC; + SIGNAL sample_valid_delay : STD_LOGIC; SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0); @@ -157,6 +158,7 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL fft_data_valid : STD_LOGIC; + SIGNAL fft_data_valid_pre : STD_LOGIC; SIGNAL fft_ready : STD_LOGIC; ----------------------------------------------------------------------------- -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0); @@ -597,40 +599,45 @@ BEGIN --sample_valid <= '0'; sample_ren_s <= (OTHERS => '1'); IF sample_full = "11111" AND sample_load = '1' THEN + sample_ren_s <= "11111"; state_fsm_load_FFT <= FIFO_1; status_MS_input <= status_channel; - select_fifo <= "000"; + select_fifo <= "000"; END IF; WHEN FIFO_1 => sample_ren_s <= "1111" & NOT(sample_load); IF sample_empty(0) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_2; + sample_ren_s <= "11111"; + state_fsm_load_FFT <= WAIT_STATE; + next_state_fsm_load_FFT <= FIFO_2; select_fifo <= "001"; END IF; WHEN FIFO_2 => sample_ren_s <= "111" & NOT(sample_load) & '1'; IF sample_empty(1) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_3; + sample_ren_s <= "11111"; + state_fsm_load_FFT <= WAIT_STATE; + next_state_fsm_load_FFT <= FIFO_3; select_fifo <= "010"; END IF; WHEN FIFO_3 => sample_ren_s <= "11" & NOT(sample_load) & "11"; IF sample_empty(2) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_4; + sample_ren_s <= "11111"; + state_fsm_load_FFT <= WAIT_STATE; + next_state_fsm_load_FFT <= FIFO_4; select_fifo <= "011"; END IF; WHEN FIFO_4 => sample_ren_s <= '1' & NOT(sample_load) & "111"; IF sample_empty(3) = '1' THEN - sample_ren_s <= (OTHERS => '1'); - state_fsm_load_FFT <= FIFO_5; + sample_ren_s <= "11111"; + state_fsm_load_FFT <= WAIT_STATE; + next_state_fsm_load_FFT <= FIFO_5; select_fifo <= "100"; END IF; @@ -641,12 +648,34 @@ BEGIN state_fsm_load_FFT <= IDLE; select_fifo <= "000"; END IF; + + WHEN WAIT_STATE => + sample_ren_s <= (OTHERS => '1'); + IF sample_load = '1' THEN + state_fsm_load_FFT <= WAIT_STATE_2 ; + END IF; + + WHEN WAIT_STATE_2 => + sample_ren_s <= (OTHERS => '1'); + IF fft_data_valid = '0' AND fft_data_valid_pre = '1' THEN + state_fsm_load_FFT <= next_state_fsm_load_FFT; + END IF; + WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + fft_data_valid_pre <= '0'; + ELSIF clk'event AND clk = '1' THEN -- rising clock edge + fft_data_valid_pre <= fft_data_valid; + END IF; + END PROCESS; + + PROCESS (clk, rstn) BEGIN IF rstn = '0' THEN sample_valid_r <= '0';