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custom dma : update transition's condition between FSM state "ARBITER" and "CTRL"
pellion -
r580:f4e8c3120b82 simu_with_Leon3
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
47
49
48 --library proasic3l;
50 --library proasic3l;
49 --use proasic3l.all;
51 --use proasic3l.all;
50
52
51 ENTITY LFR_EQM IS
53 ENTITY LFR_EQM IS
52 --GENERIC (
54 GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
55 Mem_use : INTEGER := use_RAM;
56 USE_BOOTLOADER : INTEGER := 0
57 );
54
58
55 PORT (
59 PORT (
56 clk50MHz : IN STD_ULOGIC;
60 clk50MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
61 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
62 reset : IN STD_ULOGIC;
59
63
60 -- TAG --------------------------------------------------------------------
64 -- TAG --------------------------------------------------------------------
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
65 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
66 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 -- UART APB ---------------------------------------------------------------
67 -- UART APB ---------------------------------------------------------------
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
68 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
69 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
70 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
71 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
73
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
74 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
75 nSRAM_E1 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
76 nSRAM_E2 : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
77 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
78 nSRAM_W : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
79 nSRAM_G : OUT STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
80 nSRAM_BUSY : IN STD_LOGIC; -- new
77 -- SPW --------------------------------------------------------------------
81 -- SPW --------------------------------------------------------------------
78 spw1_en : OUT STD_LOGIC; -- new
82 spw1_en : OUT STD_LOGIC; -- new
79 spw1_din : IN STD_LOGIC;
83 spw1_din : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
84 spw1_sin : IN STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
85 spw1_dout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
86 spw1_sout : OUT STD_LOGIC;
83 spw2_en : OUT STD_LOGIC; -- new
87 spw2_en : OUT STD_LOGIC; -- new
84 spw2_din : IN STD_LOGIC;
88 spw2_din : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
89 spw2_sin : IN STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
90 spw2_dout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
91 spw2_sout : OUT STD_LOGIC;
88 -- ADC --------------------------------------------------------------------
92 -- ADC --------------------------------------------------------------------
89 bias_fail_sw : OUT STD_LOGIC;
93 bias_fail_sw : OUT STD_LOGIC;
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 ADC_smpclk : OUT STD_LOGIC;
95 ADC_smpclk : OUT STD_LOGIC;
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 -- DAC --------------------------------------------------------------------
97 -- DAC --------------------------------------------------------------------
94 DAC_SDO : OUT STD_LOGIC;
98 DAC_SDO : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
99 DAC_SCK : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
100 DAC_SYNC : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
101 DAC_CAL_EN : OUT STD_LOGIC;
98 -- HK ---------------------------------------------------------------------
102 -- HK ---------------------------------------------------------------------
99 HK_smpclk : OUT STD_LOGIC;
103 HK_smpclk : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
104 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
105 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ---------------------------------------------------------------------------
106 ---------------------------------------------------------------------------
103 TAG8 : OUT STD_LOGIC
107 TAG8 : OUT STD_LOGIC
104 );
108 );
105
109
106 END LFR_EQM;
110 END LFR_EQM;
107
111
108
112
109 ARCHITECTURE beh OF LFR_EQM IS
113 ARCHITECTURE beh OF LFR_EQM IS
110
114
111 SIGNAL clk_25 : STD_LOGIC := '0';
115 SIGNAL clk_25 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
116 SIGNAL clk_24 : STD_LOGIC := '0';
113 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
118 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116
120
117 -- CONSTANTS
121 -- CONSTANTS
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
122 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
123 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
124 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
125 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122
126
123 SIGNAL apbi_ext : apb_slv_in_type;
127 SIGNAL apbi_ext : apb_slv_in_type;
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
128 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
129 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
130 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
131 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
132 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129
133
130 -- Spacewire signals
134 -- Spacewire signals
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
136 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
137 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
138 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
139 SIGNAL spw_rxclkn : STD_ULOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
140 SIGNAL spw_clk : STD_LOGIC;
137 SIGNAL swni : grspw_in_type;
141 SIGNAL swni : grspw_in_type;
138 SIGNAL swno : grspw_out_type;
142 SIGNAL swno : grspw_out_type;
139
143
140 --GPIO
144 --GPIO
141 SIGNAL gpioi : gpio_in_type;
145 SIGNAL gpioi : gpio_in_type;
142 SIGNAL gpioo : gpio_out_type;
146 SIGNAL gpioo : gpio_out_type;
143
147
144 -- AD Converter ADS7886
148 -- AD Converter ADS7886
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
149 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
150 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 SIGNAL sample_val : STD_LOGIC;
151 SIGNAL sample_val : STD_LOGIC;
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
152 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149
153
150 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152
156
153 -----------------------------------------------------------------------------
157 -----------------------------------------------------------------------------
154 SIGNAL rstn_25 : STD_LOGIC;
158 SIGNAL rstn_25 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
159 SIGNAL rstn_24 : STD_LOGIC;
156
160
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
161 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
162 SIGNAL LFR_rstn : STD_LOGIC;
159
163
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
164 SIGNAL ADC_smpclk_s : STD_LOGIC;
161
165
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
166 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163
167
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
168 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
169 SIGNAL clk_25_int : STD_LOGIC := '0';
166
170
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
171 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
172
169 BEGIN -- beh
173 BEGIN -- beh
170
174
171 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
172 -- CLK
176 -- CLK
173 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
178 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
179 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176
180
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
181 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 clk50MHz_int <= clk50MHz;
182 clk50MHz_int <= clk50MHz;
179
183
180 PROCESS(clk50MHz_int)
184 PROCESS(clk50MHz_int)
181 BEGIN
185 BEGIN
182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
186 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 --clk_25_int <= NOT clk_25_int;
187 --clk_25_int <= NOT clk_25_int;
184 clk_25 <= NOT clk_25;
188 clk_25 <= NOT clk_25;
185 END IF;
189 END IF;
186 END PROCESS;
190 END PROCESS;
187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
191 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188
192
189 PROCESS(clk49_152MHz)
193 PROCESS(clk49_152MHz)
190 BEGIN
194 BEGIN
191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
195 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 clk_24 <= NOT clk_24;
196 clk_24 <= NOT clk_24;
193 END IF;
197 END IF;
194 END PROCESS;
198 END PROCESS;
195
199
196 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
197 --
201 --
198 leon3_soc_1 : leon3_soc
202 leon3_soc_1 : leon3_soc
199 GENERIC MAP (
203 GENERIC MAP (
200 fabtech => apa3l,
204 fabtech => apa3l,
201 memtech => apa3l,
205 memtech => apa3l,
202 padtech => inferred,
206 padtech => inferred,
203 clktech => inferred,
207 clktech => inferred,
204 disas => 0,
208 disas => 0,
205 dbguart => 0,
209 dbguart => 0,
206 pclow => 2,
210 pclow => 2,
207 clk_freq => 25000,
211 clk_freq => 25000,
208 IS_RADHARD => 0,
212 IS_RADHARD => 0,
209 NB_CPU => 1,
213 NB_CPU => 1,
210 ENABLE_FPU => 1,
214 ENABLE_FPU => 1,
211 FPU_NETLIST => 0,
215 FPU_NETLIST => 0,
212 ENABLE_DSU => 1,
216 ENABLE_DSU => 1,
213 ENABLE_AHB_UART => 1,
217 ENABLE_AHB_UART => 1,
214 ENABLE_APB_UART => 1,
218 ENABLE_APB_UART => 1,
215 ENABLE_IRQMP => 1,
219 ENABLE_IRQMP => 1,
216 ENABLE_GPT => 1,
220 ENABLE_GPT => 1,
217 NB_AHB_MASTER => NB_AHB_MASTER,
221 NB_AHB_MASTER => NB_AHB_MASTER,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
222 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
223 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 19,
224 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 1,
225 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '0',
226 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
227 SRBANKSZ => 8)
224 PORT MAP (
228 PORT MAP (
225 clk => clk_25,
229 clk => clk_25,
226 reset => rstn_25,
230 reset => rstn_25,
227 errorn => OPEN,
231 errorn => OPEN,
228
232
229 ahbrxd => TAG1,
233 ahbrxd => TAG1,
230 ahbtxd => TAG3,
234 ahbtxd => TAG3,
231 urxd1 => TAG2,
235 urxd1 => TAG2,
232 utxd1 => TAG4,
236 utxd1 => TAG4,
233
237
234 address => address,
238 address => address,
235 data => data,
239 data => data,
236 nSRAM_BE0 => OPEN,
240 nSRAM_BE0 => OPEN,
237 nSRAM_BE1 => OPEN,
241 nSRAM_BE1 => OPEN,
238 nSRAM_BE2 => OPEN,
242 nSRAM_BE2 => OPEN,
239 nSRAM_BE3 => OPEN,
243 nSRAM_BE3 => OPEN,
240 nSRAM_WE => nSRAM_W,
244 nSRAM_WE => nSRAM_W,
241 nSRAM_CE => nSRAM_CE,
245 nSRAM_CE => nSRAM_CE,
242 nSRAM_OE => nSRAM_G,
246 nSRAM_OE => nSRAM_G,
243 nSRAM_READY => nSRAM_BUSY,
247 nSRAM_READY => nSRAM_BUSY,
244 SRAM_MBE => nSRAM_MBE,
248 SRAM_MBE => nSRAM_MBE,
245
249
246 apbi_ext => apbi_ext,
250 apbi_ext => apbi_ext,
247 apbo_ext => apbo_ext,
251 apbo_ext => apbo_ext,
248 ahbi_s_ext => ahbi_s_ext,
252 ahbi_s_ext => ahbi_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
253 ahbo_s_ext => ahbo_s_ext,
250 ahbi_m_ext => ahbi_m_ext,
254 ahbi_m_ext => ahbi_m_ext,
251 ahbo_m_ext => ahbo_m_ext);
255 ahbo_m_ext => ahbo_m_ext);
252
256
253
257
254 nSRAM_E1 <= nSRAM_CE(0);
258 nSRAM_E1 <= nSRAM_CE(0);
255 nSRAM_E2 <= nSRAM_CE(1);
259 nSRAM_E2 <= nSRAM_CE(1);
256
260
257 -------------------------------------------------------------------------------
261 -------------------------------------------------------------------------------
258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
262 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 -------------------------------------------------------------------------------
263 -------------------------------------------------------------------------------
260 apb_lfr_management_1 : apb_lfr_management
264 apb_lfr_management_1 : apb_lfr_management
261 GENERIC MAP (
265 GENERIC MAP (
262 tech => apa3l,
266 tech => apa3l,
263 pindex => 6,
267 pindex => 6,
264 paddr => 6,
268 paddr => 6,
265 pmask => 16#fff#,
269 pmask => 16#fff#,
266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
270 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
271 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 PORT MAP (
272 PORT MAP (
269 clk25MHz => clk_25,
273 clk25MHz => clk_25,
270 resetn_25MHz => rstn_25, -- TODO
274 resetn_25MHz => rstn_25, -- TODO
271 --clk24_576MHz => clk_24, -- 49.152MHz/2
275 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 --resetn_24_576MHz => rstn_24, -- TODO
276 --resetn_24_576MHz => rstn_24, -- TODO
273
277
274 grspw_tick => swno.tickout,
278 grspw_tick => swno.tickout,
275 apbi => apbi_ext,
279 apbi => apbi_ext,
276 apbo => apbo_ext(6),
280 apbo => apbo_ext(6),
277
281
278 HK_sample => sample_s(8),
282 HK_sample => sample_s(8),
279 HK_val => sample_val,
283 HK_val => sample_val,
280 HK_sel => HK_SEL,
284 HK_sel => HK_SEL,
281
285
282 DAC_SDO => DAC_SDO,
286 DAC_SDO => DAC_SDO,
283 DAC_SCK => DAC_SCK,
287 DAC_SCK => DAC_SCK,
284 DAC_SYNC => DAC_SYNC,
288 DAC_SYNC => DAC_SYNC,
285 DAC_CAL_EN => DAC_CAL_EN,
289 DAC_CAL_EN => DAC_CAL_EN,
286
290
287 coarse_time => coarse_time,
291 coarse_time => coarse_time,
288 fine_time => fine_time,
292 fine_time => fine_time,
289 LFR_soft_rstn => LFR_soft_rstn
293 LFR_soft_rstn => LFR_soft_rstn
290 );
294 );
291
295
292 -----------------------------------------------------------------------
296 -----------------------------------------------------------------------
293 --- SpaceWire --------------------------------------------------------
297 --- SpaceWire --------------------------------------------------------
294 -----------------------------------------------------------------------
298 -----------------------------------------------------------------------
295
299
296 ------------------------------------------------------------------------------
300 ------------------------------------------------------------------------------
297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
301 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 ------------------------------------------------------------------------------
302 ------------------------------------------------------------------------------
299 spw1_en <= '1';
303 spw1_en <= '1';
300 spw2_en <= '1';
304 spw2_en <= '1';
301 ------------------------------------------------------------------------------
305 ------------------------------------------------------------------------------
302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
306 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 ------------------------------------------------------------------------------
307 ------------------------------------------------------------------------------
304
308
305 --spw_clk <= clk50MHz;
309 --spw_clk <= clk50MHz;
306 --spw_rxtxclk <= spw_clk;
310 --spw_rxtxclk <= spw_clk;
307 --spw_rxclkn <= NOT spw_rxtxclk;
311 --spw_rxclkn <= NOT spw_rxtxclk;
308
312
309 -- PADS for SPW1
313 -- PADS for SPW1
310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
314 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 PORT MAP (spw1_din, dtmp(0));
315 PORT MAP (spw1_din, dtmp(0));
312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
316 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 PORT MAP (spw1_sin, stmp(0));
317 PORT MAP (spw1_sin, stmp(0));
314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
318 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 PORT MAP (spw1_dout, swno.d(0));
319 PORT MAP (spw1_dout, swno.d(0));
316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
320 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 PORT MAP (spw1_sout, swno.s(0));
321 PORT MAP (spw1_sout, swno.s(0));
318 -- PADS FOR SPW2
322 -- PADS FOR SPW2
319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
323 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 PORT MAP (spw2_din, dtmp(1));
324 PORT MAP (spw2_din, dtmp(1));
321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
325 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 PORT MAP (spw2_sin, stmp(1));
326 PORT MAP (spw2_sin, stmp(1));
323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
327 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 PORT MAP (spw2_dout, swno.d(1));
328 PORT MAP (spw2_dout, swno.d(1));
325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
329 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 PORT MAP (spw2_sout, swno.s(1));
330 PORT MAP (spw2_sout, swno.s(1));
327
331
328 -- GRSPW PHY
332 -- GRSPW PHY
329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
333 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
334 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 spw_phy0 : grspw_phy
335 spw_phy0 : grspw_phy
332 GENERIC MAP(
336 GENERIC MAP(
333 tech => apa3l,
337 tech => apa3l,
334 rxclkbuftype => 1,
338 rxclkbuftype => 1,
335 scantest => 0)
339 scantest => 0)
336 PORT MAP(
340 PORT MAP(
337 rxrst => swno.rxrst,
341 rxrst => swno.rxrst,
338 di => dtmp(j),
342 di => dtmp(j),
339 si => stmp(j),
343 si => stmp(j),
340 rxclko => spw_rxclk(j),
344 rxclko => spw_rxclk(j),
341 do => swni.d(j),
345 do => swni.d(j),
342 ndo => swni.nd(j*5+4 DOWNTO j*5),
346 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
347 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 END GENERATE spw_inputloop;
348 END GENERATE spw_inputloop;
345
349
346 -- SPW core
350 -- SPW core
347 sw0 : grspwm GENERIC MAP(
351 sw0 : grspwm GENERIC MAP(
348 tech => apa3l,
352 tech => apa3l,
349 hindex => 1,
353 hindex => 1,
350 pindex => 5,
354 pindex => 5,
351 paddr => 5,
355 paddr => 5,
352 pirq => 11,
356 pirq => 11,
353 sysfreq => 25000, -- CPU_FREQ
357 sysfreq => 25000, -- CPU_FREQ
354 rmap => 1,
358 rmap => 1,
355 rmapcrc => 1,
359 rmapcrc => 1,
356 fifosize1 => 16,
360 fifosize1 => 16,
357 fifosize2 => 16,
361 fifosize2 => 16,
358 rxclkbuftype => 1,
362 rxclkbuftype => 1,
359 rxunaligned => 0,
363 rxunaligned => 0,
360 rmapbufs => 4,
364 rmapbufs => 4,
361 ft => 0,
365 ft => 0,
362 netlist => 0,
366 netlist => 0,
363 ports => 2,
367 ports => 2,
364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
368 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 memtech => apa3l,
369 memtech => apa3l,
366 destkey => 2,
370 destkey => 2,
367 spwcore => 1
371 spwcore => 1
368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
372 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
373 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
374 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 )
375 )
372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
376 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 spw_rxclk(1),
377 spw_rxclk(1),
374 clk50MHz_int,
378 clk50MHz_int,
375 clk50MHz_int,
379 clk50MHz_int,
376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
380 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
381 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 swni, swno);
382 swni, swno);
379
383
380 swni.tickin <= '0';
384 swni.tickin <= '0';
381 swni.rmapen <= '1';
385 swni.rmapen <= '1';
382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
386 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 swni.tickinraw <= '0';
387 swni.tickinraw <= '0';
384 swni.timein <= (OTHERS => '0');
388 swni.timein <= (OTHERS => '0');
385 swni.dcrstval <= (OTHERS => '0');
389 swni.dcrstval <= (OTHERS => '0');
386 swni.timerrstval <= (OTHERS => '0');
390 swni.timerrstval <= (OTHERS => '0');
387
391
388 -------------------------------------------------------------------------------
392 -------------------------------------------------------------------------------
389 -- LFR ------------------------------------------------------------------------
393 -- LFR ------------------------------------------------------------------------
390 -------------------------------------------------------------------------------
394 -------------------------------------------------------------------------------
391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
395 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392
396
393 lpp_lfr_1 : lpp_lfr
397 lpp_lfr_1 : lpp_lfr
394 GENERIC MAP (
398 GENERIC MAP (
395 Mem_use => use_RAM,
399 Mem_use => Mem_use,
396 nb_data_by_buffer_size => 32,
400 nb_data_by_buffer_size => 32,
397 --nb_word_by_buffer_size => 30,
401 --nb_word_by_buffer_size => 30,
398 nb_snapshot_param_size => 32,
402 nb_snapshot_param_size => 32,
399 delta_vector_size => 32,
403 delta_vector_size => 32,
400 delta_vector_size_f0_2 => 7, -- log2(96)
404 delta_vector_size_f0_2 => 7, -- log2(96)
401 pindex => 15,
405 pindex => 15,
402 paddr => 15,
406 paddr => 15,
403 pmask => 16#fff#,
407 pmask => 16#fff#,
404 pirq_ms => 6,
408 pirq_ms => 6,
405 pirq_wfp => 14,
409 pirq_wfp => 14,
406 hindex => 2,
410 hindex => 2,
407 top_lfr_version => X"020146") -- aa.bb.cc version
411 top_lfr_version => X"020146") -- aa.bb.cc version
408 -- AA : BOARD NUMBER
412 -- AA : BOARD NUMBER
409 -- 0 => MINI_LFR
413 -- 0 => MINI_LFR
410 -- 1 => EM
414 -- 1 => EM
411 -- 2 => EQM (with A3PE3000)
415 -- 2 => EQM (with A3PE3000)
412 PORT MAP (
416 PORT MAP (
413 clk => clk_25,
417 clk => clk_25,
414 rstn => LFR_rstn,
418 rstn => LFR_rstn,
415 sample_B => sample_s(2 DOWNTO 0),
419 sample_B => sample_s(2 DOWNTO 0),
416 sample_E => sample_s(7 DOWNTO 3),
420 sample_E => sample_s(7 DOWNTO 3),
417 sample_val => sample_val,
421 sample_val => sample_val,
418 apbi => apbi_ext,
422 apbi => apbi_ext,
419 apbo => apbo_ext(15),
423 apbo => apbo_ext(15),
420 ahbi => ahbi_m_ext,
424 ahbi => ahbi_m_ext,
421 ahbo => ahbo_m_ext(2),
425 ahbo => ahbo_m_ext(2),
422 coarse_time => coarse_time,
426 coarse_time => coarse_time,
423 fine_time => fine_time,
427 fine_time => fine_time,
424 data_shaping_BW => bias_fail_sw,
428 data_shaping_BW => bias_fail_sw,
425 debug_vector => OPEN,
429 debug_vector => OPEN,
426 debug_vector_ms => OPEN); --,
430 debug_vector_ms => OPEN); --,
427 --observation_vector_0 => OPEN,
431 --observation_vector_0 => OPEN,
428 --observation_vector_1 => OPEN,
432 --observation_vector_1 => OPEN,
429 --observation_reg => observation_reg);
433 --observation_reg => observation_reg);
430
434
431
435
432 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
436 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
433 sample_s(I) <= sample(I) & '0' & '0';
437 sample_s(I) <= sample(I) & '0' & '0';
434 END GENERATE all_sample;
438 END GENERATE all_sample;
435 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
439 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
436
440
437 -----------------------------------------------------------------------------
441 -----------------------------------------------------------------------------
438 --
442 --
439 -----------------------------------------------------------------------------
443 -----------------------------------------------------------------------------
440 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
444 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
441 GENERIC MAP (
445 GENERIC MAP (
442 ChanelCount => 9,
446 ChanelCount => 9,
443 ncycle_cnv_high => 13,
447 ncycle_cnv_high => 13,
444 ncycle_cnv => 25,
448 ncycle_cnv => 25,
445 FILTER_ENABLED => 16#FF#)
449 FILTER_ENABLED => 16#FF#)
446 PORT MAP (
450 PORT MAP (
447 cnv_clk => clk_24,
451 cnv_clk => clk_24,
448 cnv_rstn => rstn_24,
452 cnv_rstn => rstn_24,
449 cnv => ADC_smpclk_s,
453 cnv => ADC_smpclk_s,
450 clk => clk_25,
454 clk => clk_25,
451 rstn => rstn_25,
455 rstn => rstn_25,
452 ADC_data => ADC_data,
456 ADC_data => ADC_data,
453 ADC_nOE => ADC_OEB_bar_CH_s,
457 ADC_nOE => ADC_OEB_bar_CH_s,
454 sample => sample,
458 sample => sample,
455 sample_val => sample_val);
459 sample_val => sample_val);
456
460
457 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
461 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
458
462
459 ADC_smpclk <= ADC_smpclk_s;
463 ADC_smpclk <= ADC_smpclk_s;
460 HK_smpclk <= ADC_smpclk_s;
464 HK_smpclk <= ADC_smpclk_s;
461
465
462 TAG8 <= nSRAM_BUSY;
466 TAG8 <= nSRAM_BUSY;
463
467
464 -----------------------------------------------------------------------------
468 -----------------------------------------------------------------------------
465 -- HK
469 -- HK
466 -----------------------------------------------------------------------------
470 -----------------------------------------------------------------------------
467 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
471 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
468
472
473 -----------------------------------------------------------------------------
474 --
475 -----------------------------------------------------------------------------
476 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
477 lpp_bootloader_1: lpp_bootloader
478 GENERIC MAP (
479 pindex => 13,
480 paddr => 13,
481 pmask => 16#fff#,
482 hindex => 3,
483 haddr => 0,
484 hmask => 16#fff#)
485 PORT MAP (
486 HCLK => clk_25,
487 HRESETn => rstn_25,
488 apbi => apbi_ext,
489 apbo => apbo_ext(13),
490 ahbsi => ahbi_s_ext,
491 ahbso => ahbo_s_ext(3));
492 END GENERATE inst_bootloader;
469 END beh;
493 END beh;
Show file before | Show file after | Hide comments
@@ -1,55 +1,54
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
22
22
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
24 CLEAN=soft-clean
24 CLEAN=soft-clean
25
25
26 TECHLIBS = proasic3l
26 TECHLIBS = proasic3l
27
27
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
29 tmtc openchip hynix ihp gleichmann micron usbhc
29 tmtc openchip hynix ihp gleichmann micron usbhc
30
30
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
33 ./amba_lcd_16x2_ctrlr \
33 ./amba_lcd_16x2_ctrlr \
34 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_AMR \
35 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_balise \
36 ./general_purpose/lpp_delay \
36 ./general_purpose/lpp_delay \
37 ./lpp_bootloader \
38 ./dsp/lpp_fft_rtax \
37 ./dsp/lpp_fft_rtax \
39 ./lpp_uart \
38 ./lpp_uart \
40 ./lpp_usb \
39 ./lpp_usb \
41 ./lpp_sim/CY7C1061DV33 \
40 ./lpp_sim/CY7C1061DV33 \
42
41
43 FILESKIP = i2cmst.vhd \
42 FILESKIP = i2cmst.vhd \
44 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
46 Top_MatrixSpec.vhd \
45 Top_MatrixSpec.vhd \
47 APB_FFT.vhd\
46 APB_FFT.vhd\
48 CoreFFT_simu.vhd \
47 CoreFFT_simu.vhd \
49 lpp_lfr_apbreg_simu.vhd
48 lpp_lfr_apbreg_simu.vhd
50
49
51 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/bin/Makefile
52 include $(GRLIB)/software/leon3/Makefile
51 include $(GRLIB)/software/leon3/Makefile
53
52
54 ################## project specific targets ##########################
53 ################## project specific targets ##########################
55
54
Show file before | Show file after | Hide comments
@@ -1,22 +1,22
1 GRLIB=../../..
1 #GRLIB=../../..
2 CC=gcc
2 CC=gcc
3 XCC=sparc-elf-gcc -I$(GRLIB)/software/leon3 $(BOPT)
3 XCC=sparc-elf-gcc -I$(GRLIB)/software/leon3 $(BOPT)
4 XAS=sparc-elf-gcc -c -I. -I$(GRLIB)/software/leon3 $(BOPT)
4 XAS=sparc-elf-gcc -c -I. -I$(GRLIB)/software/leon3 $(BOPT)
5
5
6 bootrom.o: bootrom.S bootrom.h
6 bootrom.o: bootrom.S bootrom.h
7 $(XAS) $<
7 $(XAS) $<
8 bootrom.exe: bootrom.o
8 bootrom.exe: bootrom.o
9 $(XCC) -nostdlib -Tlinkprom -N -L./ -Ttext=0 -nostartfiles -o bootrom.exe $<
9 $(XCC) -nostdlib -Tlinkprom -N -L./ -Ttext=0 -nostartfiles -o bootrom.exe $<
10
10
11
11
12 make_bootrom : $(GRLIB)/bin/ahbrom.c
12 make_bootrom : $(GRLIB)/bin/ahbrom.c
13 @if test -r "/mingw/bin/gcc.exe"; then \
13 @if test -r "/mingw/bin/gcc.exe"; then \
14 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom -lwsock32; \
14 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom -lwsock32; \
15 else \
15 else \
16 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom; \
16 $(CC) $(GRLIB)/bin/ahbrom.c -o make_bootrom; \
17 fi;
17 fi;
18
18
19 bootrom.vhd: bootrom.exe
19 bootrom.vhd: bootrom.exe
20 make make_bootrom
20 make make_bootrom
21 sparc-elf-objcopy -O binary bootrom.exe bootrom.bin
21 sparc-elf-objcopy -O binary bootrom.exe bootrom.bin
22 ./make_bootrom bootrom.bin bootrom.vhd No newline at end of file
22 ./make_bootrom bootrom.bin bootrom.vhd
Show file before | Show file after | Hide comments
@@ -1,204 +1,214
1
1
2 /* Template boot-code for LEON3 test benches */
2 /* Template boot-code for LEON3 test benches */
3
3
4 #include "bootrom.h"
4 #include "bootrom.h"
5
5
6 #ifndef STACKSIZE
6 #ifndef STACKSIZE
7 #define STACKSIZE 0x00020000
7 #define STACKSIZE 0x00020000
8 #endif
8 #endif
9
9
10
10
11 .seg "text"
11 .seg "text"
12 .proc 0
12 .proc 0
13 .align 4
13 .align 4
14 .global start
14 .global start
15 start:
15 start:
16
16
17 flush
17 flush
18 set 0x10e0, %g1 ! init IU
18 set 0x10e0, %g1 ! init IU
19 mov %g1, %psr
19 mov %g1, %psr
20 mov %g0, %wim
20 mov %g0, %wim
21 mov %g0, %tbr
21 mov %g0, %tbr
22 mov %g0, %y
22 mov %g0, %y
23 mov %g0, %asr16
23 mov %g0, %asr16
24 nop
24 nop
25 set 0x81000f, %g1
25 set 0x81000f, %g1
26 sta %g1, [%g0] 2
26 sta %g1, [%g0] 2
27 mov %g0, %g2
27 mov %g0, %g2
28 nop
28 nop
29 nop
29 nop
30 nop
30 nop
31 nop
31 nop
32 nop
32 nop
33 or %g2, %g2, %g0
33 or %g2, %g2, %g0
34 nop
34 nop
35 nop
35 nop
36 nop
36 nop
37 nop
37 nop
38 nop
38 nop
39 #ifdef DSUADDR
39 #ifdef DSUADDR
40 set DSUADDR, %g2
40 set DSUADDR, %g2
41 st %g0, [%g2]
41 st %g0, [%g2]
42 st %g0, [%g2+0x08]
42 st %g0, [%g2+0x08]
43 st %g0, [%g2+0x20]
43 st %g0, [%g2+0x20]
44 st %g0, [%g2+0x24]
44 st %g0, [%g2+0x24]
45 st %g0, [%g2+0x40]
45 st %g0, [%g2+0x40]
46 st %g0, [%g2+0x44]
46 st %g0, [%g2+0x44]
47 st %g0, [%g2+0x50]
47 st %g0, [%g2+0x50]
48 st %g0, [%g2+0x54]
48 st %g0, [%g2+0x54]
49 st %g0, [%g2+0x58]
49 st %g0, [%g2+0x58]
50 st %g0, [%g2+0x5C]
50 st %g0, [%g2+0x5C]
51 st %g0, [%g2+0x54]
51 st %g0, [%g2+0x54]
52 #endif
52 #endif
53
53
54 2:
54 2:
55 mov %asr17, %g3
55 mov %asr17, %g3
56 and %g3, 0x1f, %g3
56 and %g3, 0x1f, %g3
57 mov %g0, %g4
57 mov %g0, %g4
58 mov %g0, %g5
58 mov %g0, %g5
59 mov %g0, %g6
59 mov %g0, %g6
60 mov %g0, %g7
60 mov %g0, %g7
61 1:
61 1:
62 mov %g0, %l0
62 mov %g0, %l0
63 mov %g0, %l1
63 mov %g0, %l1
64 mov %g0, %l2
64 mov %g0, %l2
65 mov %g0, %l3
65 mov %g0, %l3
66 mov %g0, %l4
66 mov %g0, %l4
67 mov %g0, %l5
67 mov %g0, %l5
68 mov %g0, %l6
68 mov %g0, %l6
69 mov %g0, %l7
69 mov %g0, %l7
70 mov %g0, %o0
70 mov %g0, %o0
71 mov %g0, %o1
71 mov %g0, %o1
72 mov %g0, %o2
72 mov %g0, %o2
73 mov %g0, %o3
73 mov %g0, %o3
74 mov %g0, %o4
74 mov %g0, %o4
75 mov %g0, %o5
75 mov %g0, %o5
76 mov %g0, %o6
76 mov %g0, %o6
77 mov %g0, %o7
77 mov %g0, %o7
78 subcc %g3, 1, %g3
78 subcc %g3, 1, %g3
79 bge 1b
79 bge 1b
80 save
80 save
81
81
82 mov 2, %g1
82 mov 2, %g1
83 mov %g1, %wim
83 mov %g1, %wim
84 set 0x10e0, %g1 ! enable traps
84 set 0x10e0, %g1 ! enable traps
85 mov %g1, %psr
85 mov %g1, %psr
86 nop; nop; nop;
86 nop; nop; nop;
87
87
88 mov %psr, %g1
88 mov %psr, %g1
89 srl %g1, 12, %g1
89 srl %g1, 12, %g1
90 andcc %g1, 1, %g0
90 andcc %g1, 1, %g0
91 be 1f
91 be 1f
92 nop
92 nop
93
93
94 set _fsrxx, %g3
94 set _fsrxx, %g3
95 ld [%g3], %fsr
95 ld [%g3], %fsr
96 ldd [%g3], %f0
96 ldd [%g3], %f0
97 ldd [%g3], %f2
97 ldd [%g3], %f2
98 ldd [%g3], %f4
98 ldd [%g3], %f4
99 ldd [%g3], %f6
99 ldd [%g3], %f6
100 ldd [%g3], %f8
100 ldd [%g3], %f8
101 ldd [%g3], %f10
101 ldd [%g3], %f10
102 ldd [%g3], %f12
102 ldd [%g3], %f12
103 ldd [%g3], %f14
103 ldd [%g3], %f14
104 ldd [%g3], %f16
104 ldd [%g3], %f16
105 ldd [%g3], %f18
105 ldd [%g3], %f18
106 ldd [%g3], %f20
106 ldd [%g3], %f20
107 ldd [%g3], %f22
107 ldd [%g3], %f22
108 ldd [%g3], %f24
108 ldd [%g3], %f24
109 ldd [%g3], %f26
109 ldd [%g3], %f26
110 ldd [%g3], %f28
110 ldd [%g3], %f28
111 ldd [%g3], %f30
111 ldd [%g3], %f30
112 nop
112 nop
113 nop
113 nop
114 nop
114 nop
115 nop
115 nop
116 nop
116 nop
117 faddd %f0, %f2, %f4
117 faddd %f0, %f2, %f4
118 nop
118 nop
119 nop
119 nop
120 nop
120 nop
121 nop
121 nop
122 ba 1f
122 ba 1f
123 nop
123 nop
124
124
125
125
126 .align 8
126 .align 8
127 _fsrxx:
127 _fsrxx:
128 .word 0
128 .word 0
129 .word 0
129 .word 0
130
130
131 1:
131 1:
132 mov %asr17, %g3
132 mov %asr17, %g3
133 srl %g3, 28, %g3
133 srl %g3, 28, %g3
134 andcc %g3, 0x0f, %g3
134 andcc %g3, 0x0f, %g3
135 bne 1f
135 bne 1f
136
136
137 set L2MCTRLIO, %g1
137 /* set L2MCTRLIO, %g1
138 set MCFG1, %g2
138 set MCFG1, %g2
139 st %g2, [%g1]
139 st %g2, [%g1]
140 set MCFG2, %g2
140 set MCFG2, %g2
141 st %g2, [%g1+4]
141 st %g2, [%g1+4]
142 set MCFG3, %g2
142 set MCFG3, %g2
143 st %g2, [%g1+8]
143 st %g2, [%g1+8]
144 */
144 ! set IRQCTRL, %g1
145 ! set IRQCTRL, %g1
145 ! set 0x0ffff, %g2
146 ! set 0x0ffff, %g2
146 ! st %g2, [%g1+0x10]
147 ! st %g2, [%g1+0x10]
147
148
148 #ifdef DDR2CTRLIO
149 #ifdef DDR2CTRLIO
149 set DDR2CTRLIO, %g1
150 set DDR2CTRLIO, %g1
150 set DDR2CFG4, %g2
151 set DDR2CFG4, %g2
151 st %g2, [%g1+12]
152 st %g2, [%g1+12]
152 #endif
153 #endif
153
154
154 #ifdef ASDCFG
155 #ifdef ASDCFG
155 #ifndef SDCTRLPNP
156 #ifndef SDCTRLPNP
156 #define SDCTRLPNP 0xFFFFF860
157 #define SDCTRLPNP 0xFFFFF860
157 #endif
158 #endif
158 set SDCTRLPNP, %g1
159 set SDCTRLPNP, %g1
159 ld [%g1], %g2
160 ld [%g1], %g2
160 srl %g2, 12, %g2
161 srl %g2, 12, %g2
161 set 0x01009, %g1
162 set 0x01009, %g1
162 subcc %g1, %g2, %g0
163 subcc %g1, %g2, %g0
163 bne 1f
164 bne 1f
164
165
165 set ASDCFG, %g1
166 set ASDCFG, %g1
166 set DSDCFG, %g2
167 set DSDCFG, %g2
167 st %g2, [%g1]
168 st %g2, [%g1]
168 #endif
169 #endif
169
170
170 ! %g3 = cpu index
171 ! %g3 = cpu index
171 1: set STACKSIZE, %g2
172 1: set STACKSIZE, %g2
172 mov %g0, %g1
173 mov %g0, %g1
173 2: subcc %g3, 0, %g0
174 2: subcc %g3, 0, %g0
174 be 3f
175 be 3f
175 nop
176 nop
176 add %g1, %g2, %g1
177 add %g1, %g2, %g1
177 ba 2b
178 ba 2b
178 sub %g3, 1, %g3
179 sub %g3, 1, %g3
179
180
181 3: set RAMSTART_RAMSIZE-32, %fp
182 sub %fp, %g1, %fp
183 sub %fp, 96, %sp
180
184
185 set RAMSTART, %g1
186
187 jmp %g1
188 nop
189
190 /*
181 3:
191 3:
182 set REG_BOOTLOADER, %10
192 set REG_BOOTLOADER, %10
183 ld [%10], %11
193 ld [%10], %11
184 tst %11
194 tst %11
185 be RunProg
195 be RunProg
186 inf_wait_on_boot:
196 inf_wait_on_boot:
187 nop
197 nop
188 ld [%10+4], %11
198 ld [%10+4], %11
189 tst %11
199 tst %11
190 be inf_wait_on_boot
200 be inf_wait_on_boot
191 RunProg:
201 RunProg:
192 nop
202 nop
193 ld [%10+8], %11
203 ld [%10+8], %11
194 set RAMSTART_RAMSIZE-32, %10
204 set RAMSTART_RAMSIZE-32, %10
195 add %11, %10, %fp
205 add %11, %10, %fp
196 sub %fp, %g1, %fp
206 sub %fp, %g1, %fp
197 sub %fp, 96, %sp
207 sub %fp, 96, %sp
198
208
199 mov %11, %g1
209 mov %11, %g1
200
210
201 jmp %g1
211 jmp %g1
202 nop
212 nop
203
213 */
204 .align 32
214 .align 32
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@@ -1,10 +1,12
1 #define MCFG1 0x10380233
1 #define MCFG1 0x10380233
2 #define MCFG2 0xe6A26e60
2 #define MCFG2 0xe6A26e60
3 #define MCFG3 0x000ff000
3 #define MCFG3 0x000ff000
4 #define ASDCFG 0xfff00100
4 //#define ASDCFG 0xfff00100
5 #define DSDCFG 0xe6A06e60
5 //#define DSDCFG 0xe6A06e60
6 #define L2MCTRLIO 0x80000000
6 #define L2MCTRLIO 0x80000000
7 #define IRQCTRL 0x80000200
7 #define IRQCTRL 0x80000200
8 #define RAMSTART 0x40000000
9 #define DSUADDR 0x90000000
8 #define RAMSTART_RAMSIZE 0x40100000
10 #define RAMSTART_RAMSIZE 0x40100000
9
11
10 #define REG_BOOTLOADER 0x80000D00
12 #define REG_BOOTLOADER 0x80000D00
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@@ -1,248 +1,223
1
1
2 ----------------------------------------------------------------------------
2 ----------------------------------------------------------------------------
3 -- This file is a part of the GRLIB VHDL IP LIBRARY
3 -- This file is a part of the GRLIB VHDL IP LIBRARY
4 -- Copyright (C) 2010 Aeroflex Gaisler
4 -- Copyright (C) 2010 Aeroflex Gaisler
5 ----------------------------------------------------------------------------
5 ----------------------------------------------------------------------------
6 -- Entity: ahbrom
6 -- Entity: ahbrom
7 -- File: ahbrom.vhd
7 -- File: ahbrom.vhd
8 -- Author: Jiri Gaisler - Gaisler Research
8 -- Author: Jiri Gaisler - Gaisler Research
9 -- Description: AHB rom. 0/1-waitstate read
9 -- Description: AHB rom. 0/1-waitstate read
10 ----------------------------------------------------------------------------
10 ----------------------------------------------------------------------------
11 library ieee;
11 library ieee;
12 use ieee.std_logic_1164.all;
12 use ieee.std_logic_1164.all;
13 library grlib;
13 library grlib;
14 use grlib.amba.all;
14 use grlib.amba.all;
15 use grlib.stdlib.all;
15 use grlib.stdlib.all;
16 use grlib.devices.all;
16 use grlib.devices.all;
17
17
18 entity ahbrom is
18 entity bootrom is
19 generic (
19 generic (
20 hindex : integer := 0;
20 hindex : integer := 0;
21 haddr : integer := 0;
21 haddr : integer := 0;
22 hmask : integer := 16#fff#;
22 hmask : integer := 16#fff#;
23 pipe : integer := 0;
23 pipe : integer := 0;
24 tech : integer := 0;
24 tech : integer := 0;
25 kbytes : integer := 1);
25 kbytes : integer := 1);
26 port (
26 port (
27 rst : in std_ulogic;
27 rst : in std_ulogic;
28 clk : in std_ulogic;
28 clk : in std_ulogic;
29 ahbsi : in ahb_slv_in_type;
29 ahbsi : in ahb_slv_in_type;
30 ahbso : out ahb_slv_out_type
30 ahbso : out ahb_slv_out_type
31 );
31 );
32 end;
32 end;
33
33
34 architecture rtl of ahbrom is
34 architecture rtl of bootrom is
35 constant abits : integer := 10;
35 constant abits : integer := 10;
36 constant bytes : integer := 624;
36 constant bytes : integer := 528;
37
37
38 constant hconfig : ahb_config_type := (
38 constant hconfig : ahb_config_type := (
39 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
39 0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
40 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
40 4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
41
41
42 signal romdata : std_logic_vector(31 downto 0);
42 signal romdata : std_logic_vector(31 downto 0);
43 signal addr : std_logic_vector(abits-1 downto 2);
43 signal addr : std_logic_vector(abits-1 downto 2);
44 signal hsel, hready : std_ulogic;
44 signal hsel, hready : std_ulogic;
45
45
46 begin
46 begin
47
47
48 ahbso.hresp <= "00";
48 ahbso.hresp <= "00";
49 ahbso.hsplit <= (others => '0');
49 ahbso.hsplit <= (others => '0');
50 ahbso.hirq <= (others => '0');
50 ahbso.hirq <= (others => '0');
51 ahbso.hcache <= '1';
52 ahbso.hconfig <= hconfig;
51 ahbso.hconfig <= hconfig;
53 ahbso.hindex <= hindex;
52 ahbso.hindex <= hindex;
54
53
55 reg : process (clk)
54 reg : process (clk)
56 begin
55 begin
57 if rising_edge(clk) then
56 if rising_edge(clk) then
58 addr <= ahbsi.haddr(abits-1 downto 2);
57 addr <= ahbsi.haddr(abits-1 downto 2);
59 end if;
58 end if;
60 end process;
59 end process;
61
60
62 p0 : if pipe = 0 generate
61 p0 : if pipe = 0 generate
63 ahbso.hrdata <= ahbdrivedata(romdata);
62 ahbso.hrdata <= ahbdrivedata(romdata);
64 ahbso.hready <= '1';
63 ahbso.hready <= '1';
65 end generate;
64 end generate;
66
65
67 p1 : if pipe = 1 generate
66 p1 : if pipe = 1 generate
68 reg2 : process (clk)
67 reg2 : process (clk)
69 begin
68 begin
70 if rising_edge(clk) then
69 if rising_edge(clk) then
71 hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
70 hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
72 hready <= ahbsi.hready;
71 hready <= ahbsi.hready;
73 ahbso.hready <= (not rst) or (hsel and hready) or
72 ahbso.hready <= (not rst) or (hsel and hready) or
74 (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
73 (ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
75 ahbso.hrdata <= ahbdrivedata(romdata);
74 ahbso.hrdata <= ahbdrivedata(romdata);
76 end if;
75 end if;
77 end process;
76 end process;
78 end generate;
77 end generate;
79
78
80 comb : process (addr)
79 comb : process (addr)
81 begin
80 begin
82 case conv_integer(addr) is
81 case conv_integer(addr) is
83 when 16#00000# => romdata <= X"81D82000";
82 when 16#00000# => romdata <= X"81D82000";
84 when 16#00001# => romdata <= X"03000004";
83 when 16#00001# => romdata <= X"03000004";
85 when 16#00002# => romdata <= X"821060E0";
84 when 16#00002# => romdata <= X"821060E0";
86 when 16#00003# => romdata <= X"81884000";
85 when 16#00003# => romdata <= X"81884000";
87 when 16#00004# => romdata <= X"81900000";
86 when 16#00004# => romdata <= X"81900000";
88 when 16#00005# => romdata <= X"81980000";
87 when 16#00005# => romdata <= X"81980000";
89 when 16#00006# => romdata <= X"81800000";
88 when 16#00006# => romdata <= X"81800000";
90 when 16#00007# => romdata <= X"A1800000";
89 when 16#00007# => romdata <= X"A1800000";
91 when 16#00008# => romdata <= X"01000000";
90 when 16#00008# => romdata <= X"01000000";
92 when 16#00009# => romdata <= X"03002040";
91 when 16#00009# => romdata <= X"03002040";
93 when 16#0000A# => romdata <= X"8210600F";
92 when 16#0000A# => romdata <= X"8210600F";
94 when 16#0000B# => romdata <= X"C2A00040";
93 when 16#0000B# => romdata <= X"C2A00040";
95 when 16#0000C# => romdata <= X"84100000";
94 when 16#0000C# => romdata <= X"84100000";
96 when 16#0000D# => romdata <= X"01000000";
95 when 16#0000D# => romdata <= X"01000000";
97 when 16#0000E# => romdata <= X"01000000";
96 when 16#0000E# => romdata <= X"01000000";
98 when 16#0000F# => romdata <= X"01000000";
97 when 16#0000F# => romdata <= X"01000000";
99 when 16#00010# => romdata <= X"01000000";
98 when 16#00010# => romdata <= X"01000000";
100 when 16#00011# => romdata <= X"01000000";
99 when 16#00011# => romdata <= X"01000000";
101 when 16#00012# => romdata <= X"80108002";
100 when 16#00012# => romdata <= X"80108002";
102 when 16#00013# => romdata <= X"01000000";
101 when 16#00013# => romdata <= X"01000000";
103 when 16#00014# => romdata <= X"01000000";
102 when 16#00014# => romdata <= X"01000000";
104 when 16#00015# => romdata <= X"01000000";
103 when 16#00015# => romdata <= X"01000000";
105 when 16#00016# => romdata <= X"01000000";
104 when 16#00016# => romdata <= X"01000000";
106 when 16#00017# => romdata <= X"01000000";
105 when 16#00017# => romdata <= X"01000000";
107 when 16#00018# => romdata <= X"87444000";
106 when 16#00018# => romdata <= X"05240000";
108 when 16#00019# => romdata <= X"8608E01F";
107 when 16#00019# => romdata <= X"C0208000";
109 when 16#0001A# => romdata <= X"88100000";
108 when 16#0001A# => romdata <= X"C020A008";
110 when 16#0001B# => romdata <= X"8A100000";
109 when 16#0001B# => romdata <= X"C020A020";
111 when 16#0001C# => romdata <= X"8C100000";
110 when 16#0001C# => romdata <= X"C020A024";
112 when 16#0001D# => romdata <= X"8E100000";
111 when 16#0001D# => romdata <= X"C020A040";
113 when 16#0001E# => romdata <= X"A0100000";
112 when 16#0001E# => romdata <= X"C020A044";
114 when 16#0001F# => romdata <= X"A2100000";
113 when 16#0001F# => romdata <= X"C020A050";
115 when 16#00020# => romdata <= X"A4100000";
114 when 16#00020# => romdata <= X"C020A054";
116 when 16#00021# => romdata <= X"A6100000";
115 when 16#00021# => romdata <= X"C020A058";
117 when 16#00022# => romdata <= X"A8100000";
116 when 16#00022# => romdata <= X"C020A05C";
118 when 16#00023# => romdata <= X"AA100000";
117 when 16#00023# => romdata <= X"C020A054";
119 when 16#00024# => romdata <= X"AC100000";
118 when 16#00024# => romdata <= X"87444000";
120 when 16#00025# => romdata <= X"AE100000";
119 when 16#00025# => romdata <= X"8608E01F";
121 when 16#00026# => romdata <= X"90100000";
120 when 16#00026# => romdata <= X"88100000";
122 when 16#00027# => romdata <= X"92100000";
121 when 16#00027# => romdata <= X"8A100000";
123 when 16#00028# => romdata <= X"94100000";
122 when 16#00028# => romdata <= X"8C100000";
124 when 16#00029# => romdata <= X"96100000";
123 when 16#00029# => romdata <= X"8E100000";
125 when 16#0002A# => romdata <= X"98100000";
124 when 16#0002A# => romdata <= X"A0100000";
126 when 16#0002B# => romdata <= X"9A100000";
125 when 16#0002B# => romdata <= X"A2100000";
127 when 16#0002C# => romdata <= X"9C100000";
126 when 16#0002C# => romdata <= X"A4100000";
128 when 16#0002D# => romdata <= X"9E100000";
127 when 16#0002D# => romdata <= X"A6100000";
129 when 16#0002E# => romdata <= X"86A0E001";
128 when 16#0002E# => romdata <= X"A8100000";
130 when 16#0002F# => romdata <= X"16BFFFEF";
129 when 16#0002F# => romdata <= X"AA100000";
131 when 16#00030# => romdata <= X"81E00000";
130 when 16#00030# => romdata <= X"AC100000";
132 when 16#00031# => romdata <= X"82102002";
131 when 16#00031# => romdata <= X"AE100000";
133 when 16#00032# => romdata <= X"81904000";
132 when 16#00032# => romdata <= X"90100000";
134 when 16#00033# => romdata <= X"03000004";
133 when 16#00033# => romdata <= X"92100000";
135 when 16#00034# => romdata <= X"821060E0";
134 when 16#00034# => romdata <= X"94100000";
136 when 16#00035# => romdata <= X"81884000";
135 when 16#00035# => romdata <= X"96100000";
137 when 16#00036# => romdata <= X"01000000";
136 when 16#00036# => romdata <= X"98100000";
138 when 16#00037# => romdata <= X"01000000";
137 when 16#00037# => romdata <= X"9A100000";
139 when 16#00038# => romdata <= X"01000000";
138 when 16#00038# => romdata <= X"9C100000";
140 when 16#00039# => romdata <= X"83480000";
139 when 16#00039# => romdata <= X"9E100000";
141 when 16#0003A# => romdata <= X"8330600C";
140 when 16#0003A# => romdata <= X"86A0E001";
142 when 16#0003B# => romdata <= X"80886001";
141 when 16#0003B# => romdata <= X"16BFFFEF";
143 when 16#0003C# => romdata <= X"02800024";
142 when 16#0003C# => romdata <= X"81E00000";
144 when 16#0003D# => romdata <= X"01000000";
143 when 16#0003D# => romdata <= X"82102002";
145 when 16#0003E# => romdata <= X"07000000";
144 when 16#0003E# => romdata <= X"81904000";
146 when 16#0003F# => romdata <= X"8610E178";
145 when 16#0003F# => romdata <= X"03000004";
147 when 16#00040# => romdata <= X"C108C000";
146 when 16#00040# => romdata <= X"821060E0";
148 when 16#00041# => romdata <= X"C118C000";
147 when 16#00041# => romdata <= X"81884000";
149 when 16#00042# => romdata <= X"C518C000";
148 when 16#00042# => romdata <= X"01000000";
150 when 16#00043# => romdata <= X"C918C000";
149 when 16#00043# => romdata <= X"01000000";
151 when 16#00044# => romdata <= X"CD18C000";
150 when 16#00044# => romdata <= X"01000000";
152 when 16#00045# => romdata <= X"D118C000";
151 when 16#00045# => romdata <= X"83480000";
153 when 16#00046# => romdata <= X"D518C000";
152 when 16#00046# => romdata <= X"8330600C";
154 when 16#00047# => romdata <= X"D918C000";
153 when 16#00047# => romdata <= X"80886001";
155 when 16#00048# => romdata <= X"DD18C000";
154 when 16#00048# => romdata <= X"02800024";
156 when 16#00049# => romdata <= X"E118C000";
155 when 16#00049# => romdata <= X"01000000";
157 when 16#0004A# => romdata <= X"E518C000";
156 when 16#0004A# => romdata <= X"07000000";
158 when 16#0004B# => romdata <= X"E918C000";
157 when 16#0004B# => romdata <= X"8610E1A8";
159 when 16#0004C# => romdata <= X"ED18C000";
158 when 16#0004C# => romdata <= X"C108C000";
160 when 16#0004D# => romdata <= X"F118C000";
159 when 16#0004D# => romdata <= X"C118C000";
161 when 16#0004E# => romdata <= X"F518C000";
160 when 16#0004E# => romdata <= X"C518C000";
162 when 16#0004F# => romdata <= X"F918C000";
161 when 16#0004F# => romdata <= X"C918C000";
163 when 16#00050# => romdata <= X"FD18C000";
162 when 16#00050# => romdata <= X"CD18C000";
164 when 16#00051# => romdata <= X"01000000";
163 when 16#00051# => romdata <= X"D118C000";
165 when 16#00052# => romdata <= X"01000000";
164 when 16#00052# => romdata <= X"D518C000";
166 when 16#00053# => romdata <= X"01000000";
165 when 16#00053# => romdata <= X"D918C000";
167 when 16#00054# => romdata <= X"01000000";
166 when 16#00054# => romdata <= X"DD18C000";
168 when 16#00055# => romdata <= X"01000000";
167 when 16#00055# => romdata <= X"E118C000";
169 when 16#00056# => romdata <= X"89A00842";
168 when 16#00056# => romdata <= X"E518C000";
170 when 16#00057# => romdata <= X"01000000";
169 when 16#00057# => romdata <= X"E918C000";
171 when 16#00058# => romdata <= X"01000000";
170 when 16#00058# => romdata <= X"ED18C000";
172 when 16#00059# => romdata <= X"01000000";
171 when 16#00059# => romdata <= X"F118C000";
173 when 16#0005A# => romdata <= X"01000000";
172 when 16#0005A# => romdata <= X"F518C000";
174 when 16#0005B# => romdata <= X"10800005";
173 when 16#0005B# => romdata <= X"F918C000";
175 when 16#0005C# => romdata <= X"01000000";
174 when 16#0005C# => romdata <= X"FD18C000";
176 when 16#0005D# => romdata <= X"01000000";
175 when 16#0005D# => romdata <= X"01000000";
177 when 16#0005E# => romdata <= X"00000000";
176 when 16#0005E# => romdata <= X"01000000";
178 when 16#0005F# => romdata <= X"00000000";
177 when 16#0005F# => romdata <= X"01000000";
179 when 16#00060# => romdata <= X"87444000";
178 when 16#00060# => romdata <= X"01000000";
180 when 16#00061# => romdata <= X"8730E01C";
179 when 16#00061# => romdata <= X"01000000";
181 when 16#00062# => romdata <= X"8688E00F";
180 when 16#00062# => romdata <= X"89A00842";
182 when 16#00063# => romdata <= X"12800016";
181 when 16#00063# => romdata <= X"01000000";
183 when 16#00064# => romdata <= X"03200000";
182 when 16#00064# => romdata <= X"01000000";
184 when 16#00065# => romdata <= X"05040E00";
183 when 16#00065# => romdata <= X"01000000";
185 when 16#00066# => romdata <= X"8410A233";
184 when 16#00066# => romdata <= X"01000000";
186 when 16#00067# => romdata <= X"C4204000";
185 when 16#00067# => romdata <= X"10800005";
187 when 16#00068# => romdata <= X"0539A89B";
186 when 16#00068# => romdata <= X"01000000";
188 when 16#00069# => romdata <= X"8410A260";
187 when 16#00069# => romdata <= X"01000000";
189 when 16#0006A# => romdata <= X"C4206004";
188 when 16#0006A# => romdata <= X"00000000";
190 when 16#0006B# => romdata <= X"050003FC";
189 when 16#0006B# => romdata <= X"00000000";
191 when 16#0006C# => romdata <= X"C4206008";
190 when 16#0006C# => romdata <= X"87444000";
192 when 16#0006D# => romdata <= X"82103860";
191 when 16#0006D# => romdata <= X"8730E01C";
193 when 16#0006E# => romdata <= X"C4004000";
192 when 16#0006E# => romdata <= X"8688E00F";
194 when 16#0006F# => romdata <= X"8530A00C";
193 when 16#0006F# => romdata <= X"12800001";
195 when 16#00070# => romdata <= X"03000004";
194 when 16#00070# => romdata <= X"05000080";
196 when 16#00071# => romdata <= X"82106009";
195 when 16#00071# => romdata <= X"82100000";
197 when 16#00072# => romdata <= X"80A04002";
196 when 16#00072# => romdata <= X"80A0E000";
198 when 16#00073# => romdata <= X"12800006";
197 when 16#00073# => romdata <= X"02800005";
199 when 16#00074# => romdata <= X"033FFC00";
198 when 16#00074# => romdata <= X"01000000";
200 when 16#00075# => romdata <= X"82106100";
199 when 16#00075# => romdata <= X"82004002";
201 when 16#00076# => romdata <= X"0539A81B";
200 when 16#00076# => romdata <= X"10BFFFFC";
202 when 16#00077# => romdata <= X"8410A260";
201 when 16#00077# => romdata <= X"8620E001";
203 when 16#00078# => romdata <= X"C4204000";
202 when 16#00078# => romdata <= X"3D1003FF";
204 when 16#00079# => romdata <= X"05000080";
203 when 16#00079# => romdata <= X"BC17A3E0";
205 when 16#0007A# => romdata <= X"82100000";
204 when 16#0007A# => romdata <= X"BC278001";
206 when 16#0007B# => romdata <= X"80A0E000";
205 when 16#0007B# => romdata <= X"9C27A060";
207 when 16#0007C# => romdata <= X"02800005";
206 when 16#0007C# => romdata <= X"03100000";
208 when 16#0007D# => romdata <= X"01000000";
207 when 16#0007D# => romdata <= X"81C04000";
209 when 16#0007E# => romdata <= X"82004002";
208 when 16#0007E# => romdata <= X"01000000";
210 when 16#0007F# => romdata <= X"10BFFFFC";
209 when 16#0007F# => romdata <= X"01000000";
211 when 16#00080# => romdata <= X"8620E001";
210 when 16#00080# => romdata <= X"00000000";
212 when 16#00081# => romdata <= X"15200003";
211 when 16#00081# => romdata <= X"00000000";
213 when 16#00082# => romdata <= X"9412A100";
212 when 16#00082# => romdata <= X"00000000";
214 when 16#00083# => romdata <= X"D6028000";
213 when 16#00083# => romdata <= X"00000000";
215 when 16#00084# => romdata <= X"8092C000";
214 when 16#00084# => romdata <= X"00000000";
216 when 16#00085# => romdata <= X"02800005";
217 when 16#00086# => romdata <= X"01000000";
218 when 16#00087# => romdata <= X"D602A004";
219 when 16#00088# => romdata <= X"8092C000";
220 when 16#00089# => romdata <= X"02BFFFFD";
221 when 16#0008A# => romdata <= X"01000000";
222 when 16#0008B# => romdata <= X"D602A008";
223 when 16#0008C# => romdata <= X"151003FF";
224 when 16#0008D# => romdata <= X"9412A3E0";
225 when 16#0008E# => romdata <= X"BC02C00A";
226 when 16#0008F# => romdata <= X"BC278001";
227 when 16#00090# => romdata <= X"9C27A060";
228 when 16#00091# => romdata <= X"8210000B";
229 when 16#00092# => romdata <= X"81C04000";
230 when 16#00093# => romdata <= X"01000000";
231 when 16#00094# => romdata <= X"01000000";
232 when 16#00095# => romdata <= X"01000000";
233 when 16#00096# => romdata <= X"01000000";
234 when 16#00097# => romdata <= X"01000000";
235 when 16#00098# => romdata <= X"00000000";
236 when 16#00099# => romdata <= X"00000000";
237 when 16#0009A# => romdata <= X"00000000";
238 when 16#0009B# => romdata <= X"00000000";
239 when 16#0009C# => romdata <= X"00000000";
240 when others => romdata <= (others => '-');
215 when others => romdata <= (others => '-');
241 end case;
216 end case;
242 end process;
217 end process;
243 -- pragma translate_off
218 -- pragma translate_off
244 bootmsg : report_version
219 bootmsg : report_version
245 generic map ("ahbrom" & tost(hindex) &
220 generic map ("ahbrom" & tost(hindex) &
246 ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
221 ": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
247 -- pragma translate_on
222 -- pragma translate_on
248 end;
223 end;
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@@ -1,145 +1,145
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29 LIBRARY lpp;
29 LIBRARY lpp;
30 USE lpp.lpp_bootloader_pkg.ALL;
30 USE lpp.lpp_bootloader_pkg.ALL;
31 USE lpp.apb_devices_list.ALL;
31 USE lpp.apb_devices_list.ALL;
32
32
33
33
34 ENTITY lpp_bootloader IS
34 ENTITY lpp_bootloader IS
35
35
36 GENERIC (
36 GENERIC (
37 pindex : INTEGER := 1;
37 pindex : INTEGER := 1;
38 paddr : INTEGER := 1;
38 paddr : INTEGER := 1;
39 pmask : INTEGER := 16#fff#;
39 pmask : INTEGER := 16#fff#;
40 hindex : INTEGER := 0;
40 hindex : INTEGER := 0;
41 haddr : INTEGER := 0;
41 haddr : INTEGER := 0;
42 hmask : INTEGER := 16#fff#
42 hmask : INTEGER := 16#fff#
43 );
43 );
44
44
45 PORT (
45 PORT (
46 -- AMBA AHB system signals
46 -- AMBA AHB system signals
47 HCLK : IN STD_ULOGIC;
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49
49
50 -- AMBA APB Slave Interface
50 -- AMBA APB Slave Interface
51 apbi : IN apb_slv_in_type;
51 apbi : IN apb_slv_in_type;
52 apbo : OUT apb_slv_out_type;
52 apbo : OUT apb_slv_out_type;
53
53
54 -- AMBA AHB Slave Interface
54 -- AMBA AHB Slave Interface
55 ahbsi : IN ahb_slv_in_type;
55 ahbsi : IN ahb_slv_in_type;
56 ahbso : OUT ahb_slv_out_type
56 ahbso : OUT ahb_slv_out_type
57 );
57 );
58
58
59 END lpp_bootloader;
59 END lpp_bootloader;
60
60
61 ARCHITECTURE Beh OF lpp_bootloader IS
61 ARCHITECTURE Beh OF lpp_bootloader IS
62
62
63 CONSTANT REVISION : INTEGER := 1;
63 CONSTANT REVISION : INTEGER := 1;
64
64
65 CONSTANT pconfig : apb_config_type := (
65 CONSTANT pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_BOOTLOADER_TYPE, 0, REVISION, 0),
66 0 => ahb_device_reg (VENDOR_LPP, LPP_BOOTLOADER_TYPE, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
67 1 => apb_iobar(paddr, pmask));
68
68
69 TYPE lpp_bootloader_regs IS RECORD
69 TYPE lpp_bootloader_regs IS RECORD
70 config_wait_on_boot : STD_LOGIC;
70 config_wait_on_boot : STD_LOGIC;
71 config_start_execution : STD_LOGIC;
71 config_start_execution : STD_LOGIC;
72 addr_start_execution : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_start_execution : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_fp : STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- addr_fp : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 END RECORD;
74 END RECORD;
75
75
76 SIGNAL reg : lpp_bootloader_regs;
76 SIGNAL reg : lpp_bootloader_regs;
77
77
78 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
79
79
80
80
81 BEGIN -- Beh
81 BEGIN -- Beh
82
82
83 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
84 -- AHBROM
84 -- AHBROM
85 -----------------------------------------------------------------------------
85 -----------------------------------------------------------------------------
86 ahbrom_1 : ahbrom
86 ahbrom_1 : bootrom
87 GENERIC MAP (
87 GENERIC MAP (
88 hindex => hindex,
88 hindex => hindex,
89 haddr => haddr,
89 haddr => haddr,
90 hmask => hmask,
90 hmask => hmask,
91 pipe => 0,
91 pipe => 0,
92 tech => 0,
92 tech => 0,
93 kbytes => 1)
93 kbytes => 1)
94 PORT MAP (
94 PORT MAP (
95 rst => HRESETn,
95 rst => HRESETn,
96 clk => HCLK,
96 clk => HCLK,
97 ahbsi => ahbsi,
97 ahbsi => ahbsi,
98 ahbso => ahbso);
98 ahbso => ahbso);
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 -- APB REG
101 -- APB REG
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103
103
104 lpp_bootloader_apbreg : PROCESS (HCLK, HRESETn)
104 lpp_bootloader_apbreg : PROCESS (HCLK, HRESETn)
105 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
105 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
106 BEGIN -- PROCESS lpp_dma_top
106 BEGIN -- PROCESS lpp_dma_top
107 IF HRESETn = '0' THEN -- asynchronous reset (active low)
107 IF HRESETn = '0' THEN -- asynchronous reset (active low)
108 reg.config_wait_on_boot <= '1';
108 reg.config_wait_on_boot <= '1';
109 reg.config_start_execution <= '0';
109 reg.config_start_execution <= '0';
110 reg.addr_start_execution <= X"40000000";
110 reg.addr_start_execution <= X"40000000";
111 prdata <= (OTHERS => '0');
111 prdata <= (OTHERS => '0');
112 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
112 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
113
113
114 paddr := "000000";
114 paddr := "000000";
115 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
115 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
116 prdata <= (OTHERS => '0');
116 prdata <= (OTHERS => '0');
117 IF apbi.psel(pindex) = '1' THEN
117 IF apbi.psel(pindex) = '1' THEN
118 -- APB DMA READ --
118 -- APB DMA READ --
119 CASE paddr(7 DOWNTO 2) IS
119 CASE paddr(7 DOWNTO 2) IS
120 WHEN "000000" => prdata(0) <= reg.config_wait_on_boot;
120 WHEN "000000" => prdata(0) <= reg.config_wait_on_boot;
121 prdata(31 DOWNTO 1) <= (OTHERS => '0');
121 prdata(31 DOWNTO 1) <= (OTHERS => '0');
122 WHEN "000001" => prdata(0) <= reg.config_start_execution;
122 WHEN "000001" => prdata(0) <= reg.config_start_execution;
123 prdata(31 DOWNTO 1) <= (OTHERS => '0');
123 prdata(31 DOWNTO 1) <= (OTHERS => '0');
124 WHEN "000010" => prdata <= reg.addr_start_execution;
124 WHEN "000010" => prdata <= reg.addr_start_execution;
125 WHEN OTHERS => NULL;
125 WHEN OTHERS => NULL;
126 END CASE;
126 END CASE;
127 IF (apbi.pwrite AND apbi.penable) = '1' THEN
127 IF (apbi.pwrite AND apbi.penable) = '1' THEN
128 -- APB DMA WRITE --
128 -- APB DMA WRITE --
129 CASE paddr(7 DOWNTO 2) IS
129 CASE paddr(7 DOWNTO 2) IS
130 WHEN "000000" => reg.config_wait_on_boot <= apbi.pwdata(0);
130 WHEN "000000" => reg.config_wait_on_boot <= apbi.pwdata(0);
131 WHEN "000001" => reg.config_start_execution <= apbi.pwdata(0);
131 WHEN "000001" => reg.config_start_execution <= apbi.pwdata(0);
132 WHEN "000010" => reg.addr_start_execution <= apbi.pwdata;
132 WHEN "000010" => reg.addr_start_execution <= apbi.pwdata;
133 WHEN OTHERS => NULL;
133 WHEN OTHERS => NULL;
134 END CASE;
134 END CASE;
135 END IF;
135 END IF;
136 END IF;
136 END IF;
137 END IF;
137 END IF;
138 END PROCESS lpp_bootloader_apbreg;
138 END PROCESS lpp_bootloader_apbreg;
139
139
140 apbo.pirq <= (OTHERS => '0');
140 apbo.pirq <= (OTHERS => '0');
141 apbo.pindex <= pindex;
141 apbo.pindex <= pindex;
142 apbo.pconfig <= pconfig;
142 apbo.pconfig <= pconfig;
143 apbo.prdata <= prdata;
143 apbo.prdata <= prdata;
144
144
145 END Beh;
145 END Beh;
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@@ -1,64 +1,64
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29
29
30 PACKAGE lpp_bootloader_pkg IS
30 PACKAGE lpp_bootloader_pkg IS
31
31
32 COMPONENT lpp_bootloader
32 COMPONENT lpp_bootloader
33 GENERIC (
33 GENERIC (
34 pindex : INTEGER;
34 pindex : INTEGER;
35 paddr : INTEGER;
35 paddr : INTEGER;
36 pmask : INTEGER;
36 pmask : INTEGER;
37 hindex : INTEGER;
37 hindex : INTEGER;
38 haddr : INTEGER;
38 haddr : INTEGER;
39 hmask : INTEGER);
39 hmask : INTEGER);
40 PORT (
40 PORT (
41 HCLK : IN STD_ULOGIC;
41 HCLK : IN STD_ULOGIC;
42 HRESETn : IN STD_ULOGIC;
42 HRESETn : IN STD_ULOGIC;
43 apbi : IN apb_slv_in_type;
43 apbi : IN apb_slv_in_type;
44 apbo : OUT apb_slv_out_type;
44 apbo : OUT apb_slv_out_type;
45 ahbsi : IN ahb_slv_in_type;
45 ahbsi : IN ahb_slv_in_type;
46 ahbso : OUT ahb_slv_out_type);
46 ahbso : OUT ahb_slv_out_type);
47 END COMPONENT;
47 END COMPONENT;
48
48
49 COMPONENT ahbrom
49 COMPONENT bootrom
50 GENERIC (
50 GENERIC (
51 hindex : INTEGER;
51 hindex : INTEGER;
52 haddr : INTEGER;
52 haddr : INTEGER;
53 hmask : INTEGER;
53 hmask : INTEGER;
54 pipe : INTEGER;
54 pipe : INTEGER;
55 tech : INTEGER;
55 tech : INTEGER;
56 kbytes : INTEGER);
56 kbytes : INTEGER);
57 PORT (
57 PORT (
58 rst : IN STD_ULOGIC;
58 rst : IN STD_ULOGIC;
59 clk : IN STD_ULOGIC;
59 clk : IN STD_ULOGIC;
60 ahbsi : IN ahb_slv_in_type;
60 ahbsi : IN ahb_slv_in_type;
61 ahbso : OUT ahb_slv_out_type);
61 ahbso : OUT ahb_slv_out_type);
62 END COMPONENT;
62 END COMPONENT;
63
63
64 END lpp_bootloader_pkg;
64 END lpp_bootloader_pkg;
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@@ -1,213 +1,213
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
31 USE grlib.devices.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
45 GENERIC (
46 hindex : INTEGER := 2;
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
49 version : IN INTEGER := 0
50 );
50 );
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- FIFO Interface
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
62
63 -- Controls
63 -- Controls
64 send : IN STD_LOGIC;
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
68 );
69 END;
69 END;
70
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
72
73 CONSTANT HConfig : AHB_Config_Type := (
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82
82
83 SIGNAL data_window : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
85
85
86 SIGNAL bus_request : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
88
89 BEGIN
89 BEGIN
90
90
91 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
92 AHB_Master_Out.HCONFIG <= HConfig;
92 AHB_Master_Out.HCONFIG <= HConfig;
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 AHB_Master_Out.HINDEX <= hindex;
94 AHB_Master_Out.HINDEX <= hindex;
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 AHB_Master_Out.HWRITE <= '1';
98 AHB_Master_Out.HWRITE <= '1';
99
99
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
101
102 --AHB_Master_Out.HBUSREQ <= bus_request;
102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
103 --AHB_Master_Out.HLOCK <= data_window;
104
104
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
107 -- '0';
108
108
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
111
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115
115
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
118 --ren <= NOT beat;
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 PROCESS (clk, rstn)
120 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
123 state <= IDLE;
124 done <= '0';
124 done <= '0';
125 address_counter_reg <= (OTHERS => '0');
125 address_counter_reg <= (OTHERS => '0');
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
127 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
128 AHB_Master_Out.HLOCK <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 done <= '0';
130 done <= '0';
131 CASE state IS
131 CASE state IS
132 WHEN IDLE =>
132 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
133 AHB_Master_Out.HBUSREQ <= '0';
134 AHB_Master_Out.HLOCK <= '0';
134 AHB_Master_Out.HLOCK <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
136 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
137 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
141 state <= s_ARBITER;
142 END IF;
142 END IF;
143
143
144 WHEN s_ARBITER =>
144 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
145 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
146 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
148 address_counter_reg <= (OTHERS => '0');
149
149
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
150 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
152 state <= s_CTRL;
153 END IF;
153 END IF;
154
154
155 WHEN s_CTRL =>
155 WHEN s_CTRL =>
156 AHB_Master_Out.HBUSREQ <= '1';
156 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
157 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
161 state <= s_CTRL_DATA;
162 END IF;
162 END IF;
163
163
164 WHEN s_CTRL_DATA =>
164 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
165 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
166 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
170 END IF;
171
171
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
173 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
176 state <= s_DATA;
177 END IF;
177 END IF;
178
178
179 WHEN s_DATA =>
179 WHEN s_DATA =>
180 AHB_Master_Out.HBUSREQ <= '0';
180 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
181 AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
183 IF AHB_Master_In.HREADY = '1' THEN
184 state <= IDLE;
184 state <= IDLE;
185 done <= '1';
185 done <= '1';
186 END IF;
186 END IF;
187
187
188 WHEN OTHERS => NULL;
188 WHEN OTHERS => NULL;
189 END CASE;
189 END CASE;
190 END IF;
190 END IF;
191 END PROCESS;
191 END PROCESS;
192
192
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197
197
198 -----------------------------------------------------------------------------
198 -----------------------------------------------------------------------------
199 --PROCESS (clk, rstn)
199 --PROCESS (clk, rstn)
200 --BEGIN -- PROCESS
200 --BEGIN -- PROCESS
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- address_counter_reg <= (OTHERS => '0');
202 -- address_counter_reg <= (OTHERS => '0');
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- address_counter_reg <= address_counter;
204 -- address_counter_reg <= address_counter;
205 -- END IF;
205 -- END IF;
206 --END PROCESS;
206 --END PROCESS;
207
207
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 -- address_counter_reg;
209 -- address_counter_reg;
210 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
211
211
212
212
213 END Behavioral;
213 END Behavioral;
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