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Simu MINI-LFR testbench WIP
Jean-christophe Pellion -
r684:f4b71d81044a Simu-Mini-LFR draft
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_LOGIC;
51 clk100MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
52 clk49_152MHz : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
116
117 --==========================================================================
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
124 --==========================================================================
125
125
126 SIGNAL clk_50_s : STD_LOGIC := '0';
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
132 --
133 SIGNAL errorn : STD_LOGIC;
133 SIGNAL errorn : STD_LOGIC;
134 --
134 --
135 SIGNAL I00_s : STD_LOGIC;
135 SIGNAL I00_s : STD_LOGIC;
136
136
137 -- CONSTANTS
137 -- CONSTANTS
138 CONSTANT CFG_PADTECH : INTEGER := inferred;
138 CONSTANT CFG_PADTECH : INTEGER := inferred;
139 --
139 --
140 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
140 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
141 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
141 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
142 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
142 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
143
143
144 SIGNAL apbi_ext : apb_slv_in_type;
144 SIGNAL apbi_ext : apb_slv_in_type;
145 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
145 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
146 SIGNAL ahbi_s_ext : ahb_slv_in_type;
146 SIGNAL ahbi_s_ext : ahb_slv_in_type;
147 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
147 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
148 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
148 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
149 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
149 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
150
150
151 -- Spacewire signals
151 -- Spacewire signals
152 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
155 SIGNAL spw_rxtxclk : STD_ULOGIC;
155 SIGNAL spw_rxtxclk : STD_ULOGIC;
156 SIGNAL spw_rxclkn : STD_ULOGIC;
156 SIGNAL spw_rxclkn : STD_ULOGIC;
157 SIGNAL spw_clk : STD_LOGIC;
157 SIGNAL spw_clk : STD_LOGIC;
158 SIGNAL swni : grspw_in_type;
158 SIGNAL swni : grspw_in_type;
159 SIGNAL swno : grspw_out_type;
159 SIGNAL swno : grspw_out_type;
160
160
161 --GPIO
161 --GPIO
162 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioi : gpio_in_type;
163 SIGNAL gpioo : gpio_out_type;
163 SIGNAL gpioo : gpio_out_type;
164
164
165 -- AD Converter ADS7886
165 -- AD Converter ADS7886
166 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample : Samples14v(7 DOWNTO 0);
167 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_s : Samples(7 DOWNTO 0);
168 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL sample_val : STD_LOGIC;
169 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_nCS_sig : STD_LOGIC;
170 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_CLK_sig : STD_LOGIC;
171 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
172
172
173 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 SIGNAL bias_fail_sw_sig : STD_LOGIC;
174
174
175 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
178 -----------------------------------------------------------------------------
178 -----------------------------------------------------------------------------
179
179
180 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 SIGNAL LFR_soft_rstn : STD_LOGIC;
181 SIGNAL LFR_rstn : STD_LOGIC;
181 SIGNAL LFR_rstn : STD_LOGIC;
182
182
183
183
184 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25 : STD_LOGIC;
185 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d1 : STD_LOGIC;
186 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d2 : STD_LOGIC;
187 SIGNAL rstn_25_d3 : STD_LOGIC;
187 SIGNAL rstn_25_d3 : STD_LOGIC;
188
188
189 SIGNAL rstn_24 : STD_LOGIC;
189 SIGNAL rstn_24 : STD_LOGIC;
190 SIGNAL rstn_24_d1 : STD_LOGIC;
190 SIGNAL rstn_24_d1 : STD_LOGIC;
191 SIGNAL rstn_24_d2 : STD_LOGIC;
191 SIGNAL rstn_24_d2 : STD_LOGIC;
192 SIGNAL rstn_24_d3 : STD_LOGIC;
192 SIGNAL rstn_24_d3 : STD_LOGIC;
193
193
194 SIGNAL rstn_50 : STD_LOGIC;
194 SIGNAL rstn_50 : STD_LOGIC;
195 SIGNAL rstn_50_d1 : STD_LOGIC;
195 SIGNAL rstn_50_d1 : STD_LOGIC;
196 SIGNAL rstn_50_d2 : STD_LOGIC;
196 SIGNAL rstn_50_d2 : STD_LOGIC;
197 SIGNAL rstn_50_d3 : STD_LOGIC;
197 SIGNAL rstn_50_d3 : STD_LOGIC;
198
198
199 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
199 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
200 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
200 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
201
201
202 --
202 --
203 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
204
204
205 --
205 --
206 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
206 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
207 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
207 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
208
208
209 SIGNAL nSRAM_READY : STD_LOGIC;
209 SIGNAL nSRAM_READY : STD_LOGIC;
210
210
211 BEGIN -- beh
211 BEGIN -- beh
212
212
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214 PROCESS (clk100MHz, reset)
214 PROCESS (clk100MHz, reset)
215 BEGIN -- PROCESS
215 BEGIN -- PROCESS
216 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
216 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
217 clk_50_s <= NOT clk_50_s;
217 clk_50_s <= NOT clk_50_s;
218 END IF;
218 END IF;
219 END PROCESS;
219 END PROCESS;
220 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
221
221
222 PROCESS (clk_50_s, reset)
222 PROCESS (clk_50_s, reset)
223 BEGIN -- PROCESS
223 BEGIN -- PROCESS
224 IF reset = '0' THEN -- asynchronous reset (active low)
224 IF reset = '0' THEN -- asynchronous reset (active low)
225 clk_25 <= '0';
225 clk_25 <= '0';
226 rstn_25 <= '0';
226 rstn_25 <= '0';
227 rstn_25_d1 <= '0';
227 rstn_25_d1 <= '0';
228 rstn_25_d2 <= '0';
228 rstn_25_d2 <= '0';
229 rstn_25_d3 <= '0';
229 rstn_25_d3 <= '0';
230 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
230 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
231 clk_25 <= NOT clk_25;
231 clk_25 <= NOT clk_25;
232 rstn_25_d1 <= '1';
232 rstn_25_d1 <= '1';
233 rstn_25_d2 <= rstn_25_d1;
233 rstn_25_d2 <= rstn_25_d1;
234 rstn_25_d3 <= rstn_25_d2;
234 rstn_25_d3 <= rstn_25_d2;
235 rstn_25 <= rstn_25_d3;
235 rstn_25 <= rstn_25_d3;
236 END IF;
236 END IF;
237 END PROCESS;
237 END PROCESS;
238
238
239 PROCESS (clk49_152MHz, reset)
239 PROCESS (clk49_152MHz, reset)
240 BEGIN -- PROCESS
240 BEGIN -- PROCESS
241 IF reset = '0' THEN -- asynchronous reset (active low)
241 IF reset = '0' THEN -- asynchronous reset (active low)
242 clk_24 <= '0';
242 clk_24 <= '0';
243 rstn_24_d1 <= '0';
243 rstn_24_d1 <= '0';
244 rstn_24_d2 <= '0';
244 rstn_24_d2 <= '0';
245 rstn_24_d3 <= '0';
245 rstn_24_d3 <= '0';
246 rstn_24 <= '0';
246 rstn_24 <= '0';
247 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
247 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
248 clk_24 <= NOT clk_24;
248 clk_24 <= NOT clk_24;
249 rstn_24_d1 <= '1';
249 rstn_24_d1 <= '1';
250 rstn_24_d2 <= rstn_24_d1;
250 rstn_24_d2 <= rstn_24_d1;
251 rstn_24_d3 <= rstn_24_d2;
251 rstn_24_d3 <= rstn_24_d2;
252 rstn_24 <= rstn_24_d3;
252 rstn_24 <= rstn_24_d3;
253 END IF;
253 END IF;
254 END PROCESS;
254 END PROCESS;
255
255
256 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
257
257
258 PROCESS (clk_25, rstn_25)
258 PROCESS (clk_25, rstn_25)
259 BEGIN -- PROCESS
259 BEGIN -- PROCESS
260 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
260 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
261 LED0 <= '0';
261 LED0 <= '0';
262 LED1 <= '0';
262 LED1 <= '0';
263 LED2 <= '0';
263 LED2 <= '0';
264 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
264 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
265 LED0 <= '0';
265 LED0 <= '0';
266 LED1 <= '1';
266 LED1 <= '1';
267 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
267 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
268 END IF;
268 END IF;
269 END PROCESS;
269 END PROCESS;
270
270
271 PROCESS (clk49_152MHz, rstn_24)
271 PROCESS (clk49_152MHz, rstn_24)
272 BEGIN -- PROCESS
272 BEGIN -- PROCESS
273 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
273 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
274 I00_s <= '0';
274 I00_s <= '0';
275 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
275 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
276 I00_s <= NOT I00_s;
276 I00_s <= NOT I00_s;
277 END IF;
277 END IF;
278 END PROCESS;
278 END PROCESS;
279
279
280 --UARTs
280 --UARTs
281 nCTS1 <= '1';
281 nCTS1 <= '1';
282 nCTS2 <= '1';
282 nCTS2 <= '1';
283 nDCD2 <= '1';
283 nDCD2 <= '1';
284 -- No AHB UART
284 -- No AHB UART
285 RXD1 <= TXD1;
285 -- RXD1 <= TXD1;
286
286
287 --
287 --
288
288
289 leon3_soc_1 : leon3_soc
289 leon3_soc_1 : leon3_soc
290 GENERIC MAP (
290 GENERIC MAP (
291 fabtech => apa3e,
291 fabtech => apa3e,
292 memtech => apa3e,
292 memtech => apa3e,
293 padtech => inferred,
293 padtech => inferred,
294 clktech => inferred,
294 clktech => inferred,
295 disas => 0,
295 disas => 0,
296 dbguart => 0,
296 dbguart => 0,
297 pclow => 2,
297 pclow => 2,
298 clk_freq => 25000,
298 clk_freq => 25000,
299 IS_RADHARD => 0,
299 IS_RADHARD => 0,
300 NB_CPU => 1,
300 NB_CPU => 1,
301 ENABLE_FPU => 1,
301 ENABLE_FPU => 1,
302 FPU_NETLIST => 0,
302 FPU_NETLIST => 0,
303 ENABLE_DSU => 1,
303 ENABLE_DSU => 1,
304 ENABLE_AHB_UART => 0,
304 ENABLE_AHB_UART => 1,
305 ENABLE_APB_UART => 1,
305 ENABLE_APB_UART => 1,
306 ENABLE_IRQMP => 1,
306 ENABLE_IRQMP => 1,
307 ENABLE_GPT => 1,
307 ENABLE_GPT => 1,
308 NB_AHB_MASTER => NB_AHB_MASTER,
308 NB_AHB_MASTER => NB_AHB_MASTER,
309 NB_AHB_SLAVE => NB_AHB_SLAVE,
309 NB_AHB_SLAVE => NB_AHB_SLAVE,
310 NB_APB_SLAVE => NB_APB_SLAVE,
310 NB_APB_SLAVE => NB_APB_SLAVE,
311 ADDRESS_SIZE => 20,
311 ADDRESS_SIZE => 20,
312 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
312 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
313 BYPASS_EDAC_MEMCTRLR => '0',
313 BYPASS_EDAC_MEMCTRLR => '0',
314 SRBANKSZ => 9)
314 SRBANKSZ => 9,
315 SLOW_TIMING_EMULATION => 0)
315 PORT MAP (
316 PORT MAP (
316 clk => clk_25,
317 clk => clk_25,
317 reset => rstn_25,
318 reset => rstn_25,
318 errorn => errorn,
319 errorn => errorn,
319 ahbrxd => OPEN,--TXD1,
320 ahbrxd => TXD1, -- '1'
320 ahbtxd => OPEN,--RXD1,
321 ahbtxd => RXD1, --OPEN
321 urxd1 => TXD2,
322 urxd1 => TXD2,
322 utxd1 => RXD2,
323 utxd1 => RXD2,
323 address => SRAM_A,
324 address => SRAM_A,
324 data => SRAM_DQ,
325 data => SRAM_DQ,
325 nSRAM_BE0 => SRAM_nBE(0),
326 nSRAM_BE0 => SRAM_nBE(0),
326 nSRAM_BE1 => SRAM_nBE(1),
327 nSRAM_BE1 => SRAM_nBE(1),
327 nSRAM_BE2 => SRAM_nBE(2),
328 nSRAM_BE2 => SRAM_nBE(2),
328 nSRAM_BE3 => SRAM_nBE(3),
329 nSRAM_BE3 => SRAM_nBE(3),
329 nSRAM_WE => SRAM_nWE,
330 nSRAM_WE => SRAM_nWE,
330 nSRAM_CE => SRAM_CE_s,
331 nSRAM_CE => SRAM_CE_s,
331 nSRAM_OE => SRAM_nOE,
332 nSRAM_OE => SRAM_nOE,
332 nSRAM_READY => nSRAM_READY,
333 nSRAM_READY => nSRAM_READY,
333 SRAM_MBE => OPEN,
334 SRAM_MBE => OPEN,
334 apbi_ext => apbi_ext,
335 apbi_ext => apbi_ext,
335 apbo_ext => apbo_ext,
336 apbo_ext => apbo_ext,
336 ahbi_s_ext => ahbi_s_ext,
337 ahbi_s_ext => ahbi_s_ext,
337 ahbo_s_ext => ahbo_s_ext,
338 ahbo_s_ext => ahbo_s_ext,
338 ahbi_m_ext => ahbi_m_ext,
339 ahbi_m_ext => ahbi_m_ext,
339 ahbo_m_ext => ahbo_m_ext);
340 ahbo_m_ext => ahbo_m_ext);
340
341
341 PROCESS (clk_25, rstn_25)
342 PROCESS (clk_25, rstn_25)
342 BEGIN -- PROCESS
343 BEGIN -- PROCESS
343 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
344 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
344 nSRAM_READY <= '1';
345 nSRAM_READY <= '1';
345 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
346 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
346 nSRAM_READY <= '1';
347 nSRAM_READY <= '1';
347 IF IO0 = '1' THEN
348 IF IO0 = '1' THEN
348 nSRAM_READY <= '0';
349 nSRAM_READY <= '0';
349 END IF;
350 END IF;
350 END IF;
351 END IF;
351 END PROCESS;
352 END PROCESS;
352
353
353
354
354
355
355 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
356 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
356 SRAM_CE <= not SRAM_CE_s(0);
357 SRAM_CE <= not SRAM_CE_s(0);
357 END GENERATE;
358 END GENERATE;
358
359
359 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
360 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
360 SRAM_CE <= SRAM_CE_s(0);
361 SRAM_CE <= SRAM_CE_s(0);
361 END GENERATE;
362 END GENERATE;
362 -------------------------------------------------------------------------------
363 -------------------------------------------------------------------------------
363 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
364 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
364 -------------------------------------------------------------------------------
365 -------------------------------------------------------------------------------
365 apb_lfr_management_1 : apb_lfr_management
366 apb_lfr_management_1 : apb_lfr_management
366 GENERIC MAP (
367 GENERIC MAP (
367 tech => apa3e,
368 tech => apa3e,
368 pindex => 6,
369 pindex => 6,
369 paddr => 6,
370 paddr => 6,
370 pmask => 16#fff#,
371 pmask => 16#fff#,
371 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
372 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
372 PORT MAP (
373 PORT MAP (
373 clk25MHz => clk_25,
374 clk25MHz => clk_25,
374 resetn_25MHz => rstn_25,
375 resetn_25MHz => rstn_25,
375 grspw_tick => swno.tickout,
376 grspw_tick => swno.tickout,
376 apbi => apbi_ext,
377 apbi => apbi_ext,
377 apbo => apbo_ext(6),
378 apbo => apbo_ext(6),
378 HK_sample => sample_hk,
379 HK_sample => sample_hk,
379 HK_val => sample_val,
380 HK_val => sample_val,
380 HK_sel => HK_SEL,
381 HK_sel => HK_SEL,
381 DAC_SDO => OPEN,
382 DAC_SDO => OPEN,
382 DAC_SCK => OPEN,
383 DAC_SCK => OPEN,
383 DAC_SYNC => OPEN,
384 DAC_SYNC => OPEN,
384 DAC_CAL_EN => OPEN,
385 DAC_CAL_EN => OPEN,
385 coarse_time => coarse_time,
386 coarse_time => coarse_time,
386 fine_time => fine_time,
387 fine_time => fine_time,
387 LFR_soft_rstn => LFR_soft_rstn
388 LFR_soft_rstn => LFR_soft_rstn
388 );
389 );
389
390
390 -----------------------------------------------------------------------
391 -----------------------------------------------------------------------
391 --- SpaceWire --------------------------------------------------------
392 --- SpaceWire --------------------------------------------------------
392 -----------------------------------------------------------------------
393 -----------------------------------------------------------------------
393
394
394 SPW_EN <= '1';
395 SPW_EN <= '1';
395
396
396 spw_clk <= clk_50_s;
397 spw_clk <= clk_50_s;
397 spw_rxtxclk <= spw_clk;
398 spw_rxtxclk <= spw_clk;
398 spw_rxclkn <= NOT spw_rxtxclk;
399 spw_rxclkn <= NOT spw_rxtxclk;
399
400
400 -- PADS for SPW1
401 -- PADS for SPW1
401 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
402 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
402 PORT MAP (SPW_NOM_DIN, dtmp(0));
403 PORT MAP (SPW_NOM_DIN, dtmp(0));
403 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
404 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
404 PORT MAP (SPW_NOM_SIN, stmp(0));
405 PORT MAP (SPW_NOM_SIN, stmp(0));
405 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
406 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
406 PORT MAP (SPW_NOM_DOUT, swno.d(0));
407 PORT MAP (SPW_NOM_DOUT, swno.d(0));
407 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
408 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
408 PORT MAP (SPW_NOM_SOUT, swno.s(0));
409 PORT MAP (SPW_NOM_SOUT, swno.s(0));
409 -- PADS FOR SPW2
410 -- PADS FOR SPW2
410 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
411 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
411 PORT MAP (SPW_RED_SIN, dtmp(1));
412 PORT MAP (SPW_RED_SIN, dtmp(1));
412 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
413 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
413 PORT MAP (SPW_RED_DIN, stmp(1));
414 PORT MAP (SPW_RED_DIN, stmp(1));
414 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
415 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
415 PORT MAP (SPW_RED_DOUT, swno.d(1));
416 PORT MAP (SPW_RED_DOUT, swno.d(1));
416 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
417 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
417 PORT MAP (SPW_RED_SOUT, swno.s(1));
418 PORT MAP (SPW_RED_SOUT, swno.s(1));
418
419
419 -- GRSPW PHY
420 -- GRSPW PHY
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 GENERIC MAP(
423 tech => apa3e,
424 tech => apa3e,
424 rxclkbuftype => 1,
425 rxclkbuftype => 1,
425 scantest => 0)
426 scantest => 0)
426 PORT MAP(
427 PORT MAP(
427 rxrst => swno.rxrst,
428 rxrst => swno.rxrst,
428 di => dtmp(j),
429 di => dtmp(j),
429 si => stmp(j),
430 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435 END GENERATE spw_inputloop;
435
436
436 swni.rmapnodeaddr <= (OTHERS => '0');
437 swni.rmapnodeaddr <= (OTHERS => '0');
437
438
438 -- SPW core
439 -- SPW core
439 sw0 : grspwm GENERIC MAP(
440 sw0 : grspwm GENERIC MAP(
440 tech => apa3e,
441 tech => apa3e,
441 hindex => 1,
442 hindex => 1,
442 pindex => 5,
443 pindex => 5,
443 paddr => 5,
444 paddr => 5,
444 pirq => 11,
445 pirq => 11,
445 sysfreq => 25000, -- CPU_FREQ
446 sysfreq => 25000, -- CPU_FREQ
446 rmap => 1,
447 rmap => 1,
447 rmapcrc => 1,
448 rmapcrc => 1,
448 fifosize1 => 16,
449 fifosize1 => 16,
449 fifosize2 => 16,
450 fifosize2 => 16,
450 rxclkbuftype => 1,
451 rxclkbuftype => 1,
451 rxunaligned => 0,
452 rxunaligned => 0,
452 rmapbufs => 4,
453 rmapbufs => 4,
453 ft => 0,
454 ft => 0,
454 netlist => 0,
455 netlist => 0,
455 ports => 2,
456 ports => 2,
456 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
457 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
457 memtech => apa3e,
458 memtech => apa3e,
458 destkey => 2,
459 destkey => 2,
459 spwcore => 1
460 spwcore => 1
460 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
461 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
461 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
462 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
462 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
463 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
463 )
464 )
464 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
465 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
465 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
466 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
466 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
467 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
467 swni, swno);
468 swni, swno);
468
469
469 swni.tickin <= '0';
470 swni.tickin <= '0';
470 swni.rmapen <= '1';
471 swni.rmapen <= '1';
471 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
472 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
472 swni.tickinraw <= '0';
473 swni.tickinraw <= '0';
473 swni.timein <= (OTHERS => '0');
474 swni.timein <= (OTHERS => '0');
474 swni.dcrstval <= (OTHERS => '0');
475 swni.dcrstval <= (OTHERS => '0');
475 swni.timerrstval <= (OTHERS => '0');
476 swni.timerrstval <= (OTHERS => '0');
476
477
477 -------------------------------------------------------------------------------
478 -------------------------------------------------------------------------------
478 -- LFR ------------------------------------------------------------------------
479 -- LFR ------------------------------------------------------------------------
479 -------------------------------------------------------------------------------
480 -------------------------------------------------------------------------------
480
481
481
482
482 LFR_rstn <= LFR_soft_rstn AND rstn_25;
483 LFR_rstn <= LFR_soft_rstn AND rstn_25;
483
484
484 lpp_lfr_1 : lpp_lfr
485 lpp_lfr_1 : lpp_lfr
485 GENERIC MAP (
486 GENERIC MAP (
486 Mem_use => use_RAM,
487 Mem_use => use_RAM,
488 tech => apa3e,
487 nb_data_by_buffer_size => 32,
489 nb_data_by_buffer_size => 32,
488 nb_snapshot_param_size => 32,
490 nb_snapshot_param_size => 32,
489 delta_vector_size => 32,
491 delta_vector_size => 32,
490 delta_vector_size_f0_2 => 7, -- log2(96)
492 delta_vector_size_f0_2 => 7, -- log2(96)
491 pindex => 15,
493 pindex => 15,
492 paddr => 15,
494 paddr => 15,
493 pmask => 16#fff#,
495 pmask => 16#fff#,
494 pirq_ms => 6,
496 pirq_ms => 6,
495 pirq_wfp => 14,
497 pirq_wfp => 14,
496 hindex => 2,
498 hindex => 2,
497 top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015B",
499 top_lfr_version => LPP_LFR_BOARD_MINI_LFR & X"015B",
500 DEBUG_FORCE_DATA_DMA => 0,
501 RTL_DESIGN_LIGHT => 0,
502 WINDOWS_HAANNING_PARAM_SIZE => 15,
498 DATA_SHAPING_SATURATION => 1) -- aa.bb.cc version
503 DATA_SHAPING_SATURATION => 1) -- aa.bb.cc version
499 PORT MAP (
504 PORT MAP (
500 clk => clk_25,
505 clk => clk_25,
501 rstn => LFR_rstn,
506 rstn => LFR_rstn,
502 sample_B => sample_s(2 DOWNTO 0),
507 sample_B => sample_s(2 DOWNTO 0),
503 sample_E => sample_s(7 DOWNTO 3),
508 sample_E => sample_s(7 DOWNTO 3),
504 sample_val => sample_val,
509 sample_val => sample_val,
505 apbi => apbi_ext,
510 apbi => apbi_ext,
506 apbo => apbo_ext(15),
511 apbo => apbo_ext(15),
507 ahbi => ahbi_m_ext,
512 ahbi => ahbi_m_ext,
508 ahbo => ahbo_m_ext(2),
513 ahbo => ahbo_m_ext(2),
509 coarse_time => coarse_time,
514 coarse_time => coarse_time,
510 fine_time => fine_time,
515 fine_time => fine_time,
511 data_shaping_BW => bias_fail_sw_sig,
516 data_shaping_BW => bias_fail_sw_sig,
512 debug_vector => lfr_debug_vector,
517 debug_vector => lfr_debug_vector,
513 debug_vector_ms => lfr_debug_vector_ms
518 debug_vector_ms => lfr_debug_vector_ms
514 );
519 );
515
520
516 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
521 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
517 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
522 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
518 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
523 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
519 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
524 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
520
525
521 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
526 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
522 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
527 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
523 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
528 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
524 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
529 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
525 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
530 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
526 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
531 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
527 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
532 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
528
533
529 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
534 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
530 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
535 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
531 END GENERATE all_sample;
536 END GENERATE all_sample;
532
537
533 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
538 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
534 GENERIC MAP(
539 GENERIC MAP(
535 ChannelCount => 8,
540 ChannelCount => 8,
536 SampleNbBits => 14,
541 SampleNbBits => 14,
537 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
542 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
538 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
543 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
539 PORT MAP (
544 PORT MAP (
540 -- CONV
545 -- CONV
541 cnv_clk => clk_24,
546 cnv_clk => clk_24,
542 cnv_rstn => rstn_24,
547 cnv_rstn => rstn_24,
543 cnv => ADC_nCS_sig,
548 cnv => ADC_nCS_sig,
544 -- DATA
549 -- DATA
545 clk => clk_25,
550 clk => clk_25,
546 rstn => rstn_25,
551 rstn => rstn_25,
547 sck => ADC_CLK_sig,
552 sck => ADC_CLK_sig,
548 sdo => ADC_SDO_sig,
553 sdo => ADC_SDO_sig,
549 -- SAMPLE
554 -- SAMPLE
550 sample => sample,
555 sample => sample,
551 sample_val => sample_val);
556 sample_val => sample_val);
552
557
553 ADC_nCS <= ADC_nCS_sig;
558 ADC_nCS <= ADC_nCS_sig;
554 ADC_CLK <= ADC_CLK_sig;
559 ADC_CLK <= ADC_CLK_sig;
555 ADC_SDO_sig <= ADC_SDO;
560 ADC_SDO_sig <= ADC_SDO;
556
561
557 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
562 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
558 "0010001000100010" WHEN HK_SEL = "01" ELSE
563 "0010001000100010" WHEN HK_SEL = "01" ELSE
559 "0100010001000100" WHEN HK_SEL = "10" ELSE
564 "0100010001000100" WHEN HK_SEL = "10" ELSE
560 (OTHERS => '0');
565 (OTHERS => '0');
561
566
562
567
563 ----------------------------------------------------------------------
568 ----------------------------------------------------------------------
564 --- GPIO -----------------------------------------------------------
569 --- GPIO -----------------------------------------------------------
565 ----------------------------------------------------------------------
570 ----------------------------------------------------------------------
566
571
567 grgpio0 : grgpio
572 grgpio0 : grgpio
568 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
573 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
569 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
574 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
570
575
571 gpioi.sig_en <= (OTHERS => '0');
576 gpioi.sig_en <= (OTHERS => '0');
572 gpioi.sig_in <= (OTHERS => '0');
577 gpioi.sig_in <= (OTHERS => '0');
573 gpioi.din <= (OTHERS => '0');
578 gpioi.din <= (OTHERS => '0');
574 PROCESS (clk_25, rstn_25)
579 PROCESS (clk_25, rstn_25)
575 BEGIN -- PROCESS
580 BEGIN -- PROCESS
576 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
581 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
577 IO8 <= '0';
582 IO8 <= '0';
578 IO9 <= '0';
583 IO9 <= '0';
579 IO10 <= '0';
584 IO10 <= '0';
580 IO11 <= '0';
585 IO11 <= '0';
581 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
586 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
582 CASE gpioo.dout(2 DOWNTO 0) IS
587 CASE gpioo.dout(2 DOWNTO 0) IS
583 WHEN "011" =>
588 WHEN "011" =>
584 IO8 <= observation_reg(8);
589 IO8 <= observation_reg(8);
585 IO9 <= observation_reg(9);
590 IO9 <= observation_reg(9);
586 IO10 <= observation_reg(10);
591 IO10 <= observation_reg(10);
587 IO11 <= observation_reg(11);
592 IO11 <= observation_reg(11);
588 WHEN "001" =>
593 WHEN "001" =>
589 IO8 <= observation_reg(8 + 12);
594 IO8 <= observation_reg(8 + 12);
590 IO9 <= observation_reg(9 + 12);
595 IO9 <= observation_reg(9 + 12);
591 IO10 <= observation_reg(10 + 12);
596 IO10 <= observation_reg(10 + 12);
592 IO11 <= observation_reg(11 + 12);
597 IO11 <= observation_reg(11 + 12);
593 WHEN "010" =>
598 WHEN "010" =>
594 IO8 <= '0';
599 IO8 <= '0';
595 IO9 <= '0';
600 IO9 <= '0';
596 IO10 <= '0';
601 IO10 <= '0';
597 IO11 <= '0';
602 IO11 <= '0';
598 WHEN "000" =>
603 WHEN "000" =>
599 IO8 <= observation_vector_0(8);
604 IO8 <= observation_vector_0(8);
600 IO9 <= observation_vector_0(9);
605 IO9 <= observation_vector_0(9);
601 IO10 <= observation_vector_0(10);
606 IO10 <= observation_vector_0(10);
602 IO11 <= observation_vector_0(11);
607 IO11 <= observation_vector_0(11);
603 WHEN "100" =>
608 WHEN "100" =>
604 IO8 <= observation_vector_1(8);
609 IO8 <= observation_vector_1(8);
605 IO9 <= observation_vector_1(9);
610 IO9 <= observation_vector_1(9);
606 IO10 <= observation_vector_1(10);
611 IO10 <= observation_vector_1(10);
607 IO11 <= observation_vector_1(11);
612 IO11 <= observation_vector_1(11);
608 WHEN OTHERS => NULL;
613 WHEN OTHERS => NULL;
609 END CASE;
614 END CASE;
610
615
611 END IF;
616 END IF;
612 END PROCESS;
617 END PROCESS;
613 -----------------------------------------------------------------------------
618 -----------------------------------------------------------------------------
614 --
619 --
615 -----------------------------------------------------------------------------
620 -----------------------------------------------------------------------------
616 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
621 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
617 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
622 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
618 apbo_ext(I) <= apb_none;
623 apbo_ext(I) <= apb_none;
619 END GENERATE apbo_ext_not_used;
624 END GENERATE apbo_ext_not_used;
620 END GENERATE all_apbo_ext;
625 END GENERATE all_apbo_ext;
621
626
622
627
623 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
628 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
624 ahbo_s_ext(I) <= ahbs_none;
629 ahbo_s_ext(I) <= ahbs_none;
625 END GENERATE all_ahbo_ext;
630 END GENERATE all_ahbo_ext;
626
631
627 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
632 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
628 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
633 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
629 ahbo_m_ext(I) <= ahbm_none;
634 ahbo_m_ext(I) <= ahbm_none;
630 END GENERATE ahbo_m_ext_not_used;
635 END GENERATE ahbo_m_ext_not_used;
631 END GENERATE all_ahbo_m_ext;
636 END GENERATE all_ahbo_m_ext;
632
637
633 END beh;
638 END beh;
Show file before | Show file after | Hide comments
@@ -1,326 +1,326
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4 use IEEE.std_logic_textio.all;
4 use IEEE.std_logic_textio.all;
5 LIBRARY STD;
5 LIBRARY STD;
6 use std.textio.all;
6 use std.textio.all;
7
7
8 LIBRARY grlib;
8 LIBRARY grlib;
9 USE grlib.stdlib.ALL;
9 USE grlib.stdlib.ALL;
10 LIBRARY gaisler;
10 LIBRARY gaisler;
11 USE gaisler.libdcom.ALL;
11 USE gaisler.libdcom.ALL;
12 USE gaisler.sim.ALL;
12 USE gaisler.sim.ALL;
13 USE gaisler.jtagtst.ALL;
13 USE gaisler.jtagtst.ALL;
14 LIBRARY techmap;
14 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
15 USE techmap.gencomp.ALL;
16
16
17 LIBRARY lpp;
17 LIBRARY lpp;
18 USE lpp.lpp_sim_pkg.ALL;
18 USE lpp.lpp_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
19 USE lpp.lpp_lfr_sim_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
20 USE lpp.lpp_lfr_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
21 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
22
22
23
23
24 ENTITY testbench IS
24 ENTITY testbench IS
25 END;
25 END;
26
26
27 ARCHITECTURE behav OF testbench IS
27 ARCHITECTURE behav OF testbench IS
28
28
29 COMPONENT MINI_LFR_top
29 COMPONENT MINI_LFR_top
30 PORT (
30 PORT (
31 clk_50 : IN STD_LOGIC;
31 clk100MHz : IN STD_LOGIC;
32 clk_49 : IN STD_LOGIC;
32 clk49_152MHz : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
33 reset : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
34 BP0 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
35 BP1 : IN STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
36 LED0 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
37 LED1 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
38 LED2 : OUT STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
39 TXD1 : IN STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
40 RXD1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
41 nCTS1 : OUT STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
42 nRTS1 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
43 TXD2 : IN STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
44 RXD2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
45 nCTS2 : OUT STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
46 nDTR2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
47 nRTS2 : IN STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
48 nDCD2 : OUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
49 IO0 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
50 IO1 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
51 IO2 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
52 IO3 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
53 IO4 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
54 IO5 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
55 IO6 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
56 IO7 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
57 IO8 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
58 IO9 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
59 IO10 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
60 IO11 : INOUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
61 SPW_EN : OUT STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
62 SPW_NOM_DIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
63 SPW_NOM_SIN : IN STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
64 SPW_NOM_DOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
65 SPW_NOM_SOUT : OUT STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
66 SPW_RED_DIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
67 SPW_RED_SIN : IN STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
68 SPW_RED_DOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
69 SPW_RED_SOUT : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
70 ADC_nCS : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
71 ADC_CLK : OUT STD_LOGIC;
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
72 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
73 SRAM_nWE : OUT STD_LOGIC;
73 SRAM_nWE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
74 SRAM_CE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
75 SRAM_nOE : OUT STD_LOGIC;
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
76 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
77 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
78 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
79 END COMPONENT;
79 END COMPONENT;
80
80
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL clk_50 : STD_LOGIC := '0';
82 SIGNAL clk_50 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
83 SIGNAL clk_49 : STD_LOGIC := '0';
84 SIGNAL reset : STD_LOGIC;
84 SIGNAL reset : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
85 SIGNAL BP0 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
86 SIGNAL BP1 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
87 SIGNAL LED0 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
88 SIGNAL LED1 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
89 SIGNAL LED2 : STD_LOGIC;
90 SIGNAL TXD1 : STD_LOGIC;
90 SIGNAL TXD : STD_LOGIC;
91 SIGNAL RXD1 : STD_LOGIC;
91 SIGNAL RXD : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
92 SIGNAL nCTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
93 SIGNAL nRTS1 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
94 SIGNAL TXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
95 SIGNAL RXD2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
96 SIGNAL nCTS2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
97 SIGNAL nDTR2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
98 SIGNAL nRTS2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
99 SIGNAL nDCD2 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
100 SIGNAL IO0 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
101 SIGNAL IO1 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
102 SIGNAL IO2 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
103 SIGNAL IO3 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
104 SIGNAL IO4 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
105 SIGNAL IO5 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
106 SIGNAL IO6 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
107 SIGNAL IO7 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
108 SIGNAL IO8 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
109 SIGNAL IO9 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
110 SIGNAL IO10 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
111 SIGNAL IO11 : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
112 SIGNAL SPW_EN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
113 SIGNAL SPW_NOM_DIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
114 SIGNAL SPW_NOM_SIN : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
115 SIGNAL SPW_NOM_DOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
116 SIGNAL SPW_NOM_SOUT : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
117 SIGNAL SPW_RED_DIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
118 SIGNAL SPW_RED_SIN : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
119 SIGNAL SPW_RED_DOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
120 SIGNAL SPW_RED_SOUT : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
121 SIGNAL ADC_nCS : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
122 SIGNAL ADC_CLK : STD_LOGIC;
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
123 SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
124 SIGNAL SRAM_nWE : STD_LOGIC;
124 SIGNAL SRAM_nWE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
125 SIGNAL SRAM_CE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
126 SIGNAL SRAM_nOE : STD_LOGIC;
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
128 SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
131
131
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
132 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
133 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
134 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
135
135
136
136
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
137 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
138 SIGNAL data_message : STRING(1 TO 15) := "---------------";
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
139 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
140
140
141 BEGIN
141 BEGIN
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- TB
144 -- TB
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 PROCESS
146 PROCESS
147 CONSTANT txp : TIME := 320 ns;
147 CONSTANT txp : TIME := 320 ns;
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 BEGIN -- PROCESS
149 BEGIN -- PROCESS
150 TXD1 <= '1';
150 TXD <= '1';
151 reset <= '0';
151 reset <= '0';
152 WAIT FOR 500 ns;
152 WAIT FOR 500 ns;
153 reset <= '1';
153 reset <= '1';
154 WAIT FOR 10000 ns;
154 WAIT FOR 10000 ns;
155 message_simu <= "0 - UART init ";
155 message_simu <= "0 - UART init ";
156 UART_INIT(TXD1,txp);
156 UART_INIT(TXD,txp);
157
157
158 message_simu <= "1 - UART test ";
158 message_simu <= "1 - UART test ";
159 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
159 UART_WRITE(TXD,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
160 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
160 UART_WRITE(TXD,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
161 UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
161 UART_WRITE(TXD,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
162 UART_READ(TXD1,RXD1,txp,ADDR_BASE_GPIO & "000001",data_read_v);
162 UART_READ(TXD,RXD,txp,ADDR_BASE_GPIO & "000001",data_read_v);
163 data_read <= data_read_v;
163 data_read <= data_read_v;
164 data_message <= "GPIO_data_write";
164 data_message <= "GPIO_data_write";
165
165
166 -- UNSET the LFR reset
166 -- UNSET the LFR reset
167 message_simu <= "2 - LFR UNRESET";
167 message_simu <= "2 - LFR UNRESET";
168 UNRESET_LFR(TXD1,txp,ADDR_BASE_TIME_MANAGMENT);
168 UNRESET_LFR(TXD,txp,ADDR_BASE_TIME_MANAGMENT);
169 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
169 --UART_WRITE(TXD,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
170 --UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
170 --UART_WRITE(TXD,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
171 --
171 --
172 message_simu <= "3 - LFR CONFIG ";
172 message_simu <= "3 - LFR CONFIG ";
173 --UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
173 --UART_WRITE(TXD,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
174 LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR,
174 LAUNCH_SPECTRAL_MATRIX(TXD,RXD,txp,ADDR_BASE_LFR,
175 X"40000000",
175 X"40000000",
176 X"40001000",
176 X"40001000",
177 X"40002000",
177 X"40002000",
178 X"40003000",
178 X"40003000",
179 X"40004000",
179 X"40004000",
180 X"40005000");
180 X"40005000");
181
181
182
182
183 LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
183 LAUNCH_WAVEFORM_PICKER(TXD,RXD,txp,
184 LFR_MODE_SBM1,
184 LFR_MODE_SBM1,
185 X"7FFFFFFF", -- START DATE
185 X"7FFFFFFF", -- START DATE
186
186
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
187 "00000",--DATA_SHAPING ( 4 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
188 X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
189 X"0001280A",--DELTA_F0 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
190 X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
191 X"0001283F",--DELTA_F1 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
192 X"000127FF",--DELTA_F2 (31 DOWNTO 0)
193
193
194 ADDR_BASE_LFR,
194 ADDR_BASE_LFR,
195 X"40006000",
195 X"40006000",
196 X"40007000",
196 X"40007000",
197 X"40008000",
197 X"40008000",
198 X"40009000",
198 X"40009000",
199 X"4000A000",
199 X"4000A000",
200 X"4000B000",
200 X"4000B000",
201 X"4000C000",
201 X"4000C000",
202 X"4000D000");
202 X"4000D000");
203
203
204 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
204 UART_WRITE(TXD ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
205 UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
205 UART_WRITE(TXD ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
206
206
207 message_simu <= "4 - GO GO GO !!";
207 message_simu <= "4 - GO GO GO !!";
208 UART_WRITE (TXD1 ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
208 UART_WRITE (TXD ,txp,ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE,X"00000000");
209
209
210 READ_STATUS: LOOP
210 READ_STATUS: LOOP
211 WAIT FOR 2 ms;
211 WAIT FOR 2 ms;
212 data_message <= "READ_NEW_STATUS";
212 data_message <= "READ_NEW_STATUS";
213 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
213 UART_READ(TXD,RXD,txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
214 data_read <= data_read_v;
214 data_read <= data_read_v;
215 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
215 UART_WRITE(TXD, txp,ADDR_BASE_LFR & ADDR_LFR_SM_STATUS,data_read_v);
216
216
217 UART_READ(TXD1,RXD1,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
217 UART_READ(TXD,RXD,txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
218 data_read <= data_read_v;
218 data_read <= data_read_v;
219 UART_WRITE(TXD1, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
219 UART_WRITE(TXD, txp,ADDR_BASE_LFR & ADDR_LFR_WP_STATUS,data_read_v);
220 END LOOP READ_STATUS;
220 END LOOP READ_STATUS;
221
221
222 WAIT;
222 WAIT;
223 END PROCESS;
223 END PROCESS;
224
224
225 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
226 -- CLOCK
226 -- CLOCK
227 -----------------------------------------------------------------------------
227 -----------------------------------------------------------------------------
228 clk_50 <= NOT clk_50 AFTER 5 ns;
228 clk_50 <= NOT clk_50 AFTER 5 ns;
229 clk_49 <= NOT clk_49 AFTER 10172 ps;
229 clk_49 <= NOT clk_49 AFTER 10172 ps;
230
230
231 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
232 -- DON'T CARE
232 -- DON'T CARE
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 BP0 <= '0';
234 BP0 <= '0';
235 BP1 <= '0';
235 BP1 <= '0';
236 nRTS1 <= '0' ;
236 nRTS1 <= '0' ;
237
237
238 TXD2 <= '1';
238 TXD2 <= '1';
239 nRTS2 <= '1';
239 nRTS2 <= '1';
240 nDTR2 <= '1';
240 nDTR2 <= '1';
241
241
242 SPW_NOM_DIN <= '1';
242 SPW_NOM_DIN <= '1';
243 SPW_NOM_SIN <= '1';
243 SPW_NOM_SIN <= '1';
244 SPW_RED_DIN <= '1';
244 SPW_RED_DIN <= '1';
245 SPW_RED_SIN <= '1';
245 SPW_RED_SIN <= '1';
246
246
247 ADC_SDO <= x"AA";
247 ADC_SDO <= x"AA";
248
248
249 SRAM_DQ <= (OTHERS => 'Z');
249 SRAM_DQ <= (OTHERS => 'Z');
250 --IO0 <= 'Z';
250 --IO0 <= 'Z';
251 --IO1 <= 'Z';
251 --IO1 <= 'Z';
252 --IO2 <= 'Z';
252 --IO2 <= 'Z';
253 --IO3 <= 'Z';
253 --IO3 <= 'Z';
254 --IO4 <= 'Z';
254 --IO4 <= 'Z';
255 --IO5 <= 'Z';
255 --IO5 <= 'Z';
256 --IO6 <= 'Z';
256 --IO6 <= 'Z';
257 --IO7 <= 'Z';
257 --IO7 <= 'Z';
258 --IO8 <= 'Z';
258 --IO8 <= 'Z';
259 --IO9 <= 'Z';
259 --IO9 <= 'Z';
260 --IO10 <= 'Z';
260 --IO10 <= 'Z';
261 --IO11 <= 'Z';
261 --IO11 <= 'Z';
262
262
263 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
264 -- DUT
264 -- DUT
265 -----------------------------------------------------------------------------
265 -----------------------------------------------------------------------------
266 MINI_LFR_top_1: MINI_LFR_top
266 MINI_LFR_top_1: MINI_LFR_top
267 PORT MAP (
267 PORT MAP (
268 clk_50 => clk_50,
268 clk100MHz => clk_50,
269 clk_49 => clk_49,
269 clk49_152MHz => clk_49,
270 reset => reset,
270 reset => reset,
271
271
272 BP0 => BP0,
272 BP0 => BP0,
273 BP1 => BP1,
273 BP1 => BP1,
274
274
275 LED0 => LED0,
275 LED0 => LED0,
276 LED1 => LED1,
276 LED1 => LED1,
277 LED2 => LED2,
277 LED2 => LED2,
278
278
279 TXD1 => TXD1,
279 TXD1 => TXD,
280 RXD1 => RXD1,
280 RXD1 => RXD,
281 nCTS1 => nCTS1,
281 nCTS1 => OPEN,
282 nRTS1 => nRTS1,
282 nRTS1 => '1',
283
283
284 TXD2 => TXD2,
284 TXD2 => '1',
285 RXD2 => RXD2,
285 RXD2 => OPEN,
286 nCTS2 => nCTS2,
286 nCTS2 => OPEN,
287 nDTR2 => nDTR2,
287 nDTR2 => '1',
288 nRTS2 => nRTS2,
288 nRTS2 => '0',
289 nDCD2 => nDCD2,
289 nDCD2 => OPEN,
290
290
291 IO0 => IO0,
291 IO0 => IO0,
292 IO1 => IO1,
292 IO1 => IO1,
293 IO2 => IO2,
293 IO2 => IO2,
294 IO3 => IO3,
294 IO3 => IO3,
295 IO4 => IO4,
295 IO4 => IO4,
296 IO5 => IO5,
296 IO5 => IO5,
297 IO6 => IO6,
297 IO6 => IO6,
298 IO7 => IO7,
298 IO7 => IO7,
299 IO8 => IO8,
299 IO8 => IO8,
300 IO9 => IO9,
300 IO9 => IO9,
301 IO10 => IO10,
301 IO10 => IO10,
302 IO11 => IO11,
302 IO11 => IO11,
303
303
304 SPW_EN => SPW_EN,
304 SPW_EN => SPW_EN,
305 SPW_NOM_DIN => SPW_NOM_DIN,
305 SPW_NOM_DIN => SPW_NOM_DIN,
306 SPW_NOM_SIN => SPW_NOM_SIN,
306 SPW_NOM_SIN => SPW_NOM_SIN,
307 SPW_NOM_DOUT => SPW_NOM_DOUT,
307 SPW_NOM_DOUT => SPW_NOM_DOUT,
308 SPW_NOM_SOUT => SPW_NOM_SOUT,
308 SPW_NOM_SOUT => SPW_NOM_SOUT,
309 SPW_RED_DIN => SPW_RED_DIN,
309 SPW_RED_DIN => SPW_RED_DIN,
310 SPW_RED_SIN => SPW_RED_SIN,
310 SPW_RED_SIN => SPW_RED_SIN,
311 SPW_RED_DOUT => SPW_RED_DOUT,
311 SPW_RED_DOUT => SPW_RED_DOUT,
312 SPW_RED_SOUT => SPW_RED_SOUT,
312 SPW_RED_SOUT => SPW_RED_SOUT,
313
313
314 ADC_nCS => ADC_nCS,
314 ADC_nCS => ADC_nCS,
315 ADC_CLK => ADC_CLK,
315 ADC_CLK => ADC_CLK,
316 ADC_SDO => ADC_SDO,
316 ADC_SDO => ADC_SDO,
317
317
318 SRAM_nWE => SRAM_nWE,
318 SRAM_nWE => SRAM_nWE,
319 SRAM_CE => SRAM_CE,
319 SRAM_CE => SRAM_CE,
320 SRAM_nOE => SRAM_nOE,
320 SRAM_nOE => SRAM_nOE,
321 SRAM_nBE => SRAM_nBE,
321 SRAM_nBE => SRAM_nBE,
322 SRAM_A => SRAM_A,
322 SRAM_A => SRAM_A,
323 SRAM_DQ => SRAM_DQ);
323 SRAM_DQ => SRAM_DQ);
324
324
325
325
326 END;
326 END;
Show file before | Show file after | Hide comments
@@ -1,29 +1,25
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1 { /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47 downto 0)} TIME_F0_0
3 quietly virtual signal -install /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1 { /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47 downto 0)} TIME_F0_1
4 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/TXD
4 add wave -noupdate /testbench/RXD
5 add wave -noupdate /testbench/message_simu
5 add wave -noupdate /testbench/message_simu
6 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 -radix hexadecimal}} -expand -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onNewMatrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_active_interruption_onError {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.config_ms_run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_ready_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.status_error_input_fifo_write {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.addr_matrix_f2_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.length_matrix {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f0_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f1_1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp.time_matrix_f2_1 {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
6 add wave -noupdate /testbench/data_read
7 add wave -noupdate -label time_buffer_f -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(383) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(382) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(381) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(380) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(379) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(378) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(377) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(376) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(375) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(374) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(373) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(372) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(371) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(370) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(369) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(368) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(367) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(366) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(365) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(364) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(363) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(362) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(361) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(360) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(359) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(358) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(357) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(356) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(355) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(354) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(353) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(352) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(351) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(350) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(349) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(348) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(347) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(346) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(345) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(344) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(343) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(342) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(341) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(340) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(339) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(338) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(337) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(336) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(335) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(334) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(333) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(332) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(331) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(330) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(329) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(328) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(327) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(326) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(325) -radix hexadecimal} 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{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(84) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(83) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(82) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(81) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(80) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(79) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(78) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(77) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(76) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(75) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(74) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(73) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(72) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(71) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(70) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(69) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(68) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(67) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(66) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(65) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(64) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(63) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(62) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(61) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(60) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(59) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(58) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(57) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(56) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(55) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(54) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(53) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(52) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(51) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(50) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(49) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(48) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(46) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(45) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(44) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(43) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(42) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(41) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(40) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(39) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(38) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(37) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(36) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(35) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(34) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(33) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(32) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(31) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(30) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(29) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(28) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(27) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(26) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(25) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(24) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(23) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(22) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(21) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(20) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(19) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(18) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(17) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(16) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(15) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(14) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(13) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(12) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(11) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(10) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(9) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(8) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(7) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(6) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(5) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(4) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(3) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(2) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(1) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(0) -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(383) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(382) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(381) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(380) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(379) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(378) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(377) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(376) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(375) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(374) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(373) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(372) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(371) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(370) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(369) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(368) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(367) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(366) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(365) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(364) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(363) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(362) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(361) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(360) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(359) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(358) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(357) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(356) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(355) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(354) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(353) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(352) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(351) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(350) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(349) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(348) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(347) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(346) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(345) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(344) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(343) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(342) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(341) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(340) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(339) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(338) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(337) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(336) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(335) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(334) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(333) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(332) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(331) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(330) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(329) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(328) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(327) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(326) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(325) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(324) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(323) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(322) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(321) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(320) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(319) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(318) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(317) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(316) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(315) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(314) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(313) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(312) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(311) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(310) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(309) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(308) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(307) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(306) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(305) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(304) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(303) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(302) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(301) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(300) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(299) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(298) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(297) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(296) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(295) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(294) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(293) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(292) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(291) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(290) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(289) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(288) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(287) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(286) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(285) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(284) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(283) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(282) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(281) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(280) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(279) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(278) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(277) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(276) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(275) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(274) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(273) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(272) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(271) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(270) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(269) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(268) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(267) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(266) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(265) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(264) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(263) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(262) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(261) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(260) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(259) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(258) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(257) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(256) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(255) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(254) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(253) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(252) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(251) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(250) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(249) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(248) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(247) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(246) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(245) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(244) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(243) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(242) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(241) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(240) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(239) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(238) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(237) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(236) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(235) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(234) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(233) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(232) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(231) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(230) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(229) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(228) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(227) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(226) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(225) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(224) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(223) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(222) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(221) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(220) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(219) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(218) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(217) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(216) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(215) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(214) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(213) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(212) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(211) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(210) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(209) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(208) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(207) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(206) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(205) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(204) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(203) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(202) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(201) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(200) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(199) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(198) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(197) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(196) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(195) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(194) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(193) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(192) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(191) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(190) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(189) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(188) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(187) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(186) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(185) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(184) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(183) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(182) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(181) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(180) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(179) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(178) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(177) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(176) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(175) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(174) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(173) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(172) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(171) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(170) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(169) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(168) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(167) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(166) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(165) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(164) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(163) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(162) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(161) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(160) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(159) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(158) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(157) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(156) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(155) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(154) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(153) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(152) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(151) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(150) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(149) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(148) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(147) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(146) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(145) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(144) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(143) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(142) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(141) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(140) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(139) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(138) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(137) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(136) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(135) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(134) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(133) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(132) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(131) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(130) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(129) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(128) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(127) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(126) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(125) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(124) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(123) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(122) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(121) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(120) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(119) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(118) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(117) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(116) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(115) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(114) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(113) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(112) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(111) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(110) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(109) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(108) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(107) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(106) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(105) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(104) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(103) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(102) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(101) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(100) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(99) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(98) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(97) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(96) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(95) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(94) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(93) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(92) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(91) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(90) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(89) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(88) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(87) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(86) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(85) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(84) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(83) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(82) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(81) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(80) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(79) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(78) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(77) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(76) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(75) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(74) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(73) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(72) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(71) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(70) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(69) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(68) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(67) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(66) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(65) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(64) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(63) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(62) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(61) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(60) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(59) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(58) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(57) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(56) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(55) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(54) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(53) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(52) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(51) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(50) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(49) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(48) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(46) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(45) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(44) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(43) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(42) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(41) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(40) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(39) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(38) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(37) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(36) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(35) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(34) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(33) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(32) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(31) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(30) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(29) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(28) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(27) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(26) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(25) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(24) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(23) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(22) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(21) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(20) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(19) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(18) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(17) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(16) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(15) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(14) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(13) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(12) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(11) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(10) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(9) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(8) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(7) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(6) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(5) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(4) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(3) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(2) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(1) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(0) {-radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f
7 add wave -noupdate /testbench/data_message
8 add wave -noupdate -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f -radix hexadecimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(383) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(382) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(381) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(380) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(379) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(378) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(377) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(376) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(375) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(374) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(373) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(372) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(371) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(370) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(369) -radix hexadecimal} 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{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(8) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(7) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(6) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(5) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(4) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(3) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(2) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(1) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(0) -radix hexadecimal}}} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date -radix hexadecimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_new_err {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_BW {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_SP1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.data_shaping_R2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_snapshot {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f0_2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.delta_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_data_by_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.nb_snapshot_param {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.enable_f3 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f0 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f1 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.burst_f2 {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.run {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.status_ready_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.addr_buffer_f {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f {-height 15 -radix hexadecimal -childformat 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{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(373) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(372) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(371) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(370) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(369) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(368) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(367) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(366) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(365) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(364) -radix hexadecimal} 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{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(353) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(352) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(351) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(350) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(349) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(348) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(347) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(346) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(345) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(344) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(343) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(342) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(341) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(340) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(339) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(338) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(337) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(336) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(335) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(334) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(333) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(332) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(331) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(330) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(329) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(328) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(327) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(326) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(325) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(324) -radix hexadecimal} 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{/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(53) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(52) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(51) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(50) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(49) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(48) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(46) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(45) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(44) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(43) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(42) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(41) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(40) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(39) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(38) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(37) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(36) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(35) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(34) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(33) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(32) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(31) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(30) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(29) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(28) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(27) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(26) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(25) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(24) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(23) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(22) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(21) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(20) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(19) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(18) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(17) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(16) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(15) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(14) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(13) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(12) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(11) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(10) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(9) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(8) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(7) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(6) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(5) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(4) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(3) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(2) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(1) -radix hexadecimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(0) -radix hexadecimal}}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(383) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(382) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(381) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(380) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(379) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(378) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(377) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(376) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(375) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(374) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(373) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(372) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(371) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(370) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(369) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(368) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(367) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(366) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(365) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(364) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(363) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(362) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(361) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(360) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(359) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(358) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(357) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(356) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(355) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(354) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(353) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(352) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(351) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(350) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(349) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(348) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(347) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(346) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(345) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(344) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(343) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(342) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(341) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(340) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(339) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(338) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(337) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(336) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(335) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(334) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(333) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(332) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(331) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(330) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(329) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(328) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(327) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(326) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(325) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(324) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(323) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(322) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(321) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(320) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(319) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(318) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(317) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(316) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(315) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(314) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(313) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(312) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(311) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(310) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(309) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(308) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(307) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(306) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(305) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(304) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(303) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(302) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(301) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(300) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(299) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(298) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(297) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(296) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(295) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(294) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(293) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(292) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(291) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(290) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(289) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(288) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(287) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(286) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(285) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(284) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(283) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(282) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(281) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(280) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(279) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(278) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(277) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(276) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(275) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(274) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(273) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(272) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(271) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(270) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(269) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(268) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(267) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(266) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(265) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(264) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(263) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(262) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(261) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(260) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(259) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(258) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(257) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(256) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(255) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(254) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(253) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(252) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(251) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(250) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(249) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(248) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(247) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(246) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(245) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(244) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(243) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(242) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(241) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(240) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(239) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(238) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(237) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(236) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(235) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(234) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(233) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(232) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(231) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(230) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(229) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(228) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(227) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(226) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(225) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(224) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(223) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(222) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(221) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(220) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(219) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(218) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(217) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(216) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(215) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(214) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(213) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(212) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(211) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(210) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(209) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(208) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(207) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(206) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(205) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(204) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(203) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(202) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(201) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(200) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(199) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(198) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(197) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(196) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(195) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(194) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(193) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(192) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(191) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(190) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(189) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(188) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(187) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(186) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(185) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(184) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(183) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(182) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(181) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(180) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(179) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(178) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(177) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(176) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(175) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(174) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(173) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(172) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(171) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(170) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(169) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(168) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(167) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(166) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(165) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(164) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(163) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(162) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(161) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(160) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(159) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(158) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(157) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(156) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(155) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(154) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(153) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(152) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(151) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(150) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(149) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(148) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(147) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(146) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(145) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(144) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(143) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(142) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(141) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(140) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(139) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(138) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(137) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(136) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(135) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(134) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(133) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(132) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(131) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(130) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(129) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(128) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(127) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(126) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(125) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(124) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(123) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(122) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(121) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(120) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(119) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(118) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(117) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(116) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(115) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(114) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(113) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(112) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(111) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(110) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(109) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(108) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(107) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(106) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(105) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(104) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(103) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(102) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(101) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(100) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(99) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(98) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(97) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(96) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(95) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(94) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(93) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(92) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(91) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(90) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(89) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(88) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(87) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(86) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(85) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(84) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(83) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(82) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(81) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(80) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(79) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(78) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(77) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(76) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(75) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(74) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(73) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(72) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(71) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(70) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(69) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(68) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(67) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(66) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(65) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(64) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(63) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(62) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(61) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(60) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(59) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(58) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(57) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(56) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(55) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(54) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(53) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(52) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(51) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(50) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(49) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(48) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(47) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(46) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(45) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(44) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(43) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(42) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(41) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(40) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(39) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(38) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(37) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(36) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(35) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(34) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(33) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(32) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(31) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(30) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(29) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(28) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(27) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(26) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(25) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(24) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(23) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(22) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(21) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(20) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(19) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(18) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(17) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(16) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(15) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(14) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(13) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(12) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(11) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(10) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(9) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(8) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(7) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(6) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(5) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(4) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(3) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(2) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(1) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.time_buffer_f(0) {-radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.length_buffer {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.error_buffer_full {-height 15 -radix hexadecimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp.start_date {-height 15 -radix hexadecimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
9 add wave -noupdate /testbench/MINI_LFR_top_1/lpp_lfr_1/lpp_lfr_ms_1/ongoing
10 add wave -noupdate -radix decimal /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/burst_send_counter
11 add wave -noupdate -radix decimal -childformat {{/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(25) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(24) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(23) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(22) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(21) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(20) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(19) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(18) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(17) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(16) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(15) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(14) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(13) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(12) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(11) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(10) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(9) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(8) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(7) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(6) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(5) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(4) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(3) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(2) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(1) -radix decimal} {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(0) -radix decimal}} -subitemconfig {/testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(25) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(24) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(23) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(22) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(21) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(20) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(19) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(18) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(17) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(16) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(15) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(14) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(13) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(12) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(11) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(10) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(9) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(8) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(7) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(6) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(5) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(4) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(3) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(2) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(1) {-radix decimal} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length(0) {-radix decimal}} /testbench/MINI_LFR_top_1/lpp_lfr_1/DMA_SubSystem_1/all_buffer(1)/DMA_SubSystem_GestionBuffer_I/buffer_length
12 TreeUpdate [SetDefaultTree]
8 TreeUpdate [SetDefaultTree]
13 WaveRestoreCursors {{Cursor 1} {14589665000 ps} 0} {{Cursor 2} {126327585000 ps} 0} {{Cursor 3} {188824345000 ps} 0}
9 WaveRestoreCursors {{Cursor 1} {8473586507 ps} 0}
14 quietly wave cursor active 1
10 quietly wave cursor active 1
15 configure wave -namecolwidth 682
11 configure wave -namecolwidth 438
16 configure wave -valuecolwidth 100
12 configure wave -valuecolwidth 100
17 configure wave -justifyvalue left
13 configure wave -justifyvalue left
18 configure wave -signalnamewidth 0
14 configure wave -signalnamewidth 0
19 configure wave -snapdistance 10
15 configure wave -snapdistance 10
20 configure wave -datasetprefix 0
16 configure wave -datasetprefix 0
21 configure wave -rowmargin 4
17 configure wave -rowmargin 4
22 configure wave -childrowmargin 2
18 configure wave -childrowmargin 2
23 configure wave -gridoffset 0
19 configure wave -gridoffset 0
24 configure wave -gridperiod 1
20 configure wave -gridperiod 1
25 configure wave -griddelta 40
21 configure wave -griddelta 40
26 configure wave -timeline 0
22 configure wave -timeline 0
27 configure wave -timelineunits ns
23 configure wave -timelineunits ns
28 update
24 update
29 WaveRestoreZoom {0 ps} {102545904300 ps}
25 WaveRestoreZoom {0 ps} {9037586250 ps}
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