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For simulation :...
pellion -
r686:ea8efb0bdfd4 Simu-LFR-FM draft
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 ENTITY spw_receiver IS
9 GENERIC(
10 FNAME : STRING := "output.txt"
11 );
12 PORT(
13 end_of_simu : IN STD_LOGIC;
14 timestamp : IN integer;
15
16 clk : IN STD_LOGIC;
17
18 rxread : out STD_LOGIC;
19 rxflag : in STD_LOGIC;
20 rxdata : in STD_LOGIC_VECTOR(7 DOWNTO 0);
21 rxvalid : in STD_LOGIC;
22 rxhalff : out STD_LOGIC
23 );
24 END spw_receiver;
25
26 ARCHITECTURE beh OF spw_receiver IS
27
28 FILE output_file : TEXT OPEN write_mode IS FNAME;
29
30 SIGNAL message_ongoing : STD_LOGIC := '0';
31 SIGNAL message_timestamp : INTEGER;
32
33 BEGIN
34 -----------------------------------------------------------------------------
35 -- Data orginization in the output file :
36 -----------------------------------------------------------------------------
37 -- Exemple of output.txt file :
38 -- Data_1
39 -- Data_2
40 -- ...
41 -- Data_N
42 -- TIME= TimeStamp_when_Data_1_was_received
43 -- Data_N+1
44 -- Data_N+2
45 -- ...
46 -- Data_M
47 -- TIME= TimeStamp_when_Data_N+1_was_received
48 -- Data_M+1
49 -- Data_M+2
50 -- ...
51 -- Data_K
52 -- TIME= TimeStamp_when_Data_M+1_was_received
53 -----------------------------------------------------------------------------
54 -- TimeStamp : integer. Waiting time (in ns) before to send the following message
55 -- Data : integer(0 to 255). A part of the message.
56 -----------------------------------------------------------------------------
57
58 PROCESS(clk,end_of_simu)
59 VARIABLE line_var : LINE;
60 BEGIN
61 IF end_of_simu = '1' THEN
62 file_close(output_file);
63 rxread <= '0';
64 ELSIF clk'EVENT AND clk = '1' THEN
65 rxread <= '1';
66 IF rxvalid = '1' THEN
67 IF rxflag = '1' THEN
68 write(line_var, "TIME= " & INTEGER'IMAGE(message_timestamp));
69 message_ongoing <= '0';
70 ELSE
71 IF message_ongoing = '0' THEN
72 message_ongoing <= '1';
73 message_timestamp <= TimeStamp;
74 END IF;
75 write(line_var, INTEGER'IMAGE(to_integer(UNSIGNED(rxdata))));
76 END IF;
77 writeline(output_file, line_var);
78 END IF;
79 END IF;
80 END PROCESS;
81
82 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 ENTITY spw_sender IS
9 GENERIC(
10 FNAME : STRING := "input.txt"
11 );
12 PORT(
13 end_of_simu : OUT STD_LOGIC;
14 start_of_simu : IN STD_LOGIC;
15
16 clk : IN STD_LOGIC;
17 txwrite : OUT STD_LOGIC;
18 txflag : OUT STD_LOGIC;
19 txdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
20 txrdy : IN STD_LOGIC;
21 txhalff : IN STD_LOGIC
22 );
23 END spw_sender;
24
25 ARCHITECTURE beh OF spw_sender IS
26 FILE input_file : TEXT OPEN read_mode IS FNAME;
27
28 BEGIN
29 -----------------------------------------------------------------------------
30 -- Data orginization in the input file :
31 -----------------------------------------------------------------------------
32 -- Exemple of input.txt file :
33 -- Time1 N1
34 -- Data_1
35 -- Data_2
36 -- ...
37 -- Data_N1
38 -- Time2 N2
39 -- Data_1
40 -- Data_2
41 -- ...
42 -- Data_N2
43 -- ...
44 -- TimeK NK
45 -- Data_1
46 -- Data_2
47 -- ...
48 -- Data_NK
49 -----------------------------------------------------------------------------
50 -- Time : integer. Waiting time (in ns) before to send the following message
51 -- N : integer. Length (in Byte) of the following message.
52 -- Data : integer(0 to 255). A part of the message.
53 -----------------------------------------------------------------------------
54
55 PROCESS IS
56 VARIABLE line_var : LINE;
57 VARIABLE waiting_time : INTEGER;
58 VARIABLE length_of_message : INTEGER;
59 VARIABLE value : INTEGER;
60 BEGIN -- PROCESS
61 txwrite <= '0';
62 txflag <= '0';
63 WAIT UNTIL clk = '1';
64 IF start_of_simu = '1' THEN
65
66 IF endfile(input_file) THEN
67 end_of_simu <= '1';
68 ELSE
69 end_of_simu <= '0';
70 readline(input_file, line_var);
71 read(line_var, waiting_time);
72 read(line_var, length_of_message);
73
74 WAIT FOR waiting_time * 1 ns;
75
76 FOR char_number IN 0 TO length_of_message-1 LOOP
77 WAIT UNTIL clk = '1' AND txrdy = '1';
78 readline(input_file, line_var);
79 read(line_var, value);
80 txwrite <= '1';
81 txflag <= '0';
82 txdata <= STD_LOGIC_VECTOR(to_unsigned(value, txdata'LENGTH));
83 END LOOP; -- char_number
84 WAIT UNTIL clk = '1' AND txrdy = '1';
85 txwrite <= '1';
86 txflag <= '1';
87 txdata <= (OTHERS => '0');
88 WAIT UNTIL clk = '1';
89 txwrite <= '0';
90 txflag <= '0';
91
92 END IF;
93 END IF;
94
95 END PROCESS;
96
97 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=testbench
5 BOARD=LFR-FM
6 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=
9 QSF=
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT=
13 VHDLSYNFILES=
14 VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd
15 SIMTOP=testbench
16 CLEAN=soft-clean
17
18 TECHLIBS = axcelerator
19
20
21 LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron
22
23 DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \
24 leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \
25 ./amba_lcd_16x2_ctrlr \
26 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_delay \
29 ./lpp_bootloader \
30 ./lpp_uart \
31 ./lpp_usb \
32 ./lpp_debug_lfr \
33 ./dsp/lpp_fft
34
35 FILESKIP = i2cmst.vhd \
36 APB_MULTI_DIODE.vhd \
37 APB_MULTI_DIODE.vhd \
38 Top_MatrixSpec.vhd \
39 APB_FFT.vhd \
40 lpp_lfr_sim_pkg.vhd
41
42 include $(GRLIB)/bin/Makefile
43 include $(GRLIB)/software/leon3/Makefile
44 ################## project specific targets ##########################
45 distclean:myclean
46
47 myclean:
48 rm -f input.txt output_fx.txt *.log
49 rm -rf ./2016*
50
51 test: | ghdl ghdl-run archivate
52
53
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1 20 3
2 28
3 14
4 32
5 1500 2
6 18
7 200
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1 28
2 14
3 32
4 TIME= 45020
5 18
6 200
7 TIME= 47660
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE ieee.numeric_std.ALL;
5 USE IEEE.std_logic_signed.ALL;
6 USE IEEE.MATH_real.ALL;
7
8 LIBRARY techmap;
9 USE techmap.gencomp.ALL;
10
11 LIBRARY std;
12 USE std.textio.ALL;
13
14 LIBRARY opencores;
15 USE opencores.spwpkg.ALL;
16 USE opencores.spwambapkg.ALL;
17
18 LIBRARY lpp;
19 USE lpp.lpp_sim_pkg.ALL;
20
21 ENTITY testbench IS
22 END;
23
24 ARCHITECTURE behav OF testbench IS
25
26 SIGNAL TSTAMP : INTEGER := 0;
27 SIGNAL clk : STD_LOGIC := '0';
28 SIGNAL rst : STD_LOGIC;
29
30 SIGNAL end_of_simu : STD_LOGIC := '0';
31
32 SIGNAL autostart : STD_LOGIC := '1';
33 SIGNAL linkstart : STD_LOGIC := '1';
34 SIGNAL linkdis : STD_LOGIC := '0';
35 SIGNAL ctrl_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
36 SIGNAL time_in : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
37 SIGNAL txwrite : STD_LOGIC := '0';
38 SIGNAL txflag : STD_LOGIC := '0';
39 SIGNAL txdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
40 SIGNAL txrdy : STD_LOGIC;
41 SIGNAL txhalff : STD_LOGIC;
42 SIGNAL tick_out : STD_LOGIC;
43 SIGNAL ctrl_out : STD_LOGIC_VECTOR(1 DOWNTO 0);
44 SIGNAL time_out : STD_LOGIC_VECTOR(5 DOWNTO 0);
45 SIGNAL rxvalid : STD_LOGIC;
46 SIGNAL rxhalff : STD_LOGIC;
47 SIGNAL rxflag : STD_LOGIC;
48 SIGNAL rxdata : STD_LOGIC_VECTOR(7 DOWNTO 0);
49 SIGNAL rxread : STD_LOGIC := '0';
50 SIGNAL started : STD_LOGIC;
51 SIGNAL connecting : STD_LOGIC;
52 SIGNAL running : STD_LOGIC;
53 SIGNAL errdisc : STD_LOGIC;
54 SIGNAL errpar : STD_LOGIC;
55 SIGNAL erresc : STD_LOGIC;
56 SIGNAL errcred : STD_LOGIC;
57
58 SIGNAL spw_di : std_logic;
59 SIGNAL spw_si : std_logic;
60 SIGNAL spw_do : std_logic;
61 SIGNAL spw_so : std_logic;
62
63 BEGIN
64
65 -----------------------------------------------------------------------------
66 -- CLOCK and RESET
67 -----------------------------------------------------------------------------
68 PROCESS
69 BEGIN -- PROCESS
70 WAIT UNTIL clk = '1';
71 rst <= '1';
72 WAIT UNTIL clk = '1';
73 WAIT UNTIL clk = '1';
74 WAIT UNTIL clk = '1';
75 rst <= '0';
76 WAIT UNTIL end_of_simu = '1';
77 WAIT FOR 10 ps;
78 ASSERT false REPORT "end of test" SEVERITY note;
79 -- Wait forever; this will finish the simulation.
80 WAIT;
81 END PROCESS;
82 -----------------------------------------------------------------------------
83
84 clk_50M_gen : PROCESS
85 BEGIN
86 IF end_of_simu /= '1' THEN
87 clk <= NOT clk;
88 TSTAMP <= TSTAMP+20;
89 WAIT FOR 10 ns;
90 ELSE
91 WAIT FOR 10 ps;
92 ASSERT false REPORT "end of test" SEVERITY note;
93 WAIT;
94 END IF;
95 END PROCESS;
96
97
98 SPW : spwstream
99
100 GENERIC MAP(
101 sysfreq => 50.0e6,
102 txclkfreq => 50.0e6,
103 rximpl => impl_generic,
104 rxchunk => 1,
105 tximpl => impl_generic,
106 rxfifosize_bits => 11,
107 txfifosize_bits => 11
108 )
109
110 PORT MAP(
111 -- System clock.
112 clk => clk,
113 rxclk => clk,
114 txclk => clk,
115 rst => rst,
116
117
118 autostart => autostart, -- Enables automatic link start on receipt of a NULL character.
119 linkstart => linkstart, -- Enables link start once the Ready state is reached. Without autostart or linkstart, the link remains in state Ready.
120 linkdis => linkdis, -- Do not start link (overrides linkstart and autostart) and/or disconnect a running link.
121
122 txdivcnt => X"00",
123
124
125 -------------------------------------------------------------------------
126 -- TimeCode transmission
127 tick_in => '0', -- High for one clock cycle to request transmission of a TimeCode. The request is registered inside the entity until it can be processed.
128 ctrl_in => ctrl_in, -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
129 time_in => time_in, -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
130 -------------------------------------------------------------------------
131
132 -------------------------------------------------------------------------
133 -- ### tx data ### tb -> SPW-light
134 txwrite => txwrite, -- Pulled high by the application to write an N-Char to the transmit queue.
135 -- If "txwrite" and "txrdy" are both high on the rising edge of "clk", a character is added to the transmit queue.
136 -- This signal has no effect if "txrdy" is low.
137 txflag => txflag, -- Control flag to be sent with the next N_Char. Must be valid while txwrite is high.
138 txdata => txdata, -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. Must be valid while txwrite is high.
139 txrdy => txrdy, -- High if the entity is ready to accept an N-Char for transmission.
140 txhalff => txhalff, -- High if the transmission queue is at least half full.
141 -------------------------------------------------------------------------
142
143 -------------------------------------------------------------------------
144 -- TimeCode reception
145 tick_out => tick_out, -- High for one clock cycle if a TimeCode was just received.
146 ctrl_out => ctrl_out, -- Control bits of the last received TimeCode.
147 time_out => time_out, -- Counter value of the last received TimeCode.
148 -------------------------------------------------------------------------
149
150
151 -------------------------------------------------------------------------
152 -- ### rx data ### tb <- SPW-light
153 rxvalid => rxvalid, -- High if "rxflag" and "rxdata" contain valid data. This signal is high unless the receive FIFO is empty.
154 rxhalff => rxhalff, -- High if the receive FIFO is at least half full.
155 rxflag => rxflag, -- High if the received character is EOP or EEP; low if the received character is a data byte. Valid if "rxvalid" is high.
156 rxdata => rxdata, -- Received byte, or "00000000" for EOP or "00000001" for EEP. Valid if "rxvalid" is high.
157 rxread => rxread, -- Pulled high by the application to accept a received character.
158 -- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
159 -- a character is removed from the receive FIFO and "rxvalid", "rxflag" and "rxdata" are updated.
160 -- This signal has no effect if "rxvalid" is low.
161 -------------------------------------------------------------------------
162
163 -------------------------------------------------------------------------
164 -- STATUS
165 started => started, -- High if the link state machine is currently in the Started state.
166 connecting => connecting, -- High if the link state machine is currently in the Connecting state.
167 running => running, -- High if the link state machine is currently in the Run state, indicatin that the link is fully operational.
168 -- If none of started, connecting or running is high, the link is in an initial state and the transmitter is not yet enabled.
169
170 errdisc => errdisc, -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
171 errpar => errpar, -- Parity error detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
172 erresc => erresc, -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing.
173 errcred => errcred, -- Credit error detected. Triggers a reset and reconnect of the link. This indication is auto-clearing.
174 -------------------------------------------------------------------------
175
176 spw_di => spw_di, -- Data In signal from SpaceWire bus.
177 spw_si => spw_si, -- Strobe In signal from SpaceWire bus.
178 spw_do => spw_do, -- Data Out signal to SpaceWire bus.
179 spw_so => spw_so -- Strobe Out signal to SpaceWire bus.
180 );
181
182
183 spw_si <= spw_so;
184 spw_di <= spw_do;
185
186 spw_sender_1: spw_sender
187 GENERIC MAP (
188 FNAME => "spw_input.txt")
189 PORT MAP (
190 end_of_simu => OPEN,
191 start_of_simu => running,
192 clk => clk,
193
194 txwrite => txwrite,
195 txflag => txflag,
196 txdata => txdata,
197 txrdy => txrdy,
198 txhalff => txhalff);
199
200 spw_receiver_1: spw_receiver
201 GENERIC MAP (
202 FNAME => "spw_output.txt")
203 PORT MAP (
204 end_of_simu => '0',
205 timestamp => TSTAMP,
206 clk => clk,
207 rxread => rxread,
208 rxflag => rxflag,
209 rxdata => rxdata,
210 rxvalid => rxvalid,
211 rxhalff => rxhalff);
212
213 END;
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1 fft_components.vhd
1 fft_components.vhd
2 lpp_fft.vhd
2 lpp_fft.vhd
3 actar.vhd
3 actar.vhd
4 actram.vhd
4 actram.vhd
5 CoreFFT.vhd
5 CoreFFT.vhd
6 fftDp.vhd
6 fftDp.vhd
7 fftSm.vhd
7 fftSm.vhd
8 primitives.vhd
8 primitives.vhd
9 twiddle.vhd
9 twiddle.vhd
10 APB_FFT.vhd
10 APB_FFT.vhd
11 Driver_FFT.vhd
11 Driver_FFT.vhd
12 FFT.vhd
12 FFT.vhd
13 FFTamont.vhd
13 FFTamont.vhd
14 FFTaval.vhd
14 FFTaval.vhd
15 Flag_Extremum.vhd
15 Flag_Extremum.vhd
16 Linker_FFT.vhd
16 Linker_FFT.vhd
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1 lpp_cna.vhd
1 lpp_cna.vhd
2 APB_LFR_CAL.vhd
2 APB_LFR_CAL.vhd
3 RAM_READER.vhd
3 RAM_READER.vhd
4 RAM_WRITER.vhd
4 RAM_WRITER.vhd
5 SPI_DAC_DRIVER.vhd
5 SPI_DAC_DRIVER.vhd
6 dynamic_freq_div.vhd
6 dynamic_freq_div.vhd
7 lfr_cal_driver.vhd
7 lfr_cal_driver.vhd
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.libdcom.ALL;
29 USE gaisler.libdcom.ALL;
30 USE gaisler.sim.ALL;
30 USE gaisler.sim.ALL;
31 USE gaisler.jtagtst.ALL;
31 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.data_type_pkg.ALL;
36 USE lpp.data_type_pkg.ALL;
37
37
38 PACKAGE lpp_sim_pkg IS
38 PACKAGE lpp_sim_pkg IS
39
39
40 PROCEDURE UART_INIT (
40 PROCEDURE UART_INIT (
41 SIGNAL TX : OUT STD_LOGIC;
41 SIGNAL TX : OUT STD_LOGIC;
42 CONSTANT tx_period : IN TIME
42 CONSTANT tx_period : IN TIME
43 );
43 );
44 PROCEDURE UART_WRITE_ADDR32 (
44 PROCEDURE UART_WRITE_ADDR32 (
45 SIGNAL TX : OUT STD_LOGIC;
45 SIGNAL TX : OUT STD_LOGIC;
46 CONSTANT tx_period : IN TIME;
46 CONSTANT tx_period : IN TIME;
47 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
48 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
49 );
49 );
50 PROCEDURE UART_WRITE (
50 PROCEDURE UART_WRITE (
51 SIGNAL TX : OUT STD_LOGIC;
51 SIGNAL TX : OUT STD_LOGIC;
52 CONSTANT tx_period : IN TIME;
52 CONSTANT tx_period : IN TIME;
53 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
53 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
54 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
54 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 );
55 );
56 PROCEDURE UART_READ (
56 PROCEDURE UART_READ (
57 SIGNAL TX : OUT STD_LOGIC;
57 SIGNAL TX : OUT STD_LOGIC;
58 SIGNAL RX : IN STD_LOGIC;
58 SIGNAL RX : IN STD_LOGIC;
59 CONSTANT tx_period : IN TIME;
59 CONSTANT tx_period : IN TIME;
60 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
60 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
61 DATA : OUT STD_LOGIC_VECTOR
61 DATA : OUT STD_LOGIC_VECTOR
62 );
62 );
63
63
64 COMPONENT sig_reader IS
64 COMPONENT sig_reader IS
65 GENERIC(
65 GENERIC(
66 FNAME : STRING := "input.txt";
66 FNAME : STRING := "input.txt";
67 WIDTH : INTEGER := 1;
67 WIDTH : INTEGER := 1;
68 RESOLUTION : INTEGER := 8;
68 RESOLUTION : INTEGER := 8;
69 GAIN : REAL := 1.0
69 GAIN : REAL := 1.0
70 );
70 );
71 PORT(
71 PORT(
72 clk : IN std_logic;
72 clk : IN std_logic;
73 end_of_simu : out std_logic;
73 end_of_simu : out std_logic;
74 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
74 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
75 );
75 );
76 END COMPONENT;
76 END COMPONENT;
77
77
78 COMPONENT sig_recorder IS
78 COMPONENT sig_recorder IS
79 GENERIC(
79 GENERIC(
80 FNAME : STRING := "output.txt";
80 FNAME : STRING := "output.txt";
81 WIDTH : INTEGER := 1;
81 WIDTH : INTEGER := 1;
82 RESOLUTION : INTEGER := 8
82 RESOLUTION : INTEGER := 8
83 );
83 );
84 PORT(
84 PORT(
85 clk : IN STD_LOGIC;
85 clk : IN STD_LOGIC;
86 end_of_simu : IN STD_LOGIC;
86 end_of_simu : IN STD_LOGIC;
87 timestamp : IN INTEGER;
87 timestamp : IN INTEGER;
88 input_signal : IN sample_vector(0 TO WIDTH-1,RESOLUTION-1 DOWNTO 0)
88 input_signal : IN sample_vector(0 TO WIDTH-1,RESOLUTION-1 DOWNTO 0)
89 );
89 );
90 END COMPONENT;
90 END COMPONENT;
91
91
92 COMPONENT spw_sender IS
93 GENERIC (
94 FNAME : STRING);
95 PORT (
96 end_of_simu : OUT STD_LOGIC;
97 start_of_simu : IN STD_LOGIC;
98 clk : IN STD_LOGIC;
99 txwrite : OUT STD_LOGIC;
100 txflag : OUT STD_LOGIC;
101 txdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 txrdy : IN STD_LOGIC;
103 txhalff : IN STD_LOGIC);
104 END COMPONENT spw_sender;
105
106 COMPONENT spw_receiver IS
107 GENERIC (
108 FNAME : STRING);
109 PORT (
110 end_of_simu : IN STD_LOGIC;
111 timestamp : IN integer;
112 clk : IN STD_LOGIC;
113 rxread : OUT STD_LOGIC;
114 rxflag : in STD_LOGIC;
115 rxdata : in STD_LOGIC_VECTOR(7 DOWNTO 0);
116 rxvalid : in STD_LOGIC;
117 rxhalff : out STD_LOGIC);
118 END COMPONENT spw_receiver;
119
92 END lpp_sim_pkg;
120 END lpp_sim_pkg;
93
121
94 PACKAGE BODY lpp_sim_pkg IS
122 PACKAGE BODY lpp_sim_pkg IS
95
123
96 PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
124 PROCEDURE UART_INIT (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME) IS
97 BEGIN
125 BEGIN
98 txc(TX, 16#55#, tx_period);
126 txc(TX, 16#55#, tx_period);
99 END;
127 END;
100
128
101 PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
129 PROCEDURE UART_WRITE_ADDR32 (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
102 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
131 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
104 BEGIN
132 BEGIN
105 txc(TX, 16#c0#, tx_period);
133 txc(TX, 16#c0#, tx_period);
106 txa(TX,
134 txa(TX,
107 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
135 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
108 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
136 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
109 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
137 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
110 to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
138 to_integer(UNSIGNED(ADDR(7 DOWNTO 0))),
111 tx_period);
139 tx_period);
112 txa(TX,
140 txa(TX,
113 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
141 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
114 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
142 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
115 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
143 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
116 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
144 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
117 tx_period);
145 tx_period);
118 END;
146 END;
119
147
120 PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
148 PROCEDURE UART_WRITE (SIGNAL TX : OUT STD_LOGIC; CONSTANT tx_period : IN TIME;
121 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
149 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
122 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
150 CONSTANT DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0)) IS
123
151
124 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
152 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
125
153
126 BEGIN
154 BEGIN
127 txc(TX, 16#c0#, tx_period);
155 txc(TX, 16#c0#, tx_period);
128 txa(TX,
156 txa(TX,
129 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
157 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
130 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
158 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
131 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
159 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
132 to_integer(UNSIGNED(ADDR_last)),
160 to_integer(UNSIGNED(ADDR_last)),
133 tx_period);
161 tx_period);
134 txa(TX,
162 txa(TX,
135 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
163 to_integer(UNSIGNED(DATA(31 DOWNTO 24))),
136 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
164 to_integer(UNSIGNED(DATA(23 DOWNTO 16))),
137 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
165 to_integer(UNSIGNED(DATA(15 DOWNTO 8))),
138 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
166 to_integer(UNSIGNED(DATA(7 DOWNTO 0))),
139 tx_period);
167 tx_period);
140 END;
168 END;
141
169
142 PROCEDURE UART_READ (
170 PROCEDURE UART_READ (
143 SIGNAL TX : OUT STD_LOGIC;
171 SIGNAL TX : OUT STD_LOGIC;
144 SIGNAL RX : IN STD_LOGIC;
172 SIGNAL RX : IN STD_LOGIC;
145 CONSTANT tx_period : IN TIME;
173 CONSTANT tx_period : IN TIME;
146 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
174 CONSTANT ADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 2);
147 DATA : OUT STD_LOGIC_VECTOR )
175 DATA : OUT STD_LOGIC_VECTOR )
148 IS
176 IS
149 VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
177 VARIABLE V_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
150 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
178 CONSTANT ADDR_last : STD_LOGIC_VECTOR(7 DOWNTO 0) := ADDR(7 DOWNTO 2) & "00";
151 BEGIN
179 BEGIN
152 txc(TX, 16#80#, tx_period);
180 txc(TX, 16#80#, tx_period);
153 txa(TX,
181 txa(TX,
154 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
182 to_integer(UNSIGNED(ADDR(31 DOWNTO 24))),
155 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
183 to_integer(UNSIGNED(ADDR(23 DOWNTO 16))),
156 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
184 to_integer(UNSIGNED(ADDR(15 DOWNTO 8))),
157 to_integer(UNSIGNED(ADDR_last)),
185 to_integer(UNSIGNED(ADDR_last)),
158 tx_period);
186 tx_period);
159 rxc(RX,V_DATA,tx_period);
187 rxc(RX,V_DATA,tx_period);
160 DATA(31 DOWNTO 24) := V_DATA;
188 DATA(31 DOWNTO 24) := V_DATA;
161 rxc(RX,V_DATA,tx_period);
189 rxc(RX,V_DATA,tx_period);
162 DATA(23 DOWNTO 16) := V_DATA;
190 DATA(23 DOWNTO 16) := V_DATA;
163 rxc(RX,V_DATA,tx_period);
191 rxc(RX,V_DATA,tx_period);
164 DATA(15 DOWNTO 8) := V_DATA;
192 DATA(15 DOWNTO 8) := V_DATA;
165 rxc(RX,V_DATA,tx_period);
193 rxc(RX,V_DATA,tx_period);
166 DATA(7 DOWNTO 0) := V_DATA;
194 DATA(7 DOWNTO 0) := V_DATA;
167 END;
195 END;
168
196
169 END lpp_sim_pkg;
197 END lpp_sim_pkg;
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@@ -1,5 +1,7
1 lpp_sim_pkg.vhd
1 lpp_sim_pkg.vhd
2 sig_reader.vhd
2 sig_reader.vhd
3 sig_recorder.vhd
3 sig_recorder.vhd
4 lpp_sim_pkg.vhd
4 lpp_sim_pkg.vhd
5 lpp_lfr_sim_pkg.vhd
5 lpp_lfr_sim_pkg.vhd
6 spw_sender.vhd
7 spw_receiver.vhd
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1 NO CONTENT: file was removed
NO CONTENT: file was removed
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