diff --git a/lib/lpp/dsp/lpp_fft_rtax/vhdlsim.txt b/lib/lpp/dsp/lpp_fft_rtax/vhdlsim.txt deleted file mode 100644 diff --git a/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt b/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt --- a/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt +++ b/lib/lpp/dsp/lpp_fft_rtax/vhdlsyn.txt @@ -1,16 +1,16 @@ -fft_components.vhd -lpp_fft.vhd -actar.vhd -actram.vhd -CoreFFT.vhd -fftDp.vhd -fftSm.vhd -primitives.vhd -twiddle.vhd -APB_FFT.vhd -Driver_FFT.vhd -FFT.vhd -FFTamont.vhd -FFTaval.vhd -Flag_Extremum.vhd -Linker_FFT.vhd +fft_components.vhd +lpp_fft.vhd +actar.vhd +actram.vhd +CoreFFT.vhd +fftDp.vhd +fftSm.vhd +primitives.vhd +twiddle.vhd +APB_FFT.vhd +Driver_FFT.vhd +FFT.vhd +FFTamont.vhd +FFTaval.vhd +Flag_Extremum.vhd +Linker_FFT.vhd diff --git a/lib/lpp/lpp_cna/vhdlsyn.txt b/lib/lpp/lpp_cna/vhdlsyn.txt --- a/lib/lpp/lpp_cna/vhdlsyn.txt +++ b/lib/lpp/lpp_cna/vhdlsyn.txt @@ -1,7 +1,7 @@ -lpp_cna.vhd -APB_LFR_CAL.vhd -RAM_READER.vhd -RAM_WRITER.vhd -SPI_DAC_DRIVER.vhd -dynamic_freq_div.vhd -lfr_cal_driver.vhd +lpp_cna.vhd +APB_LFR_CAL.vhd +RAM_READER.vhd +RAM_WRITER.vhd +SPI_DAC_DRIVER.vhd +dynamic_freq_div.vhd +lfr_cal_driver.vhd diff --git a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd --- a/lib/lpp/lpp_sim/lpp_sim_pkg.vhd +++ b/lib/lpp/lpp_sim/lpp_sim_pkg.vhd @@ -89,6 +89,34 @@ PACKAGE lpp_sim_pkg IS ); END COMPONENT; + COMPONENT spw_sender IS + GENERIC ( + FNAME : STRING); + PORT ( + end_of_simu : OUT STD_LOGIC; + start_of_simu : IN STD_LOGIC; + clk : IN STD_LOGIC; + txwrite : OUT STD_LOGIC; + txflag : OUT STD_LOGIC; + txdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txrdy : IN STD_LOGIC; + txhalff : IN STD_LOGIC); + END COMPONENT spw_sender; + + COMPONENT spw_receiver IS + GENERIC ( + FNAME : STRING); + PORT ( + end_of_simu : IN STD_LOGIC; + timestamp : IN integer; + clk : IN STD_LOGIC; + rxread : OUT STD_LOGIC; + rxflag : in STD_LOGIC; + rxdata : in STD_LOGIC_VECTOR(7 DOWNTO 0); + rxvalid : in STD_LOGIC; + rxhalff : out STD_LOGIC); + END COMPONENT spw_receiver; + END lpp_sim_pkg; PACKAGE BODY lpp_sim_pkg IS diff --git a/lib/lpp/lpp_sim/spw_receiver.vhd b/lib/lpp/lpp_sim/spw_receiver.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/spw_receiver.vhd @@ -0,0 +1,82 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +USE std.textio.ALL; + +ENTITY spw_receiver IS + GENERIC( + FNAME : STRING := "output.txt" + ); + PORT( + end_of_simu : IN STD_LOGIC; + timestamp : IN integer; + + clk : IN STD_LOGIC; + + rxread : out STD_LOGIC; + rxflag : in STD_LOGIC; + rxdata : in STD_LOGIC_VECTOR(7 DOWNTO 0); + rxvalid : in STD_LOGIC; + rxhalff : out STD_LOGIC + ); +END spw_receiver; + +ARCHITECTURE beh OF spw_receiver IS + + FILE output_file : TEXT OPEN write_mode IS FNAME; + + SIGNAL message_ongoing : STD_LOGIC := '0'; + SIGNAL message_timestamp : INTEGER; + +BEGIN + ----------------------------------------------------------------------------- + -- Data orginization in the output file : + ----------------------------------------------------------------------------- + -- Exemple of output.txt file : + -- Data_1 + -- Data_2 + -- ... + -- Data_N + -- TIME= TimeStamp_when_Data_1_was_received + -- Data_N+1 + -- Data_N+2 + -- ... + -- Data_M + -- TIME= TimeStamp_when_Data_N+1_was_received + -- Data_M+1 + -- Data_M+2 + -- ... + -- Data_K + -- TIME= TimeStamp_when_Data_M+1_was_received + ----------------------------------------------------------------------------- + -- TimeStamp : integer. Waiting time (in ns) before to send the following message + -- Data : integer(0 to 255). A part of the message. + ----------------------------------------------------------------------------- + + PROCESS(clk,end_of_simu) + VARIABLE line_var : LINE; + BEGIN + IF end_of_simu = '1' THEN + file_close(output_file); + rxread <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + rxread <= '1'; + IF rxvalid = '1' THEN + IF rxflag = '1' THEN + write(line_var, "TIME= " & INTEGER'IMAGE(message_timestamp)); + message_ongoing <= '0'; + ELSE + IF message_ongoing = '0' THEN + message_ongoing <= '1'; + message_timestamp <= TimeStamp; + END IF; + write(line_var, INTEGER'IMAGE(to_integer(UNSIGNED(rxdata)))); + END IF; + writeline(output_file, line_var); + END IF; + END IF; + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_sim/spw_sender.vhd b/lib/lpp/lpp_sim/spw_sender.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_sim/spw_sender.vhd @@ -0,0 +1,97 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY std; +USE std.textio.ALL; + +ENTITY spw_sender IS + GENERIC( + FNAME : STRING := "input.txt" + ); + PORT( + end_of_simu : OUT STD_LOGIC; + start_of_simu : IN STD_LOGIC; + + clk : IN STD_LOGIC; + txwrite : OUT STD_LOGIC; + txflag : OUT STD_LOGIC; + txdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + txrdy : IN STD_LOGIC; + txhalff : IN STD_LOGIC + ); +END spw_sender; + +ARCHITECTURE beh OF spw_sender IS + FILE input_file : TEXT OPEN read_mode IS FNAME; + +BEGIN + ----------------------------------------------------------------------------- + -- Data orginization in the input file : + ----------------------------------------------------------------------------- + -- Exemple of input.txt file : + -- Time1 N1 + -- Data_1 + -- Data_2 + -- ... + -- Data_N1 + -- Time2 N2 + -- Data_1 + -- Data_2 + -- ... + -- Data_N2 + -- ... + -- TimeK NK + -- Data_1 + -- Data_2 + -- ... + -- Data_NK + ----------------------------------------------------------------------------- + -- Time : integer. Waiting time (in ns) before to send the following message + -- N : integer. Length (in Byte) of the following message. + -- Data : integer(0 to 255). A part of the message. + ----------------------------------------------------------------------------- + + PROCESS IS + VARIABLE line_var : LINE; + VARIABLE waiting_time : INTEGER; + VARIABLE length_of_message : INTEGER; + VARIABLE value : INTEGER; + BEGIN -- PROCESS + txwrite <= '0'; + txflag <= '0'; + WAIT UNTIL clk = '1'; + IF start_of_simu = '1' THEN + + IF endfile(input_file) THEN + end_of_simu <= '1'; + ELSE + end_of_simu <= '0'; + readline(input_file, line_var); + read(line_var, waiting_time); + read(line_var, length_of_message); + + WAIT FOR waiting_time * 1 ns; + + FOR char_number IN 0 TO length_of_message-1 LOOP + WAIT UNTIL clk = '1' AND txrdy = '1'; + readline(input_file, line_var); + read(line_var, value); + txwrite <= '1'; + txflag <= '0'; + txdata <= STD_LOGIC_VECTOR(to_unsigned(value, txdata'LENGTH)); + END LOOP; -- char_number + WAIT UNTIL clk = '1' AND txrdy = '1'; + txwrite <= '1'; + txflag <= '1'; + txdata <= (OTHERS => '0'); + WAIT UNTIL clk = '1'; + txwrite <= '0'; + txflag <= '0'; + + END IF; + END IF; + + END PROCESS; + +END beh; diff --git a/lib/lpp/lpp_sim/vhdlsim.txt b/lib/lpp/lpp_sim/vhdlsim.txt --- a/lib/lpp/lpp_sim/vhdlsim.txt +++ b/lib/lpp/lpp_sim/vhdlsim.txt @@ -3,3 +3,5 @@ sig_reader.vhd sig_recorder.vhd lpp_sim_pkg.vhd lpp_lfr_sim_pkg.vhd +spw_sender.vhd +spw_receiver.vhd diff --git a/tests/Validation_SPW_light/Makefile b/tests/Validation_SPW_light/Makefile new file mode 100644 --- /dev/null +++ b/tests/Validation_SPW_light/Makefile @@ -0,0 +1,53 @@ +VHDLIB=../.. +SCRIPTSDIR=$(VHDLIB)/scripts/ +GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh) +TOP=testbench +BOARD=LFR-FM +include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc +DEVICE=$(PART)-$(PACKAGE)$(SPEED) +UCF= +QSF= +EFFORT=high +XSTOPT= +SYNPOPT= +VHDLSYNFILES= +VHDLSIMFILES= $(VHDLIB)/designs/SOLO_LFR_LFR-FM/LFR-FM.vhd tb.vhd +SIMTOP=testbench +CLEAN=soft-clean + +TECHLIBS = axcelerator + + +LIBSKIP = tmtc openchip hynix cypress ihp usbhc fmf gsi spansion eth micron + +DIRSKIP = leon2 leon2ft crypto usb satcan ddr greth grusbhc \ + leon4 leon4v0 l2cache iommu slink ascs pwm net spi can \ + ./amba_lcd_16x2_ctrlr \ + ./general_purpose/lpp_AMR \ + ./general_purpose/lpp_balise \ + ./general_purpose/lpp_delay \ + ./lpp_bootloader \ + ./lpp_uart \ + ./lpp_usb \ + ./lpp_debug_lfr \ + ./dsp/lpp_fft + +FILESKIP = i2cmst.vhd \ + APB_MULTI_DIODE.vhd \ + APB_MULTI_DIODE.vhd \ + Top_MatrixSpec.vhd \ + APB_FFT.vhd \ + lpp_lfr_sim_pkg.vhd + +include $(GRLIB)/bin/Makefile +include $(GRLIB)/software/leon3/Makefile +################## project specific targets ########################## +distclean:myclean + +myclean: + rm -f input.txt output_fx.txt *.log + rm -rf ./2016* + +test: | ghdl ghdl-run archivate + + diff --git a/tests/Validation_SPW_light/spw_input.txt b/tests/Validation_SPW_light/spw_input.txt new file mode 100644 --- /dev/null +++ b/tests/Validation_SPW_light/spw_input.txt @@ -0,0 +1,7 @@ +20 3 +28 +14 +32 +1500 2 +18 +200 diff --git a/tests/Validation_SPW_light/spw_output.txt b/tests/Validation_SPW_light/spw_output.txt new file mode 100644 --- /dev/null +++ b/tests/Validation_SPW_light/spw_output.txt @@ -0,0 +1,7 @@ +28 +14 +32 +TIME= 45020 +18 +200 +TIME= 47660 diff --git a/tests/Validation_SPW_light/tb.vhd b/tests/Validation_SPW_light/tb.vhd new file mode 100644 --- /dev/null +++ b/tests/Validation_SPW_light/tb.vhd @@ -0,0 +1,213 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +USE IEEE.std_logic_signed.ALL; +USE IEEE.MATH_real.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY std; +USE std.textio.ALL; + +LIBRARY opencores; +USE opencores.spwpkg.ALL; +USE opencores.spwambapkg.ALL; + +LIBRARY lpp; +USE lpp.lpp_sim_pkg.ALL; + +ENTITY testbench IS +END; + +ARCHITECTURE behav OF testbench IS + + SIGNAL TSTAMP : INTEGER := 0; + SIGNAL clk : STD_LOGIC := '0'; + SIGNAL rst : STD_LOGIC; + + SIGNAL end_of_simu : STD_LOGIC := '0'; + + SIGNAL autostart : STD_LOGIC := '1'; + SIGNAL linkstart : STD_LOGIC := '1'; + SIGNAL linkdis : STD_LOGIC := '0'; + SIGNAL ctrl_in : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0'); + SIGNAL time_in : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0'); + SIGNAL txwrite : STD_LOGIC := '0'; + SIGNAL txflag : STD_LOGIC := '0'; + SIGNAL txdata : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL txrdy : STD_LOGIC; + SIGNAL txhalff : STD_LOGIC; + SIGNAL tick_out : STD_LOGIC; + SIGNAL ctrl_out : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_out : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL rxvalid : STD_LOGIC; + SIGNAL rxhalff : STD_LOGIC; + SIGNAL rxflag : STD_LOGIC; + SIGNAL rxdata : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL rxread : STD_LOGIC := '0'; + SIGNAL started : STD_LOGIC; + SIGNAL connecting : STD_LOGIC; + SIGNAL running : STD_LOGIC; + SIGNAL errdisc : STD_LOGIC; + SIGNAL errpar : STD_LOGIC; + SIGNAL erresc : STD_LOGIC; + SIGNAL errcred : STD_LOGIC; + + SIGNAL spw_di : std_logic; + SIGNAL spw_si : std_logic; + SIGNAL spw_do : std_logic; + SIGNAL spw_so : std_logic; + +BEGIN + + ----------------------------------------------------------------------------- + -- CLOCK and RESET + ----------------------------------------------------------------------------- + PROCESS + BEGIN -- PROCESS + WAIT UNTIL clk = '1'; + rst <= '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + WAIT UNTIL clk = '1'; + rst <= '0'; + WAIT UNTIL end_of_simu = '1'; + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + -- Wait forever; this will finish the simulation. + WAIT; + END PROCESS; + ----------------------------------------------------------------------------- + + clk_50M_gen : PROCESS + BEGIN + IF end_of_simu /= '1' THEN + clk <= NOT clk; + TSTAMP <= TSTAMP+20; + WAIT FOR 10 ns; + ELSE + WAIT FOR 10 ps; + ASSERT false REPORT "end of test" SEVERITY note; + WAIT; + END IF; + END PROCESS; + + + SPW : spwstream + + GENERIC MAP( + sysfreq => 50.0e6, + txclkfreq => 50.0e6, + rximpl => impl_generic, + rxchunk => 1, + tximpl => impl_generic, + rxfifosize_bits => 11, + txfifosize_bits => 11 + ) + + PORT MAP( + -- System clock. + clk => clk, + rxclk => clk, + txclk => clk, + rst => rst, + + + autostart => autostart, -- Enables automatic link start on receipt of a NULL character. + linkstart => linkstart, -- Enables link start once the Ready state is reached. Without autostart or linkstart, the link remains in state Ready. + linkdis => linkdis, -- Do not start link (overrides linkstart and autostart) and/or disconnect a running link. + + txdivcnt => X"00", + + + ------------------------------------------------------------------------- + -- TimeCode transmission + tick_in => '0', -- High for one clock cycle to request transmission of a TimeCode. The request is registered inside the entity until it can be processed. + ctrl_in => ctrl_in, -- Control bits of the TimeCode to be sent. Must be valid while tick_in is high. + time_in => time_in, -- Counter value of the TimeCode to be sent. Must be valid while tick_in is high. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- ### tx data ### tb -> SPW-light + txwrite => txwrite, -- Pulled high by the application to write an N-Char to the transmit queue. + -- If "txwrite" and "txrdy" are both high on the rising edge of "clk", a character is added to the transmit queue. + -- This signal has no effect if "txrdy" is low. + txflag => txflag, -- Control flag to be sent with the next N_Char. Must be valid while txwrite is high. + txdata => txdata, -- Byte to be sent, or "00000000" for EOP or "00000001" for EEP. Must be valid while txwrite is high. + txrdy => txrdy, -- High if the entity is ready to accept an N-Char for transmission. + txhalff => txhalff, -- High if the transmission queue is at least half full. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- TimeCode reception + tick_out => tick_out, -- High for one clock cycle if a TimeCode was just received. + ctrl_out => ctrl_out, -- Control bits of the last received TimeCode. + time_out => time_out, -- Counter value of the last received TimeCode. + ------------------------------------------------------------------------- + + + ------------------------------------------------------------------------- + -- ### rx data ### tb <- SPW-light + rxvalid => rxvalid, -- High if "rxflag" and "rxdata" contain valid data. This signal is high unless the receive FIFO is empty. + rxhalff => rxhalff, -- High if the receive FIFO is at least half full. + rxflag => rxflag, -- High if the received character is EOP or EEP; low if the received character is a data byte. Valid if "rxvalid" is high. + rxdata => rxdata, -- Received byte, or "00000000" for EOP or "00000001" for EEP. Valid if "rxvalid" is high. + rxread => rxread, -- Pulled high by the application to accept a received character. + -- If "rxvalid" and "rxread" are both high on the rising edge of "clk", + -- a character is removed from the receive FIFO and "rxvalid", "rxflag" and "rxdata" are updated. + -- This signal has no effect if "rxvalid" is low. + ------------------------------------------------------------------------- + + ------------------------------------------------------------------------- + -- STATUS + started => started, -- High if the link state machine is currently in the Started state. + connecting => connecting, -- High if the link state machine is currently in the Connecting state. + running => running, -- High if the link state machine is currently in the Run state, indicatin that the link is fully operational. + -- If none of started, connecting or running is high, the link is in an initial state and the transmitter is not yet enabled. + + errdisc => errdisc, -- Disconnect detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + errpar => errpar, -- Parity error detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + erresc => erresc, -- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of the link. This indication is auto-clearing. + errcred => errcred, -- Credit error detected. Triggers a reset and reconnect of the link. This indication is auto-clearing. + ------------------------------------------------------------------------- + + spw_di => spw_di, -- Data In signal from SpaceWire bus. + spw_si => spw_si, -- Strobe In signal from SpaceWire bus. + spw_do => spw_do, -- Data Out signal to SpaceWire bus. + spw_so => spw_so -- Strobe Out signal to SpaceWire bus. + ); + + + spw_si <= spw_so; + spw_di <= spw_do; + + spw_sender_1: spw_sender + GENERIC MAP ( + FNAME => "spw_input.txt") + PORT MAP ( + end_of_simu => OPEN, + start_of_simu => running, + clk => clk, + + txwrite => txwrite, + txflag => txflag, + txdata => txdata, + txrdy => txrdy, + txhalff => txhalff); + + spw_receiver_1: spw_receiver + GENERIC MAP ( + FNAME => "spw_output.txt") + PORT MAP ( + end_of_simu => '0', + timestamp => TSTAMP, + clk => clk, + rxread => rxread, + rxflag => rxflag, + rxdata => rxdata, + rxvalid => rxvalid, + rxhalff => rxhalff); + +END;