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Débug de la FIFO...
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1 -- FFTamont.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTamont is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Load : in std_logic;
14 Empty : in std_logic;
15 Full : in std_logic;
16 DATA : in std_logic_vector(Data_sz-1 downto 0);
17 Valid : out std_logic;
18 Read : out std_logic;
19 Data_re : out std_logic_vector(Data_sz-1 downto 0);
20 Data_im : out std_logic_vector(Data_sz-1 downto 0)
21 );
22 end entity;
23
24
25 architecture ar_FFTamont of FFTamont is
26
27 type etat is (eX,e0,e1,e2);
28 signal ect : etat;
29
30
31 begin
32
33 process(clk,rstn)
34 begin
35 if(rstn='0')then
36 ect <= eX;
37 Read <= '1';
38 Valid <= '0';
39 Data_re <= (others => '0');
40 Data_im <= (others => '0');
41
42 elsif(clk'event and clk='1')then
43
44 case ect is
45
46 when eX =>
47 if(Full='1')then
48 ect <= e0;
49 end if;
50
51 when e0 =>
52 Valid <= '0';
53 if(Load='1' and Empty='0')then
54 Read <= '0';
55 ect <= e1;
56 elsif(Empty='1')then
57 ect <= eX;
58 end if;
59
60 when e1 =>
61 Read <= '1';
62 Data_re <= DATA;
63 Data_im <= (others => '0');
64 Valid <= '1';
65 ect <= e0;
66
67 when e2 =>
68 null;
69
70 end case;
71 end if;
72 end process;
73
74 end architecture;
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1 -- FFTaval.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity FFTaval is
7 generic(
8 Data_sz : integer range 1 to 32 := 8
9 );
10 port(
11 clk : in std_logic;
12 rstn : in std_logic;
13 Ready : in std_logic;
14 Valid : in std_logic;
15 Full : in std_logic;
16 Data_re : in std_logic_vector(Data_sz-1 downto 0);
17 Data_im : in std_logic_vector(Data_sz-1 downto 0);
18 Read : out std_logic;
19 Write : out std_logic;
20 ReUse : out std_logic;
21 DATA : out std_logic_vector(Data_sz-1 downto 0)
22 );
23 end entity;
24
25
26 architecture ar_FFTaval of FFTaval is
27
28 type etat is (eX,e0,e1,e2,e3);
29 signal ect : etat;
30
31 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
32
33 signal sReady : std_logic;
34
35 begin
36
37 process(clk,rstn)
38 begin
39 if(rstn='0')then
40 ect <= e0;
41 Read <= '0';
42 Write <= '1';
43 Reuse <= '0';
44
45 elsif(clk'event and clk='1')then
46 sReady <= Ready;
47
48 case ect is
49
50 when e0 =>
51 Write <= '1';
52 if(sReady='0' and Ready='1' and full='0')then
53 Read <= '1';
54 ect <= e1;
55 end if;
56
57 when e1 =>
58 Read <= '0';
59 if(Valid='1' and full='0')then
60 DataTmp <= Data_im;
61 DATA <= Data_re;
62 Write <= '0';
63 ect <= e2;
64 elsif(full='1')then
65 ReUse <= '1';
66 ect <= e0;
67 end if;
68
69 when e2 =>
70 DATA <= DataTmp;
71 ect <= e3;
72
73 when e3 =>
74 Write <= '1';
75 if(Ready='1' and full='0')then
76 Read <= '1';
77 ect <= e1;
78 end if;
79
80 when eX =>
81 null;
82
83 end case;
84 end if;
85 end process;
86
87
88
89 end architecture;
90
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25 use lpp.lpp_matrix.all;
26
27 entity Dispatch is
28 generic(
29 Data_SZ : integer := 32);
30 port(
31 clk : in std_logic;
32 reset : in std_logic;
33 Acq : in std_logic;
34 Data : in std_logic_vector(Data_SZ-1 downto 0);
35 Write : in std_logic;
36 Full : in std_logic_vector(1 downto 0);
37 -- Empty : in std_logic_vector(1 downto 0);
38 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
39 FifoWrite : out std_logic_vector(1 downto 0);
40 -- FifoFull : out std_logic;
41 Pong : out std_logic;
42 Error : out std_logic
43
44 );
45 end entity;
46
47
48 architecture ar_Dispatch of Dispatch is
49
50 type etat is (e0,e1,e2,e3);
51 signal ect : etat;
52
53 begin
54
55 process (clk,reset)
56 begin
57 if(reset='0')then
58 Pong <= '0';
59 Error <= '0';
60
61 elsif(clk' event and clk='1')then
62
63 case ect is
64
65 when e0 =>
66 if(Full(0) = '1')then
67 pong <= '1';
68 ect <= e1;
69 end if;
70
71 when e1 =>
72 if(Acq <= '1')then
73 Error <= '0';
74 pong <= '0';
75 ect <= e2;
76 else
77 Error <= '1';
78 ect <= e1;
79 end if;
80
81 when e2 =>
82 if(Full(1) = '1')then
83 pong <= '1';
84 ect <= e3;
85 end if;
86
87 when e3 =>
88 if(Acq <= '1')then
89 Error <= '0';
90 pong <= '0';
91 ect <= e0;
92 else
93 Error <= '1';
94 ect <= e3;
95 end if;
96
97 end case;
98
99 end if;
100 end process;
101
102 FifoData <= Data & Data;
103
104 with ect select
105 FifoWrite <= '1' & not Write when e0,
106 not Write & '1' when e2,
107 "11" when others;
108
109 end architecture; No newline at end of file
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1 -- Bridge.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 entity Bridge is
7 generic(
8 Data_sz : integer range 1 to 32 := 16
9 );
10 port(
11 clk : in std_logic;
12 raz : in std_logic;
13 Start : in std_logic;
14 FullUp : in std_logic;
15 EmptyUp : in std_logic;
16 FullDown : in std_logic;
17 EmptyDown : in std_logic;
18 Write : out std_logic;
19 Read : out std_logic
20 );
21 end entity;
22
23
24 architecture ar_Bridge of Bridge is
25
26 type etat is (eX,e1,e2,e3);
27 signal ect : etat;
28
29 signal i : integer;
30
31 begin
32
33 process(clk,raz)
34 begin
35 if(raz='0')then
36 Write <= '1';
37 Read <= '1';
38 i <= 0;
39 ect <= eX;
40
41 elsif(clk'event and clk='1')then
42
43 case ect is
44
45 when eX =>
46 if(FullUp='1' and EmptyDown='1' and start='0')then
47 ect <= e1;
48 end if;
49
50 when e1 =>
51 Write <= '1';
52 if(EmptyUp='0')then
53 Read <= '0';
54 ect <= e2;
55 else
56 Read <= '1';
57 ect <= e3;
58 end if;
59
60 when e2 =>
61 Read <= '1';
62 if(FullDown='0')then
63 Write <= '0';
64 ect <= e1;
65 else
66 Write <= '1';
67 ect <= e3;
68 end if;
69
70 when e3 =>
71 null;
72
73 end case;
74 end if;
75 end process;
76
77
78 end architecture; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity lppFIFOx5 is
31 generic(
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
34 Enable_ReUse : std_logic := '0'
35 );
36 port(
37 rst : in std_logic;
38 wclk : in std_logic;
39 rclk : in std_logic;
40 ReUse : in std_logic_vector(4 downto 0);
41 wen : in std_logic_vector(4 downto 0);
42 ren : in std_logic_vector(4 downto 0);
43 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
44 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
45 full : out std_logic_vector(4 downto 0);
46 empty : out std_logic_vector(4 downto 0)
47 );
48 end entity;
49
50
51 architecture ar_lppFIFOx5 of lppFIFOx5 is
52
53 begin
54
55 fifoB1 : entity work.lpp_fifo
56 generic map (tech,Enable_ReUse,Data_sz,8)
57 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
58
59 fifoB2 : entity work.lpp_fifo
60 generic map (tech,Enable_ReUse,Data_sz,8)
61 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
62
63 fifoB3 : entity work.lpp_fifo
64 generic map (tech,Enable_ReUse,Data_sz,8)
65 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
66
67 fifoE1 : entity work.lpp_fifo
68 generic map (tech,Enable_ReUse,Data_sz,8)
69 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
70
71 fifoE2 : entity work.lpp_fifo
72 generic map (tech,Enable_ReUse,Data_sz,8)
73 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
74
75
76 end architecture;
77
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26
27 27 package FILTERcfg is
28 28
29 29
30 30
31 31
32 32 --===========================================================|
33 33 --========F I L T E R C O N F I G V A L U E S=============|
34 34 --===========================================================|
35 35 --____________________________
36 36 --Bus Width and chanels number|
37 37 --____________________________|
38 38 constant ChanelsCount : integer := 1;
39 constant Sample_SZ : integer := 20;
39 constant Sample_SZ : integer := 18;
40 40 constant Coef_SZ : integer := 9;
41 41 constant CoefCntPerCel: integer := 6;
42 42 constant Cels_count : integer := 5;
43 43 constant virgPos : integer := 7;
44 44 constant Mem_use : integer := 1;
45 45
46 46
47 47
48 48 --============================================================
49 49 -- create each initial values for each coefs ============
50 50 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
51 51 --============================================================
52 52 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
53 53 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
54 54 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
55 55
56 56 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
57 57 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
58 58 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
59 59
60 60 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
61 61 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
62 62 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
63 63
64 64 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
65 65 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
66 66 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
67 67
68 68 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
69 69 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
70 70 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
71 71
72 72 constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
73 73 constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
74 74 constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
75 75
76 76 constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
77 77 constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
78 78 constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
79 79
80 80
81 81 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
82 82 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
83 83 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
84 84
85 85 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
86 86 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
87 87 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
88 88
89 89 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
90 90 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
91 91 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
92 92
93 93 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
94 94 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
95 95 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
96 96
97 97 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
98 98 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
99 99 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
100 100
101 101 constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
102 102 constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
103 103 constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
104 104 constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
105 105 constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
106 106 constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
107 107
108 108 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
109 109
110 110
111 111 end;
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@@ -1,93 +1,93
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity RAM_CEL is
27 port( WD : in std_logic_vector(35 downto 0); RD : out
28 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
27 port( WD : in std_logic_vector(15 downto 0); RD : out
28 std_logic_vector(15 downto 0);WEN, REN : in std_logic;
29 29 WADDR : in std_logic_vector(7 downto 0); RADDR : in
30 30 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
31 31 ) ;
32 32 end RAM_CEL;
33 33
34 34
35 35
36 36 architecture ar_RAM_CEL of RAM_CEL is
37 type RAMarrayT is array (0 to 255) of std_logic_vector(35 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"000000000");
39 signal RD_int : std_logic_vector(35 downto 0);
37 type RAMarrayT is array (0 to 255) of std_logic_vector(15 downto 0);
38 signal RAMarray : RAMarrayT:=(others => X"0000");
39 signal RD_int : std_logic_vector(15 downto 0);
40 40
41 41 begin
42 42
43 43 RD_int <= RAMarray(to_integer(unsigned(RADDR)));
44 44
45 45
46 46 process(RWclk,reset)
47 47 begin
48 48 if reset = '0' then
49 RD <= (X"000000000");
49 RD <= (X"0000");
50 50 rst:for i in 0 to 255 loop
51 51 RAMarray(i) <= (others => '0');
52 52 end loop;
53 53
54 54 elsif RWclk'event and RWclk = '1' then
55 55 if REN = '0' then
56 56 RD <= RD_int;
57 57 end if;
58 58
59 59 if WEN = '0' then
60 60 RAMarray(to_integer(unsigned(WADDR))) <= WD;
61 61 end if;
62 62
63 63 end if;
64 64 end process;
65 65 end ar_RAM_CEL;
66 66
67 67
68 68
69 69
70 70
71 71
72 72
73 73
74 74
75 75
76 76
77 77
78 78
79 79
80 80
81 81
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83 83
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85 85
86 86
87 87
88 88
89 89
90 90
91 91
92 92
93 93
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@@ -1,225 +1,242
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 library lpp;
26 26 use lpp.iir_filter.all;
27 27 use lpp.FILTERcfg.all;
28 28 use lpp.general_purpose.all;
29 29 library techmap;
30 30 use techmap.gencomp.all;
31 31
32 32 --TODO amliorer la flexibilit de la config de la RAM.
33 33
34 34 entity RAM_CTRLR2 is
35 35 generic(
36 36 tech : integer := 0;
37 37 Input_SZ_1 : integer := 16;
38 38 Mem_use : integer := use_RAM
39 39
40 40 );
41 41 port(
42 42 reset : in std_logic;
43 43 clk : in std_logic;
44 44 WD_sel : in std_logic;
45 45 Read : in std_logic;
46 46 WADDR_sel : in std_logic;
47 47 count : in std_logic;
48 48 SVG_ADDR : in std_logic;
49 49 Write : in std_logic;
50 50 GO_0 : in std_logic;
51 51 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
52 52 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
53 53 );
54 54 end RAM_CTRLR2;
55 55
56 56
57 57 architecture ar_RAM_CTRLR2 of RAM_CTRLR2 is
58 58
59 59 signal WD : std_logic_vector(Input_SZ_1-1 downto 0);
60 60 signal WD_D : std_logic_vector(Input_SZ_1-1 downto 0);
61 61 signal RD : std_logic_vector(Input_SZ_1-1 downto 0);
62 62 signal WEN, REN : std_logic;
63 63 signal WADDR_back : std_logic_vector(7 downto 0);
64 64 signal WADDR_back_D: std_logic_vector(7 downto 0);
65 65 signal RADDR : std_logic_vector(7 downto 0);
66 66 signal WADDR : std_logic_vector(7 downto 0);
67 67 signal WADDR_D : std_logic_vector(7 downto 0);
68 68
69
69 SIGNAL WADDR_back_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
70 70
71 71 begin
72 72
73 73 sample_out <= RD(Input_SZ_1-1 downto 0);
74 74
75 75
76 76 WEN <= not Write;
77 77 REN <= not read;
78 78
79 79
80 80 --==============================================================
81 81 --=========================R A M================================
82 82 --==============================================================
83 83 --memRAM : if (Mem_use = use_RAM or Mem_use = use_CEL)generate
84 84 --RAMblk : entity work.RAM
85 85 -- generic map
86 86 -- (
87 87 -- Input_SZ_1
88 88 -- )
89 89 -- port map(
90 90 -- WD => WD_D,
91 91 -- RD => RD,
92 92 -- WEN => WEN,
93 93 -- REN => REN,
94 94 -- WADDR => WADDR,
95 95 -- RADDR => RADDR,
96 96 -- RWCLK => clk,
97 97 -- RESET => reset
98 98 -- ) ;
99 99 --end generate;
100 100
101 101 --memCEL : if Mem_use = use_CEL generate
102 102 --RAMblk :RAM_CEL
103 103 -- port map(
104 104 -- WD => WD_D,
105 105 -- RD => RD,
106 106 -- WEN => WEN,
107 107 -- REN => REN,
108 108 -- WADDR => WADDR,
109 109 -- RADDR => RADDR,
110 110 -- RWCLK => clk,
111 111 -- RESET => reset
112 112 -- ) ;
113 113 --end generate;
114 114
115 115 SRAM : syncram_2p
116 116 generic map(tech,8,Input_SZ_1)
117 117 port map(clk,not REN,RADDR,RD,clk,not WEN,WADDR,WD_D);
118 118 --==============================================================
119 119 --==============================================================
120 120
121 121
122 122 ADDRcntr_inst : ADDRcntr
123 123 port map(
124 124 clk => clk,
125 125 reset => reset,
126 126 count => count,
127 127 clr => GO_0,
128 128 Q => RADDR
129 129 );
130 130
131 131
132 132
133 133 MUX2_inst1 :MUX2
134 134 generic map(Input_SZ => Input_SZ_1)
135 135 port map(
136 136 sel => WD_sel,
137 137 IN1 => sample_in,
138 138 IN2 => RD(Input_SZ_1-1 downto 0),
139 139 RES => WD(Input_SZ_1-1 downto 0)
140 140 );
141 141
142 142
143 143 MUX2_inst2 :MUX2
144 144 generic map(Input_SZ => 8)
145 145 port map(
146 146 sel => WADDR_sel,
147 147 IN1 => WADDR_D,
148 148 IN2 => WADDR_back_D,
149 149 RES => WADDR
150 150 );
151 151
152 152
153
153 WADDR_backreg : REG
154 generic map(size => 8,initial_VALUE =>ChanelsCount*Cels_count*4-2)
155 port map(
156 reset => reset,
157 clk => clk, --SVG_ADDR,
158 D => WADDR_back_s,--RADDR,
159 Q => WADDR_back
160 );
161 WADDR_back_s <= RADDR WHEN SVG_ADDR = '1' ELSE WADDR_back;
154 162
155 WADDR_backreg :REG
156 generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
157 port map(
158 reset => reset,
159 clk => SVG_ADDR,
160 D => RADDR,
161 Q => WADDR_back
162 );
163 WADDR_backreg2 :entity work.REG
164 generic map(size => 8)
165 port map(
166 reset => reset,
167 clk => clk, --SVG_ADDR,
168 D => WADDR_back,
169 Q => WADDR_back_D
170 );
163 171
164 WADDR_backreg2 :REG
165 generic map(size => 8)
166 port map(
167 reset => reset,
168 clk => SVG_ADDR,
169 D => WADDR_back,
170 Q => WADDR_back_D
171 );
172 --WADDR_backreg :REG
173 --generic map(size => 8,initial_VALUE =>ChanelsCouNT*Cels_count*4-2)
174 --port map(
175 -- reset => reset,
176 -- clk => SVG_ADDR,
177 -- D => RADDR,
178 -- Q => WADDR_back
179 --);
180 --
181 --WADDR_backreg2 :REG
182 --generic map(size => 8)
183 --port map(
184 -- reset => reset,
185 -- clk => SVG_ADDR,
186 -- D => WADDR_back,
187 -- Q => WADDR_back_D
188 --
172 189
173 190 WDRreg :REG
174 191 generic map(size => Input_SZ_1)
175 192 port map(
176 193 reset => reset,
177 194 clk => clk,
178 195 D => WD(Input_SZ_1-1 downto 0),
179 196 Q => WD_D(Input_SZ_1-1 downto 0)
180 197 );
181 198
182 199
183 200
184 201
185 202 ADDRreg :REG
186 203 generic map(size => 8)
187 204 port map(
188 205 reset => reset,
189 206 clk => clk,
190 207 D => RADDR,
191 208 Q => WADDR_D
192 209 );
193 210
194 211
195 212
196 213 end ar_RAM_CTRLR2;
197 214
198 215
199 216
200 217
201 218
202 219
203 220
204 221
205 222
206 223
207 224
208 225
209 226
210 227
211 228
212 229
213 230
214 231
215 232
216 233
217 234
218 235
219 236
220 237
221 238
222 239
223 240
224 241
225 242
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@@ -1,74 +1,74
1 1 -- Top_IIR.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 use work.FILTERcfg.all;
6 6 use lpp.iir_filter.all;
7 7
8 8 entity Top_IIR is
9 9 generic(
10 Sample_SZ : integer := 20;
10 Sample_SZ : integer := 18;
11 11 ChanelsCount : integer := 1;
12 12 Coef_SZ : integer := 9;
13 13 CoefCntPerCel: integer := 6;
14 14 Cels_count : integer := 5);
15 15 port(
16 16 reset : in std_logic;
17 17 clk : in std_logic;
18 18 sample_clk : in std_logic;
19 19 -- BP : in std_logic;
20 BPinput : in std_logic_vector(3 downto 0);
21 LVLinput : in std_logic_vector(11 downto 0);
20 -- BPinput : in std_logic_vector(3 downto 0);
21 LVLinput : in std_logic_vector(15 downto 0);
22 22 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
23 23 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
24 24 );
25 25 end entity;
26 26
27 27
28 28 architecture ar_Top_IIR of Top_IIR is
29 29
30 30 signal regs_in : in_IIR_CEL_reg;
31 31 signal regs_out : out_IIR_CEL_reg;
32 32 signal sample_in : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
33 33 signal sample_out : samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
34 34 signal coefs : std_logic_vector((Coef_SZ*CoefCntPerCel*Cels_count)-1 downto 0);
35 35
36 36 signal sample_int : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
37 37 --signal sample_temp : std_logic_vector(Sample_SZ-1 downto 0):=(others => '0');
38 38
39 39 begin
40 40
41 41 ChanelLoop: for i in 0 to ChanelsCount-1 generate
42 42 SampleLoop: for j in 0 to Sample_SZ-1 generate
43 43 sample_in(i,j) <= sample_int(i*20+j);
44 44 end generate;
45 45 end generate;
46 46
47 47 --CH2loop: for k in 0 to Sample_SZ-1 generate
48 48 -- sample_temp(k) <= BP;
49 49 --end generate;
50 50
51 sample_int <= BPinput(3) & BPinput(3) & BPinput(3) & BPinput(3) & BPinput & LVLinput;
51 sample_int <= LVLinput(15) & LVLinput(15) & LVLinput;
52 52 INsample <= sample_in;
53 53 OUTsample <= sample_out;
54 54
55 55 filter : IIR_CEL_FILTER
56 56 generic map (0,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,1)
57 57 port map(
58 58 reset => reset,
59 59 clk => clk,
60 60 sample_clk => sample_clk,
61 61 regs_in => regs_in,
62 62 regs_out => regs_out,
63 63 sample_in => sample_in,
64 64 sample_out => sample_out,
65 65 coefs => coefs
66 66 );
67 67
68 68 coefs <= CoefsInitValCst;
69 69 regs_in.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
70 70 regs_in.config <= (others => '1');
71 71
72 72
73 73
74 74 end architecture; No newline at end of file
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@@ -1,266 +1,266
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29
30 30
31 31
32 32
33 33 package iir_filter is
34 34
35 35
36 36 --===========================================================|
37 37 --================A L U C O N T R O L======================|
38 38 --===========================================================|
39 39 constant IDLE : std_logic_vector(3 downto 0) := "0000";
40 40 constant MAC_op : std_logic_vector(3 downto 0) := "0001";
41 41 constant MULT : std_logic_vector(3 downto 0) := "0010";
42 42 constant ADD : std_logic_vector(3 downto 0) := "0011";
43 43 constant clr_mac : std_logic_vector(3 downto 0) := "0100";
44 44
45 45 --____
46 46 --RAM |
47 47 --____|
48 48 constant use_RAM : integer := 1;
49 49 constant use_CEL : integer := 0;
50 50
51 51
52 52 --===========================================================|
53 53 --=============C O E F S ====================================|
54 54 --===========================================================|
55 55 -- create a specific type of data for coefs to avoid errors |
56 56 --===========================================================|
57 57
58 58 type scaleValT is array(natural range <>) of integer;
59 59
60 60 type samplT is array(natural range <>,natural range <>) of std_logic;
61 61
62 62 type in_IIR_CEL_reg is record
63 63 config : std_logic_vector(31 downto 0);
64 64 virgPos : std_logic_vector(4 downto 0);
65 65 end record;
66 66
67 67 type out_IIR_CEL_reg is record
68 68 config : std_logic_vector(31 downto 0);
69 69 status : std_logic_vector(31 downto 0);
70 70 end record;
71 71
72 72
73 73 component APB_IIR_CEL is
74 74 generic (
75 75 tech : integer := 0;
76 76 pindex : integer := 0;
77 77 paddr : integer := 0;
78 78 pmask : integer := 16#fff#;
79 79 pirq : integer := 0;
80 80 abits : integer := 8;
81 81 Sample_SZ : integer := 16;
82 82 ChanelsCount : integer := 6;
83 83 Coef_SZ : integer := 9;
84 84 CoefCntPerCel: integer := 6;
85 85 Cels_count : integer := 5;
86 86 virgPos : integer := 7;
87 87 Mem_use : integer := use_RAM
88 88 );
89 89 port (
90 90 rst : in std_logic;
91 91 clk : in std_logic;
92 92 apbi : in apb_slv_in_type;
93 93 apbo : out apb_slv_out_type;
94 94 sample_clk : in std_logic;
95 95 sample_clk_out : out std_logic;
96 96 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
97 97 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
98 98 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
99 99 );
100 100 end component;
101 101
102 102
103 103 component Top_IIR is
104 104 generic(
105 Sample_SZ : integer := 20;
105 Sample_SZ : integer := 18;
106 106 ChanelsCount : integer := 1;
107 107 Coef_SZ : integer := 9;
108 108 CoefCntPerCel: integer := 6;
109 109 Cels_count : integer := 5);
110 110 port(
111 111 reset : in std_logic;
112 112 clk : in std_logic;
113 113 sample_clk : in std_logic;
114 114 -- BP : in std_logic;
115 BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(11 downto 0);
115 -- BPinput : in std_logic_vector(3 downto 0);
116 LVLinput : in std_logic_vector(15 downto 0);
117 117 INsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
118 118 OUTsample : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0)
119 119 );
120 120 end component;
121 121
122 122
123 123
124 124 --component FilterCTRLR is
125 125 --port(
126 126 -- reset : in std_logic;
127 127 -- clk : in std_logic;
128 128 -- sample_clk : in std_logic;
129 129 -- ALU_Ctrl : out std_logic_vector(3 downto 0);
130 130 -- sample_in : in samplT;
131 131 -- coef : out std_logic_vector(Coef_SZ-1 downto 0);
132 132 -- sample : out std_logic_vector(Smpl_SZ-1 downto 0)
133 133 --);
134 134 --end component;
135 135
136 136
137 137 --component FILTER_RAM_CTRLR is
138 138 --port(
139 139 -- reset : in std_logic;
140 140 -- clk : in std_logic;
141 141 -- run : in std_logic;
142 142 -- GO_0 : in std_logic;
143 143 -- B_A : in std_logic;
144 144 -- writeForce : in std_logic;
145 145 -- next_blk : in std_logic;
146 146 -- sample_in : in std_logic_vector(Smpl_SZ-1 downto 0);
147 147 -- sample_out : out std_logic_vector(Smpl_SZ-1 downto 0)
148 148 --);
149 149 --end component;
150 150
151 151
152 152 component IIR_CEL_CTRLR is
153 153 generic(
154 154 tech : integer := 0;
155 155 Sample_SZ : integer := 16;
156 156 ChanelsCount : integer := 1;
157 157 Coef_SZ : integer := 9;
158 158 CoefCntPerCel: integer := 3;
159 159 Cels_count : integer := 5;
160 160 Mem_use : integer := use_RAM
161 161 );
162 162 port(
163 163 reset : in std_logic;
164 164 clk : in std_logic;
165 165 sample_clk : in std_logic;
166 166 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
167 167 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
168 168 virg_pos : in integer;
169 169 GOtest : out std_logic;
170 170 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
171 171 );
172 172 end component;
173 173
174 174
175 175 component RAM is
176 176 generic(
177 177 Input_SZ_1 : integer := 8
178 178 );
179 179 port( WD : in std_logic_vector(Input_SZ_1-1 downto 0); RD : out
180 180 std_logic_vector(Input_SZ_1-1 downto 0);WEN, REN : in std_logic;
181 181 WADDR : in std_logic_vector(7 downto 0); RADDR : in
182 182 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
183 183 ) ;
184 184 end component;
185 185
186 186
187 187 component RAM_CEL is
188 188 port( WD : in std_logic_vector(35 downto 0); RD : out
189 189 std_logic_vector(35 downto 0);WEN, REN : in std_logic;
190 190 WADDR : in std_logic_vector(7 downto 0); RADDR : in
191 191 std_logic_vector(7 downto 0);RWCLK, RESET : in std_logic
192 192 ) ;
193 193 end component;
194 194
195 195 component IIR_CEL_FILTER is
196 196 generic(
197 197 tech : integer := 0;
198 198 Sample_SZ : integer := 16;
199 199 ChanelsCount : integer := 1;
200 200 Coef_SZ : integer := 9;
201 201 CoefCntPerCel: integer := 3;
202 202 Cels_count : integer := 5;
203 203 Mem_use : integer := use_RAM);
204 204 port(
205 205 reset : in std_logic;
206 206 clk : in std_logic;
207 207 sample_clk : in std_logic;
208 208 regs_in : in in_IIR_CEL_reg;
209 209 regs_out : in out_IIR_CEL_reg;
210 210 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
211 211 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
212 212 GOtest : out std_logic;
213 213 coefs : in std_logic_vector(Coef_SZ*CoefCntPerCel*Cels_count-1 downto 0)
214 214
215 215 );
216 216 end component;
217 217
218 218
219 219 component RAM_CTRLR2 is
220 220 generic(
221 221 tech : integer := 0;
222 222 Input_SZ_1 : integer := 16;
223 223 Mem_use : integer := use_RAM
224 224 );
225 225 port(
226 226 reset : in std_logic;
227 227 clk : in std_logic;
228 228 WD_sel : in std_logic;
229 229 Read : in std_logic;
230 230 WADDR_sel : in std_logic;
231 231 count : in std_logic;
232 232 SVG_ADDR : in std_logic;
233 233 Write : in std_logic;
234 234 GO_0 : in std_logic;
235 235 sample_in : in std_logic_vector(Input_SZ_1-1 downto 0);
236 236 sample_out : out std_logic_vector(Input_SZ_1-1 downto 0)
237 237 );
238 238 end component;
239 239
240 240 component APB_IIR_Filter is
241 241 generic (
242 242 tech : integer := 0;
243 243 pindex : integer := 0;
244 244 paddr : integer := 0;
245 245 pmask : integer := 16#fff#;
246 246 pirq : integer := 0;
247 247 abits : integer := 8;
248 248 Sample_SZ : integer := 16;
249 249 ChanelsCount : integer := 1;
250 250 Coef_SZ : integer := 9;
251 251 CoefCntPerCel: integer := 6;
252 252 Cels_count : integer := 5;
253 253 virgPos : integer := 3;
254 254 Mem_use : integer := use_RAM
255 255 );
256 256 port (
257 257 rst : in std_logic;
258 258 clk : in std_logic;
259 259 apbi : in apb_slv_in_type;
260 260 apbo : out apb_slv_out_type;
261 261 sample_clk_out : out std_logic;
262 262 GOtest : out std_logic;
263 263 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
264 264 );
265 265 end component;
266 266 end;
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@@ -1,155 +1,157
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25
26 26 entity Driver_FFT is
27 27 generic(
28 28 Data_sz : integer range 1 to 32 := 16
29 29 );
30 30 port(
31 31 clk : in std_logic;
32 32 rstn : in std_logic;
33 33 Load : in std_logic;
34 34 Empty : in std_logic_vector(4 downto 0);
35 35 Full : in std_logic_vector(4 downto 0);
36 36 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
37 37 Valid : out std_logic;
38 38 Read : out std_logic_vector(4 downto 0);
39 39 Data_re : out std_logic_vector(Data_sz-1 downto 0);
40 40 Data_im : out std_logic_vector(Data_sz-1 downto 0)
41 41 );
42 42 end entity;
43 43
44 44
45 45 architecture ar_Driver of Driver_FFT is
46 46
47 47 type etat is (eX,e0,e1,e2);
48 48 signal ect : etat;
49 49
50 50 signal FifoCpt : integer;
51 51 --signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
52 52
53 53 signal sEmpty : std_logic;
54 54 signal sFull : std_logic;
55 55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56 56
57 57 begin
58 58
59 59 process(clk,rstn)
60 60 begin
61 61 if(rstn='0')then
62 62 ect <= eX;
63 63 Read <= (others => '1');
64 64 Valid <= '0';
65 65 FifoCpt <= 1;
66 Data_re <= (others => '0');
67 Data_im <= (others => '0');
66 68
67 69 elsif(clk'event and clk='1')then
68 70
69 71 case ect is
70 72
71 73 when eX =>
72 74 if(sFull='1')then
73 75 ect <= e0;
74 76 end if;
75 77
76 78 when e0 =>
77 79 Valid <= '0';
78 80 if(Load='1' and sEmpty='0')then
79 81 Read(FifoCpt-1) <= '0';
80 82 ect <= e2;
81 83 -- ect <= e1;
82 84 elsif(sEmpty='1')then
83 85 if(FifoCpt=6)then
84 86 FifoCpt <= 1;
85 87 else
86 88 FifoCpt <= FifoCpt+1;
87 89 end if;
88 90 ect <= eX;
89 91 end if;
90 92
91 93 when e1 =>
92 94 null;
93 95 -- DataTmp <= sData;
94 96 -- ect <= e2;
95 97
96 98 when e2 =>
97 99 Read(FifoCpt-1) <= '1';
98 100 Data_re <= sData;
99 101 Data_im <= (others => '0');
100 102 -- Data_re <= DataTmp;
101 103 -- Data_im <= sData;
102 104 Valid <= '1';
103 105 ect <= e0;
104 106
105 107
106 108 end case;
107 109 end if;
108 110 end process;
109 111
110 112 with FifoCpt select
111 113 sFull <= Full(0) when 1,
112 114 Full(1) when 2,
113 115 Full(2) when 3,
114 116 Full(3) when 4,
115 117 Full(4) when 5,
116 118 '1' when others;
117 119
118 120 with FifoCpt select
119 121 sEmpty <= Empty(0) when 1,
120 122 Empty(1) when 2,
121 123 Empty(2) when 3,
122 124 Empty(3) when 4,
123 125 Empty(4) when 5,
124 126 '1' when others;
125 127
126 128 with FifoCpt select
127 129 sData <= DATA(Data_sz-1 downto 0) when 1,
128 130 DATA((2*Data_sz)-1 downto Data_sz) when 2,
129 131 DATA((3*Data_sz)-1 downto (2*Data_sz)) when 3,
130 132 DATA((4*Data_sz)-1 downto (3*Data_sz)) when 4,
131 133 DATA((5*Data_sz)-1 downto (4*Data_sz)) when 5,
132 134 (others => '0') when others;
133 135
134 136 end architecture;
135 137
136 138
137 139
138 140
139 141
140 142
141 143
142 144
143 145
144 146
145 147
146 148
147 149
148 150
149 151
150 152
151 153
152 154
153 155
154 156
155 157
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@@ -1,206 +1,242
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 use lpp.lpp_memory.all;
30 30 use work.fft_components.all;
31 31
32 32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
33 33
34 34 package lpp_fft is
35 35
36 36 component APB_FFT is
37 37 generic (
38 38 pindex : integer := 0;
39 39 paddr : integer := 0;
40 40 pmask : integer := 16#fff#;
41 41 pirq : integer := 0;
42 42 abits : integer := 8;
43 43 Data_sz : integer := 16
44 44 );
45 45 port (
46 46 clk : in std_logic;
47 47 rst : in std_logic; --! Reset general du composant
48 48 apbi : in apb_slv_in_type;
49 49 apbo : out apb_slv_out_type
50 50 );
51 51 end component;
52 52
53 53
54 54 component APB_FFT_half is
55 55 generic (
56 56 pindex : integer := 0;
57 57 paddr : integer := 0;
58 58 pmask : integer := 16#fff#;
59 59 pirq : integer := 0;
60 60 abits : integer := 8;
61 61 Data_sz : integer := 16
62 62 );
63 63 port (
64 64 clk : in std_logic; --! Horloge du composant
65 65 rst : in std_logic; --! Reset general du composant
66 66 Ren : in std_logic;
67 67 ready : out std_logic;
68 68 valid : out std_logic;
69 69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 71 OUTfill : out std_logic;
72 72 OUTwrite : out std_logic;
73 73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 75 );
76 76 end component;
77 77
78 78
79 79 component Flag_Extremum is
80 80 port(
81 81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
82 82 load : in std_logic; --! Signal en provenance de CoreFFT
83 83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
84 84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
85 85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
86 86 );
87 87 end component;
88 88
89 89
90 90 component Linker_FFT is
91 91 generic(
92 92 Data_sz : integer range 1 to 32 := 16
93 93 );
94 94 port(
95 95 clk : in std_logic;
96 96 rstn : in std_logic;
97 97 Ready : in std_logic;
98 98 Valid : in std_logic;
99 99 Full : in std_logic_vector(4 downto 0);
100 100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 102 Read : out std_logic;
103 103 Write : out std_logic_vector(4 downto 0);
104 104 ReUse : out std_logic_vector(4 downto 0);
105 105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 106 );
107 107 end component;
108 108
109 109
110 110 component Driver_FFT is
111 111 generic(
112 112 Data_sz : integer range 1 to 32 := 16
113 113 );
114 114 port(
115 115 clk : in std_logic;
116 116 rstn : in std_logic;
117 117 Load : in std_logic;
118 118 Empty : in std_logic_vector(4 downto 0);
119 119 Full : in std_logic_vector(4 downto 0);
120 120 DATA : in std_logic_vector((5*Data_sz)-1 downto 0);
121 121 Valid : out std_logic;
122 122 Read : out std_logic_vector(4 downto 0);
123 123 Data_re : out std_logic_vector(Data_sz-1 downto 0);
124 124 Data_im : out std_logic_vector(Data_sz-1 downto 0)
125 125 );
126 126 end component;
127 127
128 component FFTamont is
129 generic(
130 Data_sz : integer range 1 to 32 := 16
131 );
132 port(
133 clk : in std_logic;
134 rstn : in std_logic;
135 Load : in std_logic;
136 Empty : in std_logic;
137 Full : in std_logic;
138 DATA : in std_logic_vector(Data_sz-1 downto 0);
139 Valid : out std_logic;
140 Read : out std_logic;
141 Data_re : out std_logic_vector(Data_sz-1 downto 0);
142 Data_im : out std_logic_vector(Data_sz-1 downto 0)
143 );
144 end component;
145
146 component FFTaval is
147 generic(
148 Data_sz : integer range 1 to 32 := 8
149 );
150 port(
151 clk : in std_logic;
152 rstn : in std_logic;
153 Ready : in std_logic;
154 Valid : in std_logic;
155 Full : in std_logic;
156 Data_re : in std_logic_vector(Data_sz-1 downto 0);
157 Data_im : in std_logic_vector(Data_sz-1 downto 0);
158 Read : out std_logic;
159 Write : out std_logic;
160 ReUse : out std_logic;
161 DATA : out std_logic_vector(Data_sz-1 downto 0)
162 );
163 end component;
128 164 --==============================================================|
129 165 --================== IP VHDL de la FFT actel ===================|
130 166 --================ non partag� dans la VHD_Lib =================|
131 167 --==============================================================|
132 168
133 169 component CoreFFT IS
134 170 GENERIC (
135 171 LOGPTS : integer := gLOGPTS;
136 172 LOGLOGPTS : integer := gLOGLOGPTS;
137 173 WSIZE : integer := gWSIZE;
138 174 TWIDTH : integer := gTWIDTH;
139 175 DWIDTH : integer := gDWIDTH;
140 176 TDWIDTH : integer := gTDWIDTH;
141 177 RND_MODE : integer := gRND_MODE;
142 178 SCALE_MODE : integer := gSCALE_MODE;
143 179 PTS : integer := gPTS;
144 180 HALFPTS : integer := gHALFPTS;
145 181 inBuf_RWDLY : integer := gInBuf_RWDLY );
146 182 PORT (
147 183 clk,ifiStart,ifiNreset : IN std_logic;
148 184 ifiD_valid, ifiRead_y : IN std_logic;
149 185 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
150 186 ifoLoad, ifoPong : OUT std_logic;
151 187 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
152 188 ifoY_valid, ifoY_rdy : OUT std_logic);
153 189 END component;
154 190
155 191
156 192 component actar is
157 193 port( DataA : in std_logic_vector(15 downto 0); DataB : in
158 194 std_logic_vector(15 downto 0); Mult : out
159 195 std_logic_vector(31 downto 0);Clock : in std_logic) ;
160 196 end component;
161 197
162 198 component actram is
163 199 port( DI : in std_logic_vector(31 downto 0); DO : out
164 200 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
165 201 WADDR : in std_logic_vector(6 downto 0); RADDR : in
166 202 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
167 203 std_logic) ;
168 204 end component;
169 205
170 206 component switch IS
171 207 GENERIC ( DWIDTH : integer := 32 );
172 208 PORT (
173 209 clk, sel, validIn : IN std_logic;
174 210 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
175 211 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
176 212 validOut : OUT std_logic);
177 213 END component;
178 214
179 215 component twid_rA IS
180 216 GENERIC (LOGPTS : integer := 8;
181 217 LOGLOGPTS : integer := 3 );
182 218 PORT (clk : IN std_logic;
183 219 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
184 220 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
185 221 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
186 222 END component;
187 223
188 224 component counter IS
189 225 GENERIC (
190 226 WIDTH : integer := 7;
191 227 TERMCOUNT : integer := 127 );
192 228 PORT (
193 229 clk, nGrst, rst, cntEn : IN std_logic;
194 230 tc : OUT std_logic;
195 231 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
196 232 END component;
197 233
198 234
199 235 component twiddle IS
200 236 PORT (
201 237 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
202 238 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
203 239 END component;
204 240
205 241
206 242 end; No newline at end of file
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@@ -1,105 +1,105
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26 entity GetResult is
27 27 generic(
28 28 Result_SZ : integer := 32);
29 29 port(
30 30 clk : in std_logic;
31 31 raz : in std_logic;
32 32 Valid : in std_logic;
33 33 Conjugate : in std_logic;
34 34 Res : in std_logic_vector(Result_SZ-1 downto 0);
35 Full : in std_logic;
35 -- Full : in std_logic;
36 36 WriteFIFO : out std_logic;
37 37 Received : out std_logic;
38 38 Result : out std_logic_vector(Result_SZ-1 downto 0)
39 39 );
40 40 end GetResult;
41 41
42 42
43 43 architecture ar_GetResult of GetResult is
44 44
45 45 signal Valid_reg : std_logic;
46 46
47 47 type state is (st0,st1,stX,stY);
48 48 signal ect : state;
49 49
50 50 begin
51 51 process(clk,raz)
52 52 begin
53 53
54 54 if(raz='0')then
55 55 Received <= '0';
56 56 Valid_reg <= '0';
57 57 WriteFIFO <= '0';
58 58 ect <= st0;
59 59 Result <= (others => '0');
60 60
61 61 elsif(clk'event and clk='1')then
62 62 Valid_reg <= Valid;
63 63
64 64 case ect is
65 65 when st0 =>
66 if(Full='0' and Valid='1')then
66 if(Valid='1')then--if(Full='0' and Valid='1')then
67 67 Result <= Res;
68 68 WriteFIFO <= '1';
69 69 Received <= '1';
70 70 ect <= stX;
71 71 end if;
72 72
73 73 when stX =>
74 74 WriteFIFO <= '0';
75 75 if(Conjugate='1')then
76 76 Received <= '0';
77 77 end if;
78 78 if(Valid_reg='1' and Valid='0')then
79 79 if(Conjugate='1')then
80 80 ect <= st0;
81 81 else
82 82 ect <= st1;
83 83 end if;
84 84 end if;
85 85
86 86 when st1 =>
87 if(Full='0' and Valid='1')then
87 if(Valid='1')then--if(Full='0' and Valid='1')then
88 88 Result <= Res;
89 89 WriteFIFO <= '1';
90 90 Received <= '0';
91 91 ect <= stY;
92 92 end if;
93 93
94 94 when stY =>
95 95 WriteFIFO <= '0';
96 96 if(Valid_reg='1' and Valid='0')then
97 97 ect <= st0;
98 98 end if;
99 99
100 100 end case;
101 101 end if;
102 102 end process;
103 103
104 104 end ar_GetResult;
105 105
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@@ -1,84 +1,84
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 use lpp.lpp_matrix.all;
26 26
27 27 entity SpectralMatrix is
28 28 generic(
29 29 Input_SZ : integer := 16;
30 30 Result_SZ : integer := 32);
31 31 port(
32 32 clk : in std_logic;
33 33 reset : in std_logic;
34 34 Start : in std_logic;
35 35 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
36 36 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
37 37 Statu : in std_logic_vector(3 downto 0);
38 FullFIFO : in std_logic;
38 -- FullFIFO : in std_logic;
39 39 ReadFIFO : out std_logic_vector(1 downto 0);
40 40 WriteFIFO : out std_logic;
41 41 Result : out std_logic_vector(Result_SZ-1 downto 0)
42 42 );
43 43 end SpectralMatrix;
44 44
45 45
46 46 architecture ar_SpectralMatrix of SpectralMatrix is
47 47
48 48 signal RaZ : std_logic;
49 49 signal Read_int : std_logic;
50 50 signal Take_int : std_logic;
51 51 signal Received_int : std_logic;
52 52 signal Valid_int : std_logic;
53 53 signal Conjugate_int : std_logic;
54 54
55 55 signal Resultat : std_logic_vector(Result_SZ-1 downto 0);
56 56
57 57
58 58 begin
59 59
60 60 RaZ <= reset and Start;
61 61
62 62 IN1 : DriveInputs
63 63 port map(clk,RaZ,Read_int,Conjugate_int,Take_int,ReadFIFO);
64 64
65 65
66 66 CALC0 : Matrix
67 67 generic map(Input_SZ)
68 68 port map(clk,RaZ,FIFO1,FIFO2,Take_int,Received_int,Conjugate_int,Valid_int,Read_int,Resultat);
69 69
70 70
71 71 RES0 : GetResult
72 72 generic map(Result_SZ)
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,FullFIFO,WriteFIFO,Received_int,Result);
73 port map(clk,RaZ,Valid_int,Conjugate_int,Resultat,WriteFIFO,Received_int,Result);--Resultat,FullFIFO,WriteFIFO
74 74
75 75
76 76 With Statu select
77 77 Conjugate_int <= '1' when "0001",
78 78 '1' when "0011",
79 79 '1' when "0110",
80 80 '1' when "1010",
81 81 '1' when "1111",
82 82 '0' when others;
83 83
84 84 end ar_SpectralMatrix; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,241 +1,259
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31 31
32 32 package lpp_matrix is
33 33
34 34 component APB_Matrix is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 Input_SZ : integer := 16;
42 42 Result_SZ : integer := 32);
43 43 port (
44 44 clk : in std_logic;
45 45 rst : in std_logic;
46 46 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
47 47 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
48 48 Full : in std_logic_vector(1 downto 0);
49 49 Empty : in std_logic_vector(1 downto 0);
50 50 ReadFIFO : out std_logic_vector(1 downto 0);
51 51 FullFIFO : in std_logic;
52 52 WriteFIFO : out std_logic;
53 53 Result : out std_logic_vector(Result_SZ-1 downto 0);
54 54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 56 );
57 57 end component;
58 58
59 59 component Top_MatrixSpec is
60 60 generic(
61 61 Input_SZ : integer := 16;
62 62 Result_SZ : integer := 32);
63 63 port(
64 64 clk : in std_logic;
65 65 reset : in std_logic;
66 66 Statu : in std_logic_vector(3 downto 0);
67 67 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
68 68 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
69 69 Full : in std_logic_vector(1 downto 0);
70 70 Empty : in std_logic_vector(1 downto 0);
71 71 ReadFIFO : out std_logic_vector(1 downto 0);
72 72 FullFIFO : in std_logic;
73 73 WriteFIFO : out std_logic;
74 74 Result : out std_logic_vector(Result_SZ-1 downto 0)
75 75 );
76 76 end component;
77 77
78 78 component SpectralMatrix is
79 79 generic(
80 80 Input_SZ : integer := 16;
81 81 Result_SZ : integer := 32);
82 82 port(
83 83 clk : in std_logic;
84 84 reset : in std_logic;
85 85 Start : in std_logic;
86 86 FIFO1 : in std_logic_vector(Input_SZ-1 downto 0);
87 87 FIFO2 : in std_logic_vector(Input_SZ-1 downto 0);
88 88 Statu : in std_logic_vector(3 downto 0);
89 FullFIFO : in std_logic;
89 -- FullFIFO : in std_logic;
90 90 ReadFIFO : out std_logic_vector(1 downto 0);
91 91 WriteFIFO : out std_logic;
92 92 Result : out std_logic_vector(Result_SZ-1 downto 0)
93 93 );
94 94 end component;
95 95
96 96
97 97 component Matrix is
98 98 generic(
99 99 Input_SZ : integer := 16);
100 100 port(
101 101 clk : in std_logic;
102 102 raz : in std_logic;
103 103 IN1 : in std_logic_vector(Input_SZ-1 downto 0);
104 104 IN2 : in std_logic_vector(Input_SZ-1 downto 0);
105 105 Take : in std_logic;
106 106 Received : in std_logic;
107 107 Conjugate : in std_logic;
108 108 Valid : out std_logic;
109 109 Read : out std_logic;
110 110 Result : out std_logic_vector(2*Input_SZ-1 downto 0)
111 111 );
112 112 end component;
113 113
114 114 component GetResult is
115 115 generic(
116 116 Result_SZ : integer := 32);
117 117 port(
118 118 clk : in std_logic;
119 119 raz : in std_logic;
120 120 Valid : in std_logic;
121 121 Conjugate : in std_logic;
122 122 Res : in std_logic_vector(Result_SZ-1 downto 0);
123 Full : in std_logic;
123 -- Full : in std_logic;
124 124 WriteFIFO : out std_logic;
125 125 Received : out std_logic;
126 126 Result : out std_logic_vector(Result_SZ-1 downto 0)
127 127 );
128 128 end component;
129 129
130 130
131 131 component TopMatrix_PDR is
132 132 generic(
133 133 Input_SZ : integer := 16;
134 134 Result_SZ : integer := 32);
135 135 port(
136 136 clk : in std_logic;
137 137 reset : in std_logic;
138 138 Data : in std_logic_vector((5*Input_SZ)-1 downto 0);
139 139 FULLin : in std_logic_vector(4 downto 0);
140 140 READin : in std_logic_vector(1 downto 0);
141 141 WRITEin : in std_logic;
142 142 FIFO1 : out std_logic_vector(Input_SZ-1 downto 0);
143 143 FIFO2 : out std_logic_vector(Input_SZ-1 downto 0);
144 144 Start : out std_logic;
145 145 Read : out std_logic_vector(4 downto 0);
146 146 Statu : out std_logic_vector(3 downto 0)
147 147 );
148 148 end component;
149 149
150 150
151 component Dispatch is
152 generic(
153 Data_SZ : integer := 32);
154 port(
155 clk : in std_logic;
156 reset : in std_logic;
157 Acq : in std_logic;
158 Data : in std_logic_vector(Data_SZ-1 downto 0);
159 Write : in std_logic;
160 Full : in std_logic_vector(1 downto 0);
161 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
162 FifoWrite : out std_logic_vector(1 downto 0);
163 Pong : out std_logic;
164 Error : out std_logic
165 );
166 end component;
167
168
151 169 component DriveInputs is
152 170 port(
153 171 clk : in std_logic;
154 172 raz : in std_logic;
155 173 Read : in std_logic;
156 174 Conjugate : in std_logic;
157 175 Take : out std_logic;
158 176 ReadFIFO : out std_logic_vector(1 downto 0)
159 177 );
160 178 end component;
161 179
162 180 component Starter is
163 181 port(
164 182 clk : in std_logic;
165 183 raz : in std_logic;
166 184 Full : in std_logic_vector(1 downto 0);
167 185 Empty : in std_logic_vector(1 downto 0);
168 186 Statu : in std_logic_vector(3 downto 0);
169 187 Write : in std_logic;
170 188 Start : out std_logic
171 189 );
172 190 end component;
173 191
174 192 component ALU_Driver is
175 193 generic(
176 194 Input_SZ_1 : integer := 16;
177 195 Input_SZ_2 : integer := 16);
178 196 port(
179 197 clk : in std_logic;
180 198 reset : in std_logic;
181 199 IN1 : in std_logic_vector(Input_SZ_1-1 downto 0);
182 200 IN2 : in std_logic_vector(Input_SZ_2-1 downto 0);
183 201 Take : in std_logic;
184 202 Received : in std_logic;
185 203 Conjugate : in std_logic;
186 204 Valid : out std_logic;
187 205 Read : out std_logic;
188 206 CTRL : out std_logic_vector(4 downto 0);
189 207 OP1 : out std_logic_vector(Input_SZ_1-1 downto 0);
190 208 OP2 : out std_logic_vector(Input_SZ_2-1 downto 0)
191 209 );
192 210 end component;
193 211
194 212
195 213 component ALU_v2 is
196 214 generic(
197 215 Arith_en : integer := 1;
198 216 Logic_en : integer := 1;
199 217 Input_SZ_1 : integer := 16;
200 218 Input_SZ_2 : integer := 9);
201 219 port(
202 220 clk : in std_logic;
203 221 reset : in std_logic;
204 222 ctrl : in std_logic_vector(4 downto 0);
205 223 OP1 : in std_logic_vector(Input_SZ_1-1 downto 0);
206 224 OP2 : in std_logic_vector(Input_SZ_2-1 downto 0);
207 225 RES : out std_logic_vector(Input_SZ_1+Input_SZ_2-1 downto 0)
208 226 );
209 227 end component;
210 228
211 229
212 230 component MAC_v2 is
213 231 generic(
214 232 Input_SZ_A : integer := 8;
215 233 Input_SZ_B : integer := 8);
216 234 port(
217 235 clk : in std_logic;
218 236 reset : in std_logic;
219 237 clr_MAC : in std_logic;
220 238 MAC_MUL_ADD_2C : in std_logic_vector(3 downto 0);
221 239 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
222 240 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
223 241 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
224 242 );
225 243 end component;
226 244
227 245
228 246 component TwoComplementer is
229 247 generic(
230 248 Input_SZ : integer := 16);
231 249 port(
232 250 clk : in std_logic;
233 251 reset : in std_logic;
234 252 clr : in std_logic;
235 253 TwoComp : in std_logic;
236 254 OP : in std_logic_vector(Input_SZ-1 downto 0);
237 255 RES : out std_logic_vector(Input_SZ-1 downto 0)
238 256 );
239 257 end component;
240 258
241 259 end; No newline at end of file
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@@ -1,290 +1,263
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 -- APB_FIFO.vhd
23 23 library ieee;
24 24 use ieee.std_logic_1164.all;
25 25 use IEEE.numeric_std.all;
26 26 library techmap;
27 27 use techmap.gencomp.all;
28 28 library grlib;
29 29 use grlib.amba.all;
30 30 use grlib.stdlib.all;
31 31 use grlib.devices.all;
32 32 library lpp;
33 33 use lpp.lpp_amba.all;
34 34 use lpp.apb_devices_list.all;
35 35 use lpp.lpp_memory.all;
36 36
37 37
38 38 entity APB_FIFO is
39 39 generic (
40 40 tech : integer := apa3;
41 41 pindex : integer := 0;
42 42 paddr : integer := 0;
43 43 pmask : integer := 16#fff#;
44 44 pirq : integer := 0;
45 45 abits : integer := 8;
46 46 FifoCnt : integer := 2;
47 47 Data_sz : integer := 16;
48 48 Addr_sz : integer := 9;
49 49 Enable_ReUse : std_logic := '0';
50 50 R : integer := 1;
51 51 W : integer := 1
52 52 );
53 53 port (
54 54 clk : in std_logic; --! Horloge du composant
55 55 rst : in std_logic; --! Reset general du composant
56 56 rclk : in std_logic;
57 57 wclk : in std_logic;
58 58 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
59 59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
60 60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
61 61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
62 62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
63 63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
64 64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
65 65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
66 66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 67 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
68 68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 69 );
70 70 end entity;
71 71
72 72 architecture ar_APB_FIFO of APB_FIFO is
73 73
74 74 constant REVISION : integer := 1;
75 75
76 76 constant pconfig : apb_config_type := (
77 77 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO_PID, 0, REVISION, 0),
78 78 1 => apb_iobar(paddr, pmask));
79 79
80 80 type FIFO_ctrlr_Reg is record
81 81 FIFO_Ctrl : std_logic_vector(31 downto 0);
82 82 FIFO_Wdata : std_logic_vector(Data_sz-1 downto 0);
83 83 FIFO_Rdata : std_logic_vector(Data_sz-1 downto 0);
84 84 end record;
85 85
86 86 type FIFO_ctrlr_Reg_Vec is array(FifoCnt-1 downto 0) of FIFO_ctrlr_Reg;
87 87 type fifodatabus is array(FifoCnt-1 downto 0) of std_logic_vector(Data_sz-1 downto 0);
88 88 type fifoaddressbus is array(FifoCnt-1 downto 0) of std_logic_vector(Addr_sz-1 downto 0);
89 89
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0); --05/06/12
90 signal Rec : FIFO_ctrlr_Reg_Vec;
91 signal PRdata : std_logic_vector(31 downto 0);
92 signal FIFO_ID : std_logic_vector(31 downto 0);
93 signal autoloaded : std_logic_vector(FifoCnt-1 downto 0);
94 signal sFull : std_logic_vector(FifoCnt-1 downto 0);
95 signal sEmpty : std_logic_vector(FifoCnt-1 downto 0);
96 signal sEmpty_d : std_logic_vector(FifoCnt-1 downto 0);
97 signal sWen : std_logic_vector(FifoCnt-1 downto 0);
98 signal sRen : std_logic_vector(FifoCnt-1 downto 0);
99 signal sRclk : std_logic;
100 signal sWclk : std_logic;
101 signal sWen_APB : std_logic_vector(FifoCnt-1 downto 0);
102 signal sRen_APB : std_logic_vector(FifoCnt-1 downto 0);
103 signal sRDATA : fifodatabus;
104 signal sWDATA : fifodatabus;
105 signal sWADDR : fifoaddressbus;
106 signal sRADDR : fifoaddressbus;
107 signal sReUse : std_logic_vector(FifoCnt-1 downto 0);
108 signal sReUse_APB : std_logic_vector(FifoCnt-1 downto 0);
109
110 signal regDataValid : std_logic_vector(FifoCnt-1 downto 0);
111 signal regData : fifodatabus;
112 signal regREN : std_logic_vector(FifoCnt-1 downto 0);
109 113
110 114 type state_t is (idle,Read);
111 115 signal fiforeadfsmst : state_t;
112 116
113 117 begin
114 118
115 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
116 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
117 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
119 FIFO_ID(3 downto 0) <= std_logic_vector(to_unsigned(FifoCnt,4));
120 FIFO_ID(15 downto 8) <= std_logic_vector(to_unsigned(Data_sz,8));
121 FIFO_ID(23 downto 16) <= std_logic_vector(to_unsigned(Addr_sz,8));
118 122
119 123
120 Write : if W /= 0 generate
124 Writeint : if W /= 0 generate
121 125 FIFO_ID(4) <= '1';
122 126 sWen <= sWen_APB;
123 127 sReUse <= sReUse_APB;
124 128 sWclk <= clk;
125 129 Wrapb: for i in 0 to FifoCnt-1 generate
126 130 sWDATA(i) <= Rec(i).FIFO_Wdata;
127 131 end generate;
128 132 end generate;
129 133
130 134 Writeext : if W = 0 generate
131 135 FIFO_ID(4) <= '0';
132 136 sWen <= WEN;
133 137 sReUse <= ReUse;
134 138 sWclk <= Wclk;
135 139 Wrext: for i in 0 to FifoCnt-1 generate
136 140 sWDATA(i) <= WDATA((Data_sz*(i+1)-1) downto (Data_sz)*i);
137 141 end generate;
138 142 end generate;
139 143
140 Read : if R /= 0 generate
144 Readint : if R /= 0 generate
141 145 FIFO_ID(5) <= '1';
142 146 sRen <= sRen_APB;
143 147 srclk <= clk;
144 148 Rdapb: for i in 0 to FifoCnt-1 generate
145 149 Rec(i).FIFO_Rdata <= sRDATA(i);
146 150 end generate;
147 151 end generate;
148 152
149 153 Readext : if R = 0 generate
150 154 FIFO_ID(5) <= '0';
151 155 sRen <= REN;
152 156 srclk <= rclk;
153 157 Drext: for i in 0 to FifoCnt-1 generate
154 158 RDATA((Data_sz*(i+1))-1 downto (Data_sz)*i) <= sRDATA(i);
155 159 end generate;
156 160 end generate;
157 161
158 162 ctrlregs: for i in 0 to FifoCnt-1 generate
159 163 RADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sRADDR(i);
160 164 WADDR((Addr_sz*(i+1))-1 downto (Addr_sz)*i) <= sWADDR(i);
161 165 Rec(i).FIFO_Ctrl(16) <= sFull(i);
162 --Rec(i).FIFO_Ctrl(17) <= Rec(i).FIFO_Ctrl(1); --27/01/12
163 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1); --27/01/12
164 Rec(i).FIFO_Ctrl(3 downto 2) <= "00"; --27/01/12
165 Rec(i).FIFO_Ctrl(19 downto 17) <= "000"; --27/01/12
166 sReUse_APB(i) <= Rec(i).FIFO_Ctrl(1);
167 Rec(i).FIFO_Ctrl(3 downto 2) <= "00";
168 Rec(i).FIFO_Ctrl(19 downto 17) <= "000";
166 169 Rec(i).FIFO_Ctrl(Addr_sz+3 downto 4) <= sRADDR(i);
167 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i); ---|free|Waddrs|Full||free|Raddrs|empty|
168 end generate; -- 31 17 16 15 1 0
170 Rec(i).FIFO_Ctrl((Addr_sz+19) downto 20) <= sWADDR(i);
171 end generate;
169 172
170 173 Empty <= sEmpty;
171 174 Full <= sFull;
172 175
173
174 176 fifos: for i in 0 to FifoCnt-1 generate
175 177 FIFO0 : lpp_fifo
176 178 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
177 179 port map(rst,sReUse(i),srclk,sRen(i),sRDATA(i),sEmpty(i),sRADDR(i),swclk,sWen(i),sWDATA(i),sFull(i),sWADDR(i));
178 180 end generate;
179 181
180 182 process(rst,clk)
181 183 begin
182 184 if(rst='0')then
183 185 rstloop1: for i in 0 to FifoCnt-1 loop
184 186 Rec(i).FIFO_Wdata <= (others => '0');
185 Rec(i).FIFO_Ctrl(1) <= '0'; --27/01/12
186 --Rec(i).FIFO_Ctrl(17) <= '0';
187 Rec(i).FIFO_Ctrl(1) <= '0'; -- ReUse
187 188 sWen_APB(i) <= '1';
188 189 end loop;
189 190 elsif(clk'event and clk='1')then
191
190 192 --APB Write OP
191 193 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
192 194 writelp: for i in 0 to FifoCnt-1 loop
193 195 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
194 196 Rec(i).FIFO_Ctrl(1) <= apbi.pwdata(1);
195 --Rec(i).FIFO_Ctrl(17) <= apbi.pwdata(17);
196 197 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
197 198 Rec(i).FIFO_Wdata <= apbi.pwdata(Data_sz-1 downto 0);
198 199 sWen_APB(i) <= '0';
199 200 end if;
200 201 end loop;
201 202 else
202 203 sWen_APB <= (others =>'1');
203 204 end if;
205
204 206 --APB Read OP
205 207 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
206 208 if(apbi.paddr(abits-1 downto 2)="000000") then
207 209 PRdata <= FIFO_ID;
208 210 else
209 211 readlp: for i in 0 to FifoCnt-1 loop
210 212 if(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+1)) then
211 213 PRdata <= Rec(i).FIFO_Ctrl;
212 214 elsif(conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) then
213 215 PRdata(Data_sz-1 downto 0) <= Rec(i).FIFO_rdata;
214 216 end if;
215 end loop;
216 end if;
217 end loop;
218 end if;
217 219 end if;
218 220 end if;
221
219 222 apbo.pconfig <= pconfig;
223
220 224 end process;
221 225 apbo.prdata <= PRdata when apbi.penable = '1';
222 226
223
224
225 227 process(rst,clk)
226 228 begin
227 229 if(rst='0')then
228 230 fiforeadfsmst <= idle;
229 231 rstloop: for i in 0 to FifoCnt-1 loop
230 232 sRen_APB(i) <= '1';
231 233 autoloaded(i) <= '1';
232 234 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
233 235 end loop;
234 236 elsif clk'event and clk = '1' then
235 237 sEmpty_d <= sEmpty;
236 238 case fiforeadfsmst is
237 239 when idle =>
238 240 idlelp: for i in 0 to FifoCnt-1 loop
239 241 if((sEmpty_d(i) = '1' and sEmpty(i) = '0' and autoloaded(i) = '1')or((conv_integer(apbi.paddr(abits-1 downto 2))=((2*i)+2)) and (apbi.psel(pindex)='1' and apbi.penable='1' and apbi.pwrite='0'))) then
240 242 if(sEmpty_d(i) = '1' and sEmpty(i) = '0') then
241 243 autoloaded(i) <= '0';
242 244 else
243 245 autoloaded(i) <= '1';
244 246 end if;
245 247 sRen_APB(i) <= '0';
246 248 fiforeadfsmst <= read;
247 249 Rec(i).FIFO_Ctrl(0) <= sEmpty(i);
248 250 else
249 251 sRen_APB(i) <= '1';
250 252 end if;
251 253 end loop;
252 254 when read =>
253 255 sRen_APB <= (others => '1');
254 256 fiforeadfsmst <= idle;
255 257 when others =>
256 258 fiforeadfsmst <= idle;
257 259 end case;
258 260 end if;
259 end process;
260
261
262 end ar_APB_FIFO;
263
264
265
266
267
268
269
270
271
272
273
261 end process;
274 262
275
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290
263 end ar_APB_FIFO; No newline at end of file
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@@ -1,164 +1,174
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 library lpp;
26 26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 28 library techmap;
28 29 use techmap.gencomp.all;
29 30
30 31 entity lpp_fifo is
31 32 generic(
32 33 tech : integer := 0;
33 34 Enable_ReUse : std_logic := '0';
34 35 DataSz : integer range 1 to 32 := 8;
35 36 abits : integer range 2 to 12 := 8
36 37 );
37 38 port(
38 39 rstn : in std_logic;
39 ReUse : in std_logic; --27/01/12
40 ReUse : in std_logic;
40 41 rclk : in std_logic;
41 42 ren : in std_logic;
42 43 rdata : out std_logic_vector(DataSz-1 downto 0);
43 44 empty : out std_logic;
44 45 raddr : out std_logic_vector(abits-1 downto 0);
45 46 wclk : in std_logic;
46 47 wen : in std_logic;
47 48 wdata : in std_logic_vector(DataSz-1 downto 0);
48 49 full : out std_logic;
49 50 waddr : out std_logic_vector(abits-1 downto 0)
50 51 );
51 52 end entity;
52 53
53 54
54 55 architecture ar_lpp_fifo of lpp_fifo is
55 56
56 signal sFull : std_logic:='0';
57 signal sEmpty : std_logic:='1';
58 signal sREN : std_logic:='0';
59 signal sWEN : std_logic:='0';
57 signal sFull : std_logic;
58 signal sFull_s : std_logic;
59 signal sEmpty_s : std_logic;
60
61 signal sEmpty : std_logic;
62 signal sREN : std_logic;
63 signal sWEN : std_logic;
64 signal sRE : std_logic;
65 signal sWE : std_logic;
60 66
61 67 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
62 68 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
63 signal Waddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
64 signal Raddr_vect_d : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
65 71
66 72 begin
67 73
74 --==================================================================================
75 -- /!\ syncram_2p Write et Read actif a l'�tat haut /!\
76 -- A l'inverse de RAM_CEL !!!
77 --==================================================================================
68 78 SRAM : syncram_2p
69 generic map(tech,abits,DataSz)
70 port map(RCLK,sREN,Raddr_vect,rdata,WCLK,sWEN,Waddr_vect,wdata);
71
79 generic map(tech,abits,DataSz)
80 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
81 --==================================================================================
72 82 --RAM0: entity work.RAM_CEL
73 -- generic map(abits, DataSz)
74 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, RCLK, WCLK, rstn);
75
83 -- port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
84 --==================================================================================
76 85
77 86 --=============================
78 87 -- Read section
79 88 --=============================
80 sREN <= not REN and not sempty;
89 sREN <= REN or sEmpty;
90 sRE <= not sREN;
91
92 sEmpty_s <= '0' when ReUse = '1' and Enable_ReUse='1' else
93 '1' when sEmpty = '1' and Wen = '1' else
94 '1' when sEmpty = '0' and (Wen = '1' and Ren = '0' and Raddr_vect_s = Waddr_vect) else
95 '0';
96
97 Raddr_vect_s <= std_logic_vector(unsigned(Raddr_vect) +1);
81 98
82 99 process (rclk,rstn)
83 100 begin
84 101 if(rstn='0')then
85 102 Raddr_vect <= (others =>'0');
86 Raddr_vect_d <= (others =>'1');
87 103 sempty <= '1';
88 elsif(rclk'event and rclk='1')then
89 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
90 sempty <= '0'; --27/01/12
91 elsif(Raddr_vect=Waddr_vect_d and REN = '0' and sempty = '0')then
92 sempty <= '1';
93 elsif(Raddr_vect/=Waddr_vect) then
94 sempty <= '0';
104 elsif(rclk'event and rclk='1')then
105 sEmpty <= sempty_s;
106
107 if(sREN='0' and sempty = '0')then
108 Raddr_vect <= Raddr_vect_s;
95 109 end if;
96 if(sREN='1' and sempty = '0') then
97 Raddr_vect <= std_logic_vector(unsigned(Raddr_vect) + 1);
98 Raddr_vect_d <= Raddr_vect;
99 end if;
100
110
101 111 end if;
102 112 end process;
103 113
104 114 --=============================
105 115 -- Write section
106 116 --=============================
107 sWEN <= not WEN and not sfull;
117 sWEN <= WEN or sFull;
118 sWE <= not sWEN;
119
120 sFull_s <= '1' when ReUse = '1' and Enable_ReUse='1' else
121 '1' when Waddr_vect_s = Raddr_vect and REN = '1' and WEN = '0' else
122 '1' when sFull = '1' and REN = '1' else
123 '0';
124
125 Waddr_vect_s <= std_logic_vector(unsigned(Waddr_vect) +1);
108 126
109 127 process (wclk,rstn)
110 128 begin
111 129 if(rstn='0')then
112 130 Waddr_vect <= (others =>'0');
113 Waddr_vect_d <= (others =>'1');
114 131 sfull <= '0';
115 132 elsif(wclk'event and wclk='1')then
116 if(ReUse = '1' and Enable_ReUse='1')then --27/01/12
117 sfull <= '1'; --27/01/12
118 elsif(Raddr_vect_d=Waddr_vect and WEN = '0' and sfull = '0')then
119 sfull <= '1';
120 elsif(Raddr_vect/=Waddr_vect) then
121 sfull <= '0';
133 sfull <= sfull_s;
134
135 if(sWEN='0' and sfull='0')then
136 Waddr_vect <= Waddr_vect_s;
122 137 end if;
123 if(sWEN='1' and sfull='0') then
124 Waddr_vect <= std_logic_vector(unsigned(Waddr_vect) +1);
125 Waddr_vect_d <= Waddr_vect;
126 end if;
127
128
138
129 139 end if;
130 140 end process;
131 141
132 142
133 full <= sFull;
134 empty <= sEmpty;
143 full <= sFull_s;
144 empty <= sEmpty_s;
135 145 waddr <= Waddr_vect;
136 146 raddr <= Raddr_vect;
137 147
138 148 end architecture;
139 149
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 library gaisler;
30 30 use gaisler.misc.all;
31 31 use gaisler.memctrl.all;
32 32 library techmap;
33 33 use techmap.gencomp.all;
34 34
35 35 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36 36
37 37 package lpp_memory is
38 38
39 39 component APB_FIFO is
40 40 generic (
41 41 tech : integer := apa3;
42 42 pindex : integer := 0;
43 43 paddr : integer := 0;
44 44 pmask : integer := 16#fff#;
45 45 pirq : integer := 0;
46 46 abits : integer := 8;
47 47 FifoCnt : integer := 2;
48 48 Data_sz : integer := 16;
49 49 Addr_sz : integer := 9;
50 50 Enable_ReUse : std_logic := '0';
51 51 R : integer := 1;
52 52 W : integer := 1
53 53 );
54 54 port (
55 55 clk : in std_logic; --! Horloge du composant
56 56 rst : in std_logic; --! Reset general du composant
57 57 rclk : in std_logic;
58 58 wclk : in std_logic;
59 59 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
60 60 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
61 61 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
62 62 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
63 63 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
64 64 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
65 65 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
66 66 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
67 67 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
68 68 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
69 69 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
70 70 );
71 71 end component;
72 72
73 73
74 74 component lpp_fifo is
75 75 generic(
76 76 tech : integer := 0;
77 77 Enable_ReUse : std_logic := '0';
78 78 DataSz : integer range 1 to 32 := 8;
79 79 abits : integer range 2 to 12 := 8
80 80 );
81 81 port(
82 82 rstn : in std_logic;
83 83 ReUse : in std_logic; --27/01/12
84 84 rclk : in std_logic;
85 85 ren : in std_logic;
86 86 rdata : out std_logic_vector(DataSz-1 downto 0);
87 87 empty : out std_logic;
88 88 raddr : out std_logic_vector(abits-1 downto 0);
89 89 wclk : in std_logic;
90 90 wen : in std_logic;
91 91 wdata : in std_logic_vector(DataSz-1 downto 0);
92 92 full : out std_logic;
93 93 waddr : out std_logic_vector(abits-1 downto 0)
94 94 );
95 95 end component;
96 96
97 97
98 98 component lppFIFOxN is
99 99 generic(
100 100 tech : integer := 0;
101 101 Data_sz : integer range 1 to 32 := 8;
102 102 FifoCnt : integer := 1;
103 103 Enable_ReUse : std_logic := '0'
104 104 );
105 105 port(
106 106 rst : in std_logic;
107 107 wclk : in std_logic;
108 108 rclk : in std_logic;
109 109 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
110 110 wen : in std_logic_vector(FifoCnt-1 downto 0);
111 111 ren : in std_logic_vector(FifoCnt-1 downto 0);
112 112 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
113 113 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
114 114 full : out std_logic_vector(FifoCnt-1 downto 0);
115 115 empty : out std_logic_vector(FifoCnt-1 downto 0)
116 116 );
117 117 end component;
118 118
119 component lppFIFOx5 is
120 generic(
121 tech : integer := 0;
122 Data_sz : integer range 1 to 32 := 16;
123 Addr_sz : integer range 2 to 12 := 8;
124 Enable_ReUse : std_logic := '0'
125 );
126 port(
127 rst : in std_logic;
128 wclk : in std_logic;
129 rclk : in std_logic;
130 ReUse : in std_logic_vector(4 downto 0);
131 wen : in std_logic_vector(4 downto 0);
132 ren : in std_logic_vector(4 downto 0);
133 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
134 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
135 full : out std_logic_vector(4 downto 0);
136 empty : out std_logic_vector(4 downto 0)
137 );
138 end component;
139
140 component Bridge is
141 generic(
142 Data_sz : integer range 1 to 32 := 16
143 );
144 port(
145 clk : in std_logic;
146 raz : in std_logic;
147 Start : in std_logic;
148 FullUp : in std_logic;
149 EmptyUp : in std_logic;
150 FullDown : in std_logic;
151 EmptyDown : in std_logic;
152 Write : out std_logic;
153 Read : out std_logic
154 );
155 end component;
119 156
120 157 component ssram_plugin is
121 158 generic (tech : integer := 0);
122 159 port
123 160 (
124 161 clk : in std_logic;
125 162 mem_ctrlr_o : in memory_out_type;
126 163 SSRAM_CLK : out std_logic;
127 164 nBWa : out std_logic;
128 165 nBWb : out std_logic;
129 166 nBWc : out std_logic;
130 167 nBWd : out std_logic;
131 168 nBWE : out std_logic;
132 169 nADSC : out std_logic;
133 170 nADSP : out std_logic;
134 171 nADV : out std_logic;
135 172 nGW : out std_logic;
136 173 nCE1 : out std_logic;
137 174 CE2 : out std_logic;
138 175 nCE3 : out std_logic;
139 176 nOE : out std_logic;
140 177 MODE : out std_logic;
141 178 ZZ : out std_logic
142 179 );
143 180 end component;
144 181
145 182 end;
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