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IP FFT modified/cleaned, FFT C Driver added
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_uart_Driver
25 INPUTFILE=main.c
26 EXEC=BenchFFT.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_uart_Driver.h"
4 #include "apb_fft_Driver.h"
5
6
7 int main()
8 {
9 char temp[256];
10 int i;
11 int Table[256];
12 //Somme de 2 sinus//
13 //int Tablo[256] = {0x00000000,0x0DA20000,0x1B080000,0x27F70000,0x34380000,0x3F960000,0x49E10000,0x52F10000,0x5AA10000,0x60D60000,0x657D0000,0x688C0000,0x69FE0000,0x69DB0000,0x68310000,0x65170000,0x60A90000,0x5B0D0000,0x546D0000,0x4CF90000,0x44E30000,0x3C610000,0x33AA0000,0x2AF40000,0x22750000,0x1A610000,0x12E70000,0x0C310000,0x06660000,0x01A30000,0xFE010000,0xFB8E0000,0xFA520000,0xFA4D0000,0xFB770000,0xFDBE0000,0x010A0000,0x053E0000,0x0A330000,0x0FBF0000,0x15B30000,0x1BDE0000,0x220C0000,0x28080000,0x2D9D0000,0x329B0000,0x36D20000,0x3A170000,0x3C440000,0x3D390000,0x3CDE0000,0x3B210000,0x37F90000,0x33650000,0x2D6D0000,0x26210000,0x1D990000,0x13F30000,0x09570000,0xFDF10000,0xF1F20000,0xE58F0000,0xD9030000,0xCC870000,0xC0560000,0xB4AA0000,0xA9BC0000,0x9FBF0000,0x96E40000,0x8F570000,0x893A0000,0x84AB0000,0x81BF0000,0x80830000,0x80FB0000,0x83220000,0x86EC0000,0x8C430000,0x93090000,0x9B1B0000,0xA44D0000,0xAE700000,0xB9500000,0xC4B40000,0xD0630000,0xDC240000,0xE7BD0000,0xF2F60000,0xFD9A0000,0x077A0000,0x106B0000,0x18480000,0x1EF30000,0x24570000,0x28650000,0x2B160000,0x2C6F0000,0x2C790000,0x2B470000,0x28F30000,0x259E0000,0x216E0000,0x1C8F0000,0x17310000,0x11860000,0x0BC10000,0x06170000,0x00BA0000,0xFBDD0000,0xF7AC0000,0xF44F0000,0xF1EA0000,0xF09C0000,0xF0790000,0xF1900000,0xF3E80000,0xF77E0000,0xFC4A0000,0x02370000,0x092E0000,0x110E0000,0x19AF0000,0x22E40000,0x2C7C0000,0x36420000,0x3FFF0000,0x497C0000,0x52810000,0x5AD70000,0x624B0000,0x68AD0000,0x6DD40000,0x71990000,0x73E10000,0x74950000,0x73A60000,0x71100000,0x6CD60000,0x67040000,0x5FAD0000,0x56EE0000,0x4CEA0000,0x41CD0000,0x35C50000,0x29070000,0x1BCC0000,0x0E4E0000,0x00CA0000,0xF37C0000,0xE69C0000,0xDA620000,0xCF040000,0xC4AE0000,0xBB8B0000,0xB3BC0000,0xAD5C0000,0xA87D0000,0xA5290000,0xA3630000,0xA3220000,0xA4590000,0xA6EF0000,0xAAC80000,0xAFBD0000,0xB5A40000,0xBC4F0000,0xC38B0000,0xCB220000,0xD2E00000,0xDA8E0000,0xE1F70000,0xE8EC0000,0xEF3C0000,0xF4C10000,0xF9560000,0xFCDF0000,0xFF470000,0x007F0000,0x00850000,0xFF5C0000,0xFD0B0000,0xF9A80000,0xF54B0000,0xF0170000,0xEA320000,0xE3C90000,0xDD0B0000,0xD62B0000,0xCF5F0000,0xC8DA0000,0xC2D30000,0xBD7A0000,0xB8FF0000,0xB58D0000,0xB3490000,0xB2510000,0xB2BE0000,0xB49F0000,0xB7FC0000,0xBCD60000,0xC3220000,0xCAD10000,0xD3C70000,0xDDE50000,0xE9030000,0xF4F20000,0x01800000,0x0E770000,0x1B9D0000,0x28B70000,0x35880000,0x41D70000,0x4D6C0000,0x58100000,0x61950000,0x69D00000,0x709C0000,0x75DE0000,0x79800000,0x7B750000,0x7BBB0000,0x7A570000,0x77550000,0x72CB0000,0x6CD70000,0x659E0000,0x5D490000,0x54090000,0x4A110000,0x3F980000,0x34D80000,0x2A090000,0x1F630000,0x151D0000,0x0B690000,0x02760000,0xFA6F0000,0xF3730000,0xEDA10000,0xE90B0000,0xE5BF0000,0xE3C00000,0xE30A0000,0xE38F0000,0xE53D0000,0xE7F80000,0xEB9D0000,0xF0050000,0xF5030000,0xFA680000,0x00000000,0x05980000,0x0AFD0000,0x0FFB0000,0x14630000,0x18080000};
14 //1 Sinus//
15 int Tablo[256] = {0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000};
16 printf("Debut Main\n\n");
17 UART_Device* uart0 = openUART(0);
18 FFT_Device* fft0 = openFFT(0);
19
20 printf("addr_fft: %x\n",(unsigned int)fft0);
21 printf("addr_uart: %x\n\n",(unsigned int)uart0);
22 printf("cfg_fft: %x\n",fft0->ConfigReg);
23 printf("cfg_uart: %x\n\n",uart0->ConfigReg);
24
25 while(1)
26 {
27 FftInput(Tablo,fft0);
28 /* for (i = 0 ; i < 256 ; i++)
29 {
30 sprintf(temp,"%x/in",Tablo[i]);
31 uartputs(uart0,temp);
32 }*/
33
34 FftOutput(Table,fft0);
35 for (i = 0 ; i < 128 ; i++)
36 {
37 sprintf(temp,"%x/out",Table[i]);
38 uartputs(uart0,temp);
39 }
40 }
41 return 0;
42 }
43
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24
25 #define FFT_Empty 0x00100
26 #define FFT_Full 0x01000
27
28
29 /*===================================================
30 T Y P E S D E F
31 ====================================================*/
32
33 struct FFT_Driver
34 {
35 int RWDataReg;
36 int ReadAddrReg;
37 int ConfigReg;
38 int Dummy1;
39 int Dummy0;
40 int WriteAddrReg;
41 };
42
43 typedef struct FFT_Driver FFT_Device;
44
45
46 /*===================================================
47 F U N C T I O N S
48 ====================================================*/
49
50 FFT_Device* openFFT(int count);
51 int FftInput(int Tbl[],FFT_Device*);
52 int FftOutput(int Tbl[],FFT_Device*);
53
54
55
56 #endif
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_fft_Driver
20 LIB = liblpp_fft_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #include "apb_fft_Driver.h"
23 #include "lpp_apb_functions.h"
24 #include <stdio.h>
25
26
27 FFT_Device* openFFT(int count)
28 {
29 FFT_Device* FFT0;
30 FFT0 = (FFT_Device*) apbgetdevice(LPP_FFT,VENDOR_LPP,count);
31 return FFT0;
32 }
33
34
35 int FftInput(int * Tbl,FFT_Device* fft)
36 {
37 int i;
38 printf("\nFftInput\n\n");
39
40 while((fft->ConfigReg & FFT_Full) != FFT_Full) // full a 0
41 {
42 printf("\nWrite\n\n");
43 for (i = 0 ; i < 256 ; i++)
44 {
45 fft->RWDataReg = Tbl[i];
46 if((fft->ConfigReg & FFT_Full) == FFT_Full) // full a 1
47 {
48 printf("\nBreak\n\n");
49 break;
50 }
51 }
52 }
53
54 printf("\nFULL\n\n");
55 return 0;
56 }
57
58
59 int FftOutput(int * Tbl, FFT_Device* fft)
60 {
61 int i;
62 printf("\nFftOutput\n\n");
63
64 while((fft->ConfigReg & FFT_Empty) != FFT_Empty) // empty a 0
65 {
66 printf("\nRead\n\n");
67 for (i = 0 ; i < 256 ; i++)
68 {
69 //printf("\noutFor%d\n\n",i);
70 Tbl[i] = fft->RWDataReg;
71 if((fft->ConfigReg & FFT_Empty) == FFT_Empty) // empty a 1
72 {
73 printf("\nBreak\n\n");
74 break;
75 }
76 }
77 }
78 printf("\nEMPTY\n\n");
79 return 0;
80 }
81
82
83
84
85
86
87
88
89
90
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1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24
25 #define FFT_Empty 0x00100
26 #define FFT_Full 0x01000
27
28
29 /*===================================================
30 T Y P E S D E F
31 ====================================================*/
32
33 struct FFT_Driver
34 {
35 int RWDataReg;
36 int ReadAddrReg;
37 int ConfigReg;
38 int Dummy1;
39 int Dummy0;
40 int WriteAddrReg;
41 };
42
43 typedef struct FFT_Driver FFT_Device;
44
45
46 /*===================================================
47 F U N C T I O N S
48 ====================================================*/
49
50 FFT_Device* openFFT(int count);
51 int FftInput(int Tbl[],FFT_Device*);
52 int FftOutput(int Tbl[],FFT_Device*);
53
54
55
56 #endif
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@@ -1,27 +1,28
1 #------------------------------------------------------------------------------
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
8 #-- (at your option) any later version.
9 #--
9 #--
10 #-- This program is distributed in the hope that it will be useful,
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
13 #-- GNU General Public License for more details.
14 #--
14 #--
15 #-- You should have received a copy of the GNU General Public License
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
18 #------------------------------------------------------------------------------
19
19
20
20
21
21
22 all:
22 all:
23 make all -C ScanAPB
23 make all -C ScanAPB
24 make all -C APB_lcd_ctrlr
24 make all -C APB_lcd_ctrlr
25 make all -C BenchFIFO
25 make all -C BenchFIFO
26 make all -C BenchUART
26 make all -C BenchUART
27 make all -C BenchFFT
27
28
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@@ -1,38 +1,40
1 #------------------------------------------------------------------------------
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
8 #-- (at your option) any later version.
9 #--
9 #--
10 #-- This program is distributed in the hope that it will be useful,
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
13 #-- GNU General Public License for more details.
14 #--
14 #--
15 #-- You should have received a copy of the GNU General Public License
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
18 #------------------------------------------------------------------------------
19
19
20 include ../rules.mk
20 include ../rules.mk
21
21
22
22
23
23
24 all:
24 all:
25 make all -C AMBA
25 make all -C AMBA
26 make all -C LCD
26 make all -C LCD
27 make all -C DAC
27 make all -C DAC
28 make all -C FIFO
28 make all -C FIFO
29 make all -C UART
29 make all -C UART
30 make all -C FFT
30
31
31
32
32 cleanall:
33 cleanall:
33 make clean -C AMBA
34 make clean -C AMBA
34 make clean -C LCD
35 make clean -C LCD
35 make clean -C DAC
36 make clean -C DAC
36 make clean -C FIFO
37 make clean -C FIFO
37 make clean -C UART
38 make clean -C UART
39 make clean -C FFT
38
40
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@@ -1,123 +1,107
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
31 use lpp.lpp_fft.all;
32 use lpp.lpp_memory.all;
32 use lpp.lpp_memory.all;
33 use work.fft_components.all;
33 use work.fft_components.all;
34
34
35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
36
36
37 entity APB_FFT is
37 entity APB_FFT is
38 generic (
38 generic (
39 pindex : integer := 0;
39 pindex : integer := 0;
40 paddr : integer := 0;
40 paddr : integer := 0;
41 pmask : integer := 16#fff#;
41 pmask : integer := 16#fff#;
42 pirq : integer := 0;
42 pirq : integer := 0;
43 abits : integer := 8;
43 abits : integer := 8;
44 Data_sz : integer := 32;
44 Data_sz : integer := 32;
45 Addr_sz : integer := 8;
45 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
46 addr_max_int : integer := 256);
47 port (
47 port (
48 clk : in std_logic; --! Horloge du composant
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic; --! Reset general du composant
49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
50 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
52 );
57 end APB_FFT;
53 end APB_FFT;
58
54
59
55
60 architecture ar_APB_FFT of APB_FFT is
56 architecture ar_APB_FFT of APB_FFT is
61
57
62 signal ReadEnable : std_logic;
58 signal ReadEnable : std_logic;
63 signal WriteEnable : std_logic;
59 signal WriteEnable : std_logic;
64 signal FlagEmpty : std_logic;
60 signal FlagEmpty : std_logic;
65 signal FlagFull : std_logic;
61 signal FlagFull : std_logic;
66 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
62 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
67 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
63 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
68 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
64 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
69 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
65 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
73 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
74
70
75 signal start : std_logic;
71 signal start : std_logic;
76 signal load : std_logic;
72 signal load : std_logic;
77 signal rdy : std_logic;
73 signal rdy : std_logic;
78 signal raz : std_logic;
79
80
74
81 begin
75 begin
82
76
83 APB : ApbDriver
77 APB : ApbDriver
84 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
78 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
86
80
87
81
88 Extremum : Flag_Extremum
82 Extremum : Flag_Extremum
89 port map(clk,raz,load,rdy,FlagFull,FlagEmpty);
83 port map(clk,rst,load,rdy,FlagFull,FlagEmpty);
90
84
91
85
92 DEVICE : CoreFFT
86 DEVICE : CoreFFT
93 generic map(
87 generic map(
94 LOGPTS => gLOGPTS,
88 LOGPTS => gLOGPTS,
95 LOGLOGPTS => gLOGLOGPTS,
89 LOGLOGPTS => gLOGLOGPTS,
96 WSIZE => gWSIZE,
90 WSIZE => gWSIZE,
97 TWIDTH => gTWIDTH,
91 TWIDTH => gTWIDTH,
98 DWIDTH => gDWIDTH,
92 DWIDTH => gDWIDTH,
99 TDWIDTH => gTDWIDTH,
93 TDWIDTH => gTDWIDTH,
100 RND_MODE => gRND_MODE,
94 RND_MODE => gRND_MODE,
101 SCALE_MODE => gSCALE_MODE,
95 SCALE_MODE => gSCALE_MODE,
102 PTS => gPTS,
96 PTS => gPTS,
103 HALFPTS => gHALFPTS,
97 HALFPTS => gHALFPTS,
104 inBuf_RWDLY => gInBuf_RWDLY)
98 inBuf_RWDLY => gInBuf_RWDLY)
105 port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
99 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
106
100
107 start <= not rst;
101 start <= not rst;
108
102
109 DataIn_re <= DataIn(31 downto 16);
103 DataIn_re <= DataIn(31 downto 16);
110 DataIn_im <= DataIn(15 downto 0);
104 DataIn_im <= DataIn(15 downto 0);
111 DataOut <= DataOut_re & DataOut_im;
105 DataOut <= DataOut_re & DataOut_im;
112
113
114 full <= FlagFull;
115 empty <= FlagEmpty;
116 WR <= WriteEnable;
117 RE <= ReadEnable;
118 flg_load <= load;
119 flg_rdy <= rdy;
120 RZ <= raz;
121
122
106
123 end ar_APB_FFT; No newline at end of file
107 end ar_APB_FFT;
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@@ -1,120 +1,72
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
25 use work.FFT_config.all;
26
26
27 --! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C
28
27 entity Flag_Extremum is
29 entity Flag_Extremum is
28 port(
30 port(
29 clk,raz : in std_logic;
31 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
30 load : in std_logic;
32 load : in std_logic; --! Signal en provenance de CoreFFT
31 y_rdy : in std_logic;
33 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
32 full : out std_logic;
34 full : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
33 empty : out std_logic
35 empty : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
34 );
36 );
35 end Flag_Extremum;
37 end Flag_Extremum;
36
38
39 --! @details Flags g�n�r�s a partir de signaux fourni par l'IP FFT d'actel
40
37 architecture ar_Flag_Extremum of Flag_Extremum is
41 architecture ar_Flag_Extremum of Flag_Extremum is
38
42
39 --type etat is (eA,eB,eC,e0,e1,e2);
43 begin
40 --signal ect : etat;
41
42 signal load_reg : std_logic;
43 signal y_rdy_reg : std_logic;
44
45 begin
46 process (clk,raz)
44 process (clk,raz)
47 begin
45 begin
48 if(raz='0')then
46 if(raz='0')then
49 full <= '1';
47 full <= '1';
50 empty <= '1';
48 empty <= '1';
51 -- ect <= eA;
49
52
50 elsif(clk' event and clk='1')then
53 elsif(clk' event and clk='1')then
54 -- load_reg <= load;
55 -- y_rdy_reg <= y_rdy;
56
51
57 if(load='1' and y_rdy='0')then
52 if(load='1' and y_rdy='0')then
58 full <= '0';
53 full <= '0';
59 empty <= '1';
54 empty <= '1';
60
55
61 elsif(y_rdy='1')then
56 elsif(y_rdy='1')then
62 full <= '1';
57 full <= '1';
63 empty <= '0';
58 empty <= '0';
64
59
65 else
60 else
66 full <= '1';
61 full <= '1';
67 empty <= '1';
62 empty <= '1';
68
63
69 end if;
64 end if;
70
71 -- case ect is
72
73 -- when eA =>
74 -- if(load_reg='0' and load='1')then
75 -- full <= '0';
76 -- ect <= eB;
77 -- end if;
78 --
79 -- when eB =>
80 -- if(load_reg='1' and load='0')then
81 -- ect <= eC;
82 -- end if;
83 --
84 -- when eC =>
85 -- if(load_reg='1' and load='0')then
86 -- full <= '1';
87 -- ect <= e0;
88 -- end if;
89
90 --===================================================================================
91
92 -- when e0 =>
93 -- if(load_reg='0' and load='1')then
94 -- full <= '0';
95 -- ect <= e1;
96 -- end if;
97 --
98 -- when e1 =>
99 -- if(load_reg='1' and load='0')then
100 -- full <= '1';
101 -- empty <= '0';
102 -- ect <= e2;
103 -- end if;
104 --
105 -- when e2 =>
106 -- if(y_rdy_reg='1' and y_rdy='0')then
107 -- empty <= '1';
108 -- ect <= e0;
109 -- end if;
110 --
111 --
112 -- end case;
113 end if;
65 end if;
114 end process;
66 end process;
115
67
116 end ar_Flag_Extremum;
68 end ar_Flag_Extremum;
117
69
118
70
119
71
120
72
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@@ -1,144 +1,143
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32
33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
34
33
35 package lpp_fft is
34 package lpp_fft is
36
35
37 component APB_FFT is
36 component APB_FFT is
38 generic (
37 generic (
39 pindex : integer := 0;
38 pindex : integer := 0;
40 paddr : integer := 0;
39 paddr : integer := 0;
41 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
42 pirq : integer := 0;
41 pirq : integer := 0;
43 abits : integer := 8;
42 abits : integer := 8;
44 Data_sz : integer := 32;
43 Data_sz : integer := 32;
45 Addr_sz : integer := 8;
44 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
45 addr_max_int : integer := 256);
47 port (
46 port (
48 clk : in std_logic; --! Horloge du composant
47 clk : in std_logic;
49 rst : in std_logic; --! Reset general du composant
48 rst : in std_logic;
50 full,empty : out std_logic;
49 apbi : in apb_slv_in_type;
51 WR,RE : out std_logic;
50 apbo : out apb_slv_out_type
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
51 );
57 end component;
52 end component;
58
53
59
54
60 component Flag_Extremum is
55 component Flag_Extremum is
61 port(
56 port(
62 clk,raz : in std_logic;
57 clk,raz : in std_logic;
63 load : in std_logic;
58 load : in std_logic;
64 y_rdy : in std_logic;
59 y_rdy : in std_logic;
65 full : out std_logic;
60 full : out std_logic;
66 empty : out std_logic
61 empty : out std_logic
67 );
62 );
68 end component;
63 end component;
69
64
65 --==============================================================|
66 --================== IP VHDL de la FFT actel ===================|
67 --================ non partag� dans la VHD_Lib =================|
68 --==============================================================|
70
69
71 component CoreFFT IS
70 component CoreFFT IS
72 GENERIC (
71 GENERIC (
73 LOGPTS : integer := gLOGPTS;
72 LOGPTS : integer := gLOGPTS;
74 LOGLOGPTS : integer := gLOGLOGPTS;
73 LOGLOGPTS : integer := gLOGLOGPTS;
75 WSIZE : integer := gWSIZE;
74 WSIZE : integer := gWSIZE;
76 TWIDTH : integer := gTWIDTH;
75 TWIDTH : integer := gTWIDTH;
77 DWIDTH : integer := gDWIDTH;
76 DWIDTH : integer := gDWIDTH;
78 TDWIDTH : integer := gTDWIDTH;
77 TDWIDTH : integer := gTDWIDTH;
79 RND_MODE : integer := gRND_MODE;
78 RND_MODE : integer := gRND_MODE;
80 SCALE_MODE : integer := gSCALE_MODE;
79 SCALE_MODE : integer := gSCALE_MODE;
81 PTS : integer := gPTS;
80 PTS : integer := gPTS;
82 HALFPTS : integer := gHALFPTS;
81 HALFPTS : integer := gHALFPTS;
83 inBuf_RWDLY : integer := gInBuf_RWDLY );
82 inBuf_RWDLY : integer := gInBuf_RWDLY );
84 PORT (
83 PORT (
85 clk,ifiStart,ifiNreset : IN std_logic;
84 clk,ifiStart,ifiNreset : IN std_logic;
86 ifiD_valid, ifiRead_y : IN std_logic;
85 ifiD_valid, ifiRead_y : IN std_logic;
87 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
86 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
88 ifoLoad, ifoPong : OUT std_logic;
87 ifoLoad, ifoPong : OUT std_logic;
89 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
88 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
90 ifoY_valid, ifoY_rdy : OUT std_logic);
89 ifoY_valid, ifoY_rdy : OUT std_logic);
91 END component;
90 END component;
92
91
93
92
94 component actar is
93 component actar is
95 port( DataA : in std_logic_vector(15 downto 0); DataB : in
94 port( DataA : in std_logic_vector(15 downto 0); DataB : in
96 std_logic_vector(15 downto 0); Mult : out
95 std_logic_vector(15 downto 0); Mult : out
97 std_logic_vector(31 downto 0);Clock : in std_logic) ;
96 std_logic_vector(31 downto 0);Clock : in std_logic) ;
98 end component;
97 end component;
99
98
100 component actram is
99 component actram is
101 port( DI : in std_logic_vector(31 downto 0); DO : out
100 port( DI : in std_logic_vector(31 downto 0); DO : out
102 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
101 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
103 WADDR : in std_logic_vector(6 downto 0); RADDR : in
102 WADDR : in std_logic_vector(6 downto 0); RADDR : in
104 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
103 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
105 std_logic) ;
104 std_logic) ;
106 end component;
105 end component;
107
106
108 component switch IS
107 component switch IS
109 GENERIC ( DWIDTH : integer := 32 );
108 GENERIC ( DWIDTH : integer := 32 );
110 PORT (
109 PORT (
111 clk, sel, validIn : IN std_logic;
110 clk, sel, validIn : IN std_logic;
112 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
111 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
113 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
112 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
114 validOut : OUT std_logic);
113 validOut : OUT std_logic);
115 END component;
114 END component;
116
115
117 component twid_rA IS
116 component twid_rA IS
118 GENERIC (LOGPTS : integer := 8;
117 GENERIC (LOGPTS : integer := 8;
119 LOGLOGPTS : integer := 3 );
118 LOGLOGPTS : integer := 3 );
120 PORT (clk : IN std_logic;
119 PORT (clk : IN std_logic;
121 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
120 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
122 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
121 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
123 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
122 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
124 END component;
123 END component;
125
124
126 component counter IS
125 component counter IS
127 GENERIC (
126 GENERIC (
128 WIDTH : integer := 7;
127 WIDTH : integer := 7;
129 TERMCOUNT : integer := 127 );
128 TERMCOUNT : integer := 127 );
130 PORT (
129 PORT (
131 clk, nGrst, rst, cntEn : IN std_logic;
130 clk, nGrst, rst, cntEn : IN std_logic;
132 tc : OUT std_logic;
131 tc : OUT std_logic;
133 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
132 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
134 END component;
133 END component;
135
134
136
135
137 component twiddle IS
136 component twiddle IS
138 PORT (
137 PORT (
139 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
138 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
140 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
139 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
141 END component;
140 END component;
142
141
143
142
144 end; No newline at end of file
143 end;
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@@ -1,159 +1,154
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31
31
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
32 --! Driver APB "G�n�rique" qui va faire le lien entre le bus Amba et la FIFO
33
33
34 entity ApbDriver is
34 entity ApbDriver is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
38 pmask : integer := 16#fff#;
38 pmask : integer := 16#fff#;
39 pirq : integer := 0;
39 pirq : integer := 0;
40 abits : integer := 8;
40 abits : integer := 8;
41 LPP_DEVICE : integer;
41 LPP_DEVICE : integer;
42 Data_sz : integer := 16;
42 Data_sz : integer := 16;
43 Addr_sz : integer := 8;
43 Addr_sz : integer := 8;
44 addr_max_int : integer := 256);
44 addr_max_int : integer := 256);
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 RZ : out std_logic;
49 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
50 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
51 FlagEmpty : in std_logic; --! Flag, M�moire vide
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
52 FlagFull : in std_logic; --! Flag, M�moire pleine
51 FlagFull : in std_logic; --! Flag, M�moire pleine
53 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en entr�e
54 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donn�es en sortie
55 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (�criture)
56 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
57 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
56 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
58 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
59 );
58 );
60 end ApbDriver;
59 end ApbDriver;
61
60
62 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
61 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
63
62
64 architecture ar_ApbDriver of ApbDriver is
63 architecture ar_ApbDriver of ApbDriver is
65
64
66 constant REVISION : integer := 1;
65 constant REVISION : integer := 1;
67
66
68 constant pconfig : apb_config_type := (
67 constant pconfig : apb_config_type := (
69 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
68 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
70 1 => apb_iobar(paddr, pmask));
69 1 => apb_iobar(paddr, pmask));
71
70
72 type DEVICE_ctrlr_Reg is record
71 type DEVICE_ctrlr_Reg is record
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
74 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
75 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
77 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
76 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
78 end record;
77 end record;
79
78
80 signal Rec : DEVICE_ctrlr_Reg;
79 signal Rec : DEVICE_ctrlr_Reg;
81 signal Rdata : std_logic_vector(31 downto 0);
80 signal Rdata : std_logic_vector(31 downto 0);
82
81
83 signal FlagRE : std_logic;
82 signal FlagRE : std_logic;
84 signal FlagWR : std_logic;
83 signal FlagWR : std_logic;
84
85 begin
85 begin
86
86
87 Rec.DEVICE_Cfg(0) <= FlagRE;
87 Rec.DEVICE_Cfg(0) <= FlagRE;
88 Rec.DEVICE_Cfg(1) <= FlagWR;
88 Rec.DEVICE_Cfg(1) <= FlagWR;
89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
90 Rec.DEVICE_Cfg(3) <= FlagFull;
90 Rec.DEVICE_Cfg(3) <= FlagFull;
91 Rz <= Rec.DEVICE_Cfg(4);
92
91
93 DataIn <= Rec.DEVICE_DataW;
92 DataIn <= Rec.DEVICE_DataW;
94 Rec.DEVICE_DataR <= DataOut;
93 Rec.DEVICE_DataR <= DataOut;
95 Rec.DEVICE_AddrW <= AddrIn;
94 Rec.DEVICE_AddrW <= AddrIn;
96 Rec.DEVICE_AddrR <= AddrOut;
95 Rec.DEVICE_AddrR <= AddrOut;
97
96
98
97
99
98
100 process(rst,clk)
99 process(rst,clk)
101 begin
100 begin
102 if(rst='0')then
101 if(rst='0')then
103 Rec.DEVICE_DataW <= (others => '0');
102 Rec.DEVICE_DataW <= (others => '0');
104 Rec.DEVICE_Cfg(4) <= '0';
105 FlagWR <= '0';
103 FlagWR <= '0';
106 FlagRE <= '0';
104 FlagRE <= '0';
107
105
108 elsif(clk'event and clk='1')then
106 elsif(clk'event and clk='1')then
109
107
110 --APB Write OP
108 --APB Write OP
111 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
109 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
112 case apbi.paddr(abits-1 downto 2) is
110 case apbi.paddr(abits-1 downto 2) is
113 when "000000" =>
111 when "000000" =>
114 FlagWR <= '1';
112 FlagWR <= '1';
115 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
113 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
116 when "000010" =>
117 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
118 when others =>
114 when others =>
119 null;
115 null;
120 end case;
116 end case;
121 else
117 else
122 FlagWR <= '0';
118 FlagWR <= '0';
123 end if;
119 end if;
124
120
125 --APB Read OP
121 --APB Read OP
126 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
122 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
123 case apbi.paddr(abits-1 downto 2) is
128 when "000000" =>
124 when "000000" =>
129 FlagRE <= '1';
125 FlagRE <= '1';
130 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
126 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
131 when "000001" =>
127 when "000001" =>
132 Rdata(31 downto 8) <= X"AAAAAA";
128 Rdata(31 downto 8) <= X"AAAAAA";
133 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
129 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
134 when "000101" =>
130 when "000101" =>
135 Rdata(31 downto 8) <= X"AAAAAA";
131 Rdata(31 downto 8) <= X"AAAAAA";
136 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
132 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
137 when "000010" =>
133 when "000010" =>
138 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
134 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
139 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
135 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
140 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
136 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
141 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
137 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
142 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
138 Rdata(31 downto 16) <= X"CCCC";
143 Rdata(31 downto 20) <= X"CCC";
144 when others =>
139 when others =>
145 Rdata <= (others => '0');
140 Rdata <= (others => '0');
146 end case;
141 end case;
147 else
142 else
148 FlagRE <= '0';
143 FlagRE <= '0';
149 end if;
144 end if;
150
145
151 end if;
146 end if;
152 apbo.pconfig <= pconfig;
147 apbo.pconfig <= pconfig;
153 end process;
148 end process;
154
149
155 apbo.prdata <= Rdata when apbi.penable = '1';
150 apbo.prdata <= Rdata when apbi.penable = '1';
156 WriteEnable <= FlagWR;
151 WriteEnable <= FlagWR;
157 ReadEnable <= FlagRE;
152 ReadEnable <= FlagRE;
158
153
159 end ar_ApbDriver; No newline at end of file
154 end ar_ApbDriver;
Show file before | Show file after | Hide comments
@@ -1,234 +1,232
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
31
33 package lpp_memory is
32 package lpp_memory is
34
33
35 --===========================================================|
34 --===========================================================|
36 --================= FIFOW SRAM FIFOR ========================|
35 --=================== FIFO Compl�te =========================|
37 --===========================================================|
36 --===========================================================|
38
37
39 component APB_FIFO is
38 component APB_FIFO is
40 generic (
39 generic (
41 pindex : integer := 0;
40 pindex : integer := 0;
42 paddr : integer := 0;
41 paddr : integer := 0;
43 pmask : integer := 16#fff#;
42 pmask : integer := 16#fff#;
44 pirq : integer := 0;
43 pirq : integer := 0;
45 abits : integer := 8;
44 abits : integer := 8;
46 Data_sz : integer := 16;
45 Data_sz : integer := 16;
47 Addr_sz : integer := 8;
46 Addr_sz : integer := 8;
48 addr_max_int : integer := 256);
47 addr_max_int : integer := 256);
49 port (
48 port (
50 clk : in std_logic;
49 clk : in std_logic;
51 rst : in std_logic;
50 rst : in std_logic;
52 apbi : in apb_slv_in_type;
51 apbi : in apb_slv_in_type;
53 apbo : out apb_slv_out_type
52 apbo : out apb_slv_out_type
54 );
53 );
55 end component;
54 end component;
56
55
57
56
58 component ApbDriver is
57 component ApbDriver is
59 generic (
58 generic (
60 pindex : integer := 0;
59 pindex : integer := 0;
61 paddr : integer := 0;
60 paddr : integer := 0;
62 pmask : integer := 16#fff#;
61 pmask : integer := 16#fff#;
63 pirq : integer := 0;
62 pirq : integer := 0;
64 abits : integer := 8;
63 abits : integer := 8;
65 LPP_DEVICE : integer;
64 LPP_DEVICE : integer;
66 Data_sz : integer := 16;
65 Data_sz : integer := 16;
67 Addr_sz : integer := 8;
66 Addr_sz : integer := 8;
68 addr_max_int : integer := 256);
67 addr_max_int : integer := 256);
69 port (
68 port (
70 clk : in std_logic;
69 clk : in std_logic;
71 rst : in std_logic;
70 rst : in std_logic;
72 RZ : out std_logic;
73 ReadEnable : in std_logic;
71 ReadEnable : in std_logic;
74 WriteEnable : in std_logic;
72 WriteEnable : in std_logic;
75 FlagEmpty : in std_logic;
73 FlagEmpty : in std_logic;
76 FlagFull : in std_logic;
74 FlagFull : in std_logic;
77 DataIn : out std_logic_vector(Data_sz-1 downto 0);
75 DataIn : out std_logic_vector(Data_sz-1 downto 0);
78 DataOut : in std_logic_vector(Data_sz-1 downto 0);
76 DataOut : in std_logic_vector(Data_sz-1 downto 0);
79 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
77 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
80 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
78 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
81 apbi : in apb_slv_in_type;
79 apbi : in apb_slv_in_type;
82 apbo : out apb_slv_out_type
80 apbo : out apb_slv_out_type
83 );
81 );
84 end component;
82 end component;
85
83
86
84
87 component Top_FIFO is
85 component Top_FIFO is
88 generic(
86 generic(
89 Data_sz : integer := 16;
87 Data_sz : integer := 16;
90 Addr_sz : integer := 8;
88 Addr_sz : integer := 8;
91 addr_max_int : integer := 256
89 addr_max_int : integer := 256
92 );
90 );
93 port(
91 port(
94 clk,raz : in std_logic; --! Horloge et reset general du composant
92 clk,raz : in std_logic;
95 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
93 flag_RE : in std_logic;
96 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
94 flag_WR : in std_logic;
97 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
95 Data_in : in std_logic_vector(Data_sz-1 downto 0);
98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
96 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
97 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
100 full : out std_logic; --! Flag, M�moire pleine
98 full : out std_logic;
101 empty : out std_logic; --! Flag, M�moire vide
99 empty : out std_logic;
102 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
100 Data_out : out std_logic_vector(Data_sz-1 downto 0)
103 );
101 );
104 end component;
102 end component;
105
103
106
104
107 component Fifo_Read is
105 component Fifo_Read is
108 generic(
106 generic(
109 Addr_sz : integer := 8;
107 Addr_sz : integer := 8;
110 addr_max_int : integer := 256);
108 addr_max_int : integer := 256);
111 port(
109 port(
112 clk : in std_logic;
110 clk : in std_logic;
113 raz : in std_logic;
111 raz : in std_logic;
114 flag_RE : in std_logic;
112 flag_RE : in std_logic;
115 Waddr : in std_logic_vector(addr_sz-1 downto 0);
113 Waddr : in std_logic_vector(addr_sz-1 downto 0);
116 empty : out std_logic;
114 empty : out std_logic;
117 Raddr : out std_logic_vector(addr_sz-1 downto 0)
115 Raddr : out std_logic_vector(addr_sz-1 downto 0)
118 );
116 );
119 end component;
117 end component;
120
118
121
119
122 component Fifo_Write is
120 component Fifo_Write is
123 generic(
121 generic(
124 Addr_sz : integer := 8;
122 Addr_sz : integer := 8;
125 addr_max_int : integer := 256);
123 addr_max_int : integer := 256);
126 port(
124 port(
127 clk : in std_logic;
125 clk : in std_logic;
128 raz : in std_logic;
126 raz : in std_logic;
129 flag_WR : in std_logic;
127 flag_WR : in std_logic;
130 Raddr : in std_logic_vector(addr_sz-1 downto 0);
128 Raddr : in std_logic_vector(addr_sz-1 downto 0);
131 full : out std_logic;
129 full : out std_logic;
132 Waddr : out std_logic_vector(addr_sz-1 downto 0)
130 Waddr : out std_logic_vector(addr_sz-1 downto 0)
133 );
131 );
134 end component;
132 end component;
135
133
136
134
137 component Link_Reg is
135 component Link_Reg is
138 generic(Data_sz : integer := 16);
136 generic(Data_sz : integer := 16);
139 port(
137 port(
140 clk,raz : in std_logic;
138 clk,raz : in std_logic;
141 Data_one : in std_logic_vector(Data_sz-1 downto 0);
139 Data_one : in std_logic_vector(Data_sz-1 downto 0);
142 Data_two : in std_logic_vector(Data_sz-1 downto 0);
140 Data_two : in std_logic_vector(Data_sz-1 downto 0);
143 flag_RE : in std_logic;
141 flag_RE : in std_logic;
144 flag_WR : in std_logic;
142 flag_WR : in std_logic;
145 empty : in std_logic;
143 empty : in std_logic;
146 Data_out : out std_logic_vector(Data_sz-1 downto 0)
144 Data_out : out std_logic_vector(Data_sz-1 downto 0)
147 );
145 );
148 end component;
146 end component;
149
147
150 --===========================================================|
148 --===========================================================|
151 --===================== FIFOW SRAM ==========================|
149 --================= Demi FIFO Ecriture ======================|
152 --===========================================================|
150 --===========================================================|
153
151
154 component APB_FifoWrite is
152 component APB_FifoWrite is
155 generic (
153 generic (
156 pindex : integer := 0;
154 pindex : integer := 0;
157 paddr : integer := 0;
155 paddr : integer := 0;
158 pmask : integer := 16#fff#;
156 pmask : integer := 16#fff#;
159 pirq : integer := 0;
157 pirq : integer := 0;
160 abits : integer := 8;
158 abits : integer := 8;
161 Data_sz : integer := 16;
159 Data_sz : integer := 16;
162 Addr_sz : integer := 8;
160 Addr_sz : integer := 8;
163 addr_max_int : integer := 256);
161 addr_max_int : integer := 256);
164 port (
162 port (
165 clk : in std_logic;
163 clk : in std_logic;
166 rst : in std_logic;
164 rst : in std_logic;
167 apbi : in apb_slv_in_type;
165 apbi : in apb_slv_in_type;
168 apbo : out apb_slv_out_type
166 apbo : out apb_slv_out_type
169 );
167 );
170 end component;
168 end component;
171
169
172
170
173 component Top_FifoWrite is
171 component Top_FifoWrite is
174 generic(
172 generic(
175 Data_sz : integer := 16;
173 Data_sz : integer := 16;
176 Addr_sz : integer := 8;
174 Addr_sz : integer := 8;
177 addr_max_int : integer := 256);
175 addr_max_int : integer := 256);
178 port(
176 port(
179 clk : in std_logic;
177 clk : in std_logic;
180 raz : in std_logic;
178 raz : in std_logic;
181 flag_RE : in std_logic;
179 flag_RE : in std_logic;
182 flag_WR : in std_logic;
180 flag_WR : in std_logic;
183 Data_in : in std_logic_vector(Data_sz-1 downto 0);
181 Data_in : in std_logic_vector(Data_sz-1 downto 0);
184 Raddr : in std_logic_vector(addr_sz-1 downto 0);
182 Raddr : in std_logic_vector(addr_sz-1 downto 0);
185 full : out std_logic;
183 full : out std_logic;
186 empty : out std_logic;
184 empty : out std_logic;
187 Waddr : out std_logic_vector(addr_sz-1 downto 0);
185 Waddr : out std_logic_vector(addr_sz-1 downto 0);
188 Data_out : out std_logic_vector(Data_sz-1 downto 0)
186 Data_out : out std_logic_vector(Data_sz-1 downto 0)
189 );
187 );
190 end component;
188 end component;
191
189
192 --===========================================================|
190 --===========================================================|
193 --===================== SRAM FIFOR ==========================|
191 --================== Demi FIFO Lecture ======================|
194 --===========================================================|
192 --===========================================================|
195
193
196 component APB_FifoRead is
194 component APB_FifoRead is
197 generic (
195 generic (
198 pindex : integer := 0;
196 pindex : integer := 0;
199 paddr : integer := 0;
197 paddr : integer := 0;
200 pmask : integer := 16#fff#;
198 pmask : integer := 16#fff#;
201 pirq : integer := 0;
199 pirq : integer := 0;
202 abits : integer := 8;
200 abits : integer := 8;
203 Data_sz : integer := 16;
201 Data_sz : integer := 16;
204 Addr_sz : integer := 8;
202 Addr_sz : integer := 8;
205 addr_max_int : integer := 256);
203 addr_max_int : integer := 256);
206 port (
204 port (
207 clk : in std_logic;
205 clk : in std_logic;
208 rst : in std_logic;
206 rst : in std_logic;
209 apbi : in apb_slv_in_type;
207 apbi : in apb_slv_in_type;
210 apbo : out apb_slv_out_type
208 apbo : out apb_slv_out_type
211 );
209 );
212 end component;
210 end component;
213
211
214
212
215 component Top_FifoRead is
213 component Top_FifoRead is
216 generic(
214 generic(
217 Data_sz : integer := 16;
215 Data_sz : integer := 16;
218 Addr_sz : integer := 8;
216 Addr_sz : integer := 8;
219 addr_max_int : integer := 256);
217 addr_max_int : integer := 256);
220 port(
218 port(
221 clk : in std_logic;
219 clk : in std_logic;
222 raz : in std_logic;
220 raz : in std_logic;
223 flag_RE : in std_logic;
221 flag_RE : in std_logic;
224 flag_WR : in std_logic;
222 flag_WR : in std_logic;
225 Data_in : in std_logic_vector(Data_sz-1 downto 0);
223 Data_in : in std_logic_vector(Data_sz-1 downto 0);
226 Waddr : in std_logic_vector(addr_sz-1 downto 0);
224 Waddr : in std_logic_vector(addr_sz-1 downto 0);
227 full : out std_logic;
225 full : out std_logic;
228 empty : out std_logic;
226 empty : out std_logic;
229 Raddr : out std_logic_vector(addr_sz-1 downto 0);
227 Raddr : out std_logic_vector(addr_sz-1 downto 0);
230 Data_out : out std_logic_vector(Data_sz-1 downto 0)
228 Data_out : out std_logic_vector(Data_sz-1 downto 0)
231 );
229 );
232 end component;
230 end component;
233
231
234 end;
232 end;
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