@@ -1,10 +1,20 | |||||
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1 | SCRIPTSDIR=scripts/ | |||
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2 | LIBDIR=lib/ | |||
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3 | BOARDSDIR=boards/ | |||
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4 | DESIGNSDIR=designs/ | |||
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5 | ||||
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6 | ||||
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7 | ||||
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8 | ||||
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9 | ||||
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10 | ||||
1 | all: help |
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11 | all: help | |
2 |
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12 | |||
3 | help: |
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13 | help: | |
4 | @echo |
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14 | @echo | |
5 | @echo " batch targets:" |
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15 | @echo " batch targets:" | |
6 | @echo |
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16 | @echo | |
7 | @echo " make Patch-GRLIB : install library into $(GRLIB)" |
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17 | @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)" | |
8 | @echo " make dist : create a tar file for using into an other computer" |
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18 | @echo " make dist : create a tar file for using into an other computer" | |
9 | @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer" |
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19 | @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer" | |
10 | @echo " make allGPL : add a GPL HEADER in all vhdl Files" |
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20 | @echo " make allGPL : add a GPL HEADER in all vhdl Files" | |
@@ -13,19 +23,19 help: | |||||
13 | @echo |
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23 | @echo | |
14 |
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24 | |||
15 | allGPL: |
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25 | allGPL: | |
16 |
sh |
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26 | sh $(SCRIPTSDIR)/GPL_Patcher.sh -R | |
17 |
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27 | |||
18 | init: allGPL |
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28 | init: allGPL | |
19 |
sh |
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29 | sh $(SCRIPTSDIR)/vhdlsynPatcher.sh | |
20 |
sh |
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30 | sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp | |
21 |
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31 | |||
22 |
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32 | |||
23 | Patch-GRLIB: init doc |
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33 | Patch-GRLIB: init doc | |
24 | sh patch.sh $(GRLIB) |
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34 | sh $(SCRIPTSDIR)/patch.sh $(GRLIB) | |
25 |
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35 | |||
26 |
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36 | |||
27 | dist: init |
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37 | dist: init | |
28 |
tar -cvzf ./../lpp-lib.tgz ./../ |
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38 | tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* | |
29 |
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39 | |||
30 | Patched-dist: Patch-GRLIB |
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40 | Patched-dist: Patch-GRLIB | |
31 | tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* |
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41 | tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* |
@@ -1,4 +1,5 | |||||
1 | patch VENDOR Ids |
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1 | x patch VENDOR Ids | |
2 | Write a README |
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2 | x Write a README | |
3 | add app_simple_diode |
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3 | x add app_simple_diode | |
4 | add LCD_16x2_DRIVER.vhd |
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4 | x add LCD_16x2_DRIVER.vhd | |
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5 | Write how_to_improve.pdf |
@@ -38,7 +38,7 PROJECT_NUMBER = 1.0 | |||||
38 | # If a relative path is entered, it will be relative to the location |
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38 | # If a relative path is entered, it will be relative to the location | |
39 | # where doxygen was started. If left blank the current directory will be used. |
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39 | # where doxygen was started. If left blank the current directory will be used. | |
40 |
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40 | |||
41 | OUTPUT_DIRECTORY = doc |
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41 | OUTPUT_DIRECTORY = ../../doc/ | |
42 |
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42 | |||
43 | # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create |
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43 | # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create | |
44 | # 4096 sub-directories (in 2 levels) under the output directory of each output |
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44 | # 4096 sub-directories (in 2 levels) under the output directory of each output |
@@ -121,23 +121,6 component LCD_CLK_GENERATOR is | |||||
121 | clk_1us : out STD_LOGIC); |
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121 | clk_1us : out STD_LOGIC); | |
122 | end component; |
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122 | end component; | |
123 |
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123 | |||
124 | component AMBA_LCD_16x2_DRIVER is |
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125 | Port ( reset : in STD_LOGIC; |
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126 | clk : in STD_LOGIC; |
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127 | Bp0 : in STD_LOGIC; |
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128 | Bp1 : in STD_LOGIC; |
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129 | Bp2 : in STD_LOGIC; |
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130 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
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131 | LCD_RS : out STD_LOGIC; |
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132 | LCD_RW : out STD_LOGIC; |
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133 | LCD_E : out STD_LOGIC; |
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134 | LCD_RET : out STD_LOGIC; |
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135 | LCD_CS1 : out STD_LOGIC; |
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136 | LCD_CS2 : out STD_LOGIC; |
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137 | SF_CE0 : out std_logic |
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138 | ); |
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139 | end component; |
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140 |
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141 | component LCD_16x2_ENGINE is |
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124 | component LCD_16x2_ENGINE is | |
142 | generic(OSC_freqKHz : integer := 50000); |
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125 | generic(OSC_freqKHz : integer := 50000); | |
143 | Port ( clk : in STD_LOGIC; |
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126 | Port ( clk : in STD_LOGIC; | |
@@ -151,23 +134,4 component LCD_16x2_ENGINE is | |||||
151 | end component; |
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134 | end component; | |
152 |
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135 | |||
153 |
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136 | |||
154 | component AMBA_LCD_16x2_DRIVER is |
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155 | Port ( reset : in STD_LOGIC; |
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156 | clk : in STD_LOGIC; |
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157 | Bp0 : in STD_LOGIC; |
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158 | Bp1 : in STD_LOGIC; |
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159 | Bp2 : in STD_LOGIC; |
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160 | LCD_data : out STD_LOGIC_VECTOR (7 downto 0); |
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161 | LCD_RS : out STD_LOGIC; |
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162 | LCD_RW : out STD_LOGIC; |
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163 | LCD_E : out STD_LOGIC; |
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164 | LCD_RET : out STD_LOGIC; |
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165 | LCD_CS1 : out STD_LOGIC; |
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166 | LCD_CS2 : out STD_LOGIC; |
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167 | SF_CE0 : out std_logic |
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168 | ); |
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169 | end component; |
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170 |
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171 |
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172 |
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173 | end; |
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137 | end; |
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