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Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

cleaned file tree, added README
alexis -
r7:de2005838214 default
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@@ -1,10 +1,20
1 SCRIPTSDIR=scripts/
2 LIBDIR=lib/
3 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
5
6
7
8
9
10
1 11 all: help
2 12
3 13 help:
4 14 @echo
5 15 @echo " batch targets:"
6 16 @echo
7 @echo " make Patch-GRLIB : install library into $(GRLIB)"
17 @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)"
8 18 @echo " make dist : create a tar file for using into an other computer"
9 19 @echo " make Patched-dist : create a tar file for with a patched grlib for using into an other computer"
10 20 @echo " make allGPL : add a GPL HEADER in all vhdl Files"
@@ -13,19 +23,19 help:
13 23 @echo
14 24
15 25 allGPL:
16 sh lib/GPL_Patcher.sh -R
26 sh $(SCRIPTSDIR)/GPL_Patcher.sh -R
17 27
18 28 init: allGPL
19 sh lib/lpp/vhdlsynPatcher.sh
20 sh lib/lpp/makeDirs.sh lib/lpp
29 sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
30 sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp
21 31
22 32
23 33 Patch-GRLIB: init doc
24 sh patch.sh $(GRLIB)
34 sh $(SCRIPTSDIR)/patch.sh $(GRLIB)
25 35
26 36
27 37 dist: init
28 tar -cvzf ./../lpp-lib.tgz ./../lib_lpp/*
38 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
29 39
30 40 Patched-dist: Patch-GRLIB
31 41 tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/*
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@@ -1,4 +1,5
1 patch VENDOR Ids
2 Write a README
3 add app_simple_diode
4 add LCD_16x2_DRIVER.vhd
1 x patch VENDOR Ids
2 x Write a README
3 x add app_simple_diode
4 x add LCD_16x2_DRIVER.vhd
5 Write how_to_improve.pdf
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@@ -38,7 +38,7 PROJECT_NUMBER = 1.0
38 38 # If a relative path is entered, it will be relative to the location
39 39 # where doxygen was started. If left blank the current directory will be used.
40 40
41 OUTPUT_DIRECTORY = doc
41 OUTPUT_DIRECTORY = ../../doc/
42 42
43 43 # If the CREATE_SUBDIRS tag is set to YES, then doxygen will create
44 44 # 4096 sub-directories (in 2 levels) under the output directory of each output
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@@ -121,23 +121,6 component LCD_CLK_GENERATOR is
121 121 clk_1us : out STD_LOGIC);
122 122 end component;
123 123
124 component AMBA_LCD_16x2_DRIVER is
125 Port ( reset : in STD_LOGIC;
126 clk : in STD_LOGIC;
127 Bp0 : in STD_LOGIC;
128 Bp1 : in STD_LOGIC;
129 Bp2 : in STD_LOGIC;
130 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
131 LCD_RS : out STD_LOGIC;
132 LCD_RW : out STD_LOGIC;
133 LCD_E : out STD_LOGIC;
134 LCD_RET : out STD_LOGIC;
135 LCD_CS1 : out STD_LOGIC;
136 LCD_CS2 : out STD_LOGIC;
137 SF_CE0 : out std_logic
138 );
139 end component;
140
141 124 component LCD_16x2_ENGINE is
142 125 generic(OSC_freqKHz : integer := 50000);
143 126 Port ( clk : in STD_LOGIC;
@@ -151,23 +134,4 component LCD_16x2_ENGINE is
151 134 end component;
152 135
153 136
154 component AMBA_LCD_16x2_DRIVER is
155 Port ( reset : in STD_LOGIC;
156 clk : in STD_LOGIC;
157 Bp0 : in STD_LOGIC;
158 Bp1 : in STD_LOGIC;
159 Bp2 : in STD_LOGIC;
160 LCD_data : out STD_LOGIC_VECTOR (7 downto 0);
161 LCD_RS : out STD_LOGIC;
162 LCD_RW : out STD_LOGIC;
163 LCD_E : out STD_LOGIC;
164 LCD_RET : out STD_LOGIC;
165 LCD_CS1 : out STD_LOGIC;
166 LCD_CS2 : out STD_LOGIC;
167 SF_CE0 : out std_logic
168 );
169 end component;
170
171
172
173 137 end;
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@@ -1,6 +1,7
1 1 amba_lcd_16x2_ctrlr.vhd
2 2 FRAME_CLK.vhd
3 3 LCD_16x2_CFG.vhd
4 LCD_16x2_DRVR.vhd
4 5 LCD_16x2_ENGINE.vhd
5 6 LCD_2x16_DRIVER.vhd
6 7 LCD_CLK_GENERATOR.vhd
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