HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r359:ddd83014c899

update

pellion -

r359:ddd83014c899 JC

parent child

Context file:

r359:ddd83014c899

Collapse all files

designs/Validation_LFR_SpectralMatrix/MS_control.vhd created 644 +129 0

@@ -0,0 +1,129
	1	LIBRARY IEEE;
	2	USE IEEE.std_logic_1164.ALL;
	3	USE IEEE.numeric_std.ALL;
	4
	5	ENTITY MS_control IS
	6	PORT (
	7	clk : IN STD_LOGIC;
	8	rstn : IN STD_LOGIC;
	9
	10	-- IN
	11	fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	12	fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
	13	fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	14	fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
	15	fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	16	fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
	17	-- OUT
	18	fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
	19	fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
	20	fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
	21	-- OUT
	22	correlation_start : OUT STD_LOGIC;
	23	correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
	24	correlation_done : IN STD_LOGIC
	25	);
	26	END MS_control;
	27
	28	ARCHITECTURE beh OF MS_control IS
	29
	30	TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
	31	SIGNAL state : fsm_control_MS;
	32
	33	SUBTYPE fifo_pointer IS RANGE 0 TO 4;
	34	SIGNAL fifo_1 : fifo_pointer;
	35	SIGNAL fifo_2 : fifo_pointer;
	36
	37	SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
	38	SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
	39
	40	BEGIN -- beh
	41
	42	fifo_in_lock <= fifo_in_lock_s;
	43	fifo_in_reuse <= fifo_in_reuse_s;
	44
	45	PROCESS (clk, rstn)
	46	BEGIN
	47	IF rstn = '0' THEN
	48	state <= WAIT_DATA;
	49	fifo_1 <= 0;
	50	fifo_2 <= 0;
	51	fifo_in_lock_s <= (OTHERS => '0');
	52	fifo_in_reuse_s <= (OTHERS => '0');
	53	correlation_start <= '0';
	54	correlation_auto <= '0';
	55	ELSIF clk'event AND clk = '1' THEN
	56	CASE state IS
	57	WHEN WAIT_DATA =>
	58	fifo_in_reuse_s <= (OTHERS => '0');
	59	IF fifo_in_full[fifo_1] = '1' AND fifo_in_full[fifo_2] = '1' THEN
	60	fifo_in_lock_s(fifo_1) <= '1';
	61	fifo_in_lock_s(fifo_2) <= '1';
	62	correlation_start <= '1';
	63	IF fifo_1 = fifo_2 THEN
	64	correlation_auto <= '1';
	65	END IF;
	66	state <= CORRELATION_ONGOING;
	67	END IF;
	68
	69	WHEN CORRELATION_ONGOING =>
	70	correlation_start <= '0';
	71	correlation_auto <= '0';
	72	IF correlation_done = '1' THEN
	73	state <= WAIT_DATA;
	74	IF fifo_2 = 4 THEN
	75	fifo_in_lock_s(fifo_1) <= '0';
	76	IF fifo_1 = 4 THEN
	77	fifo_1 <= 0;
	78	fifo_2 <= 0;
	79	ELSE
	80	fifo_in_reuse_s(fifo_2) <= '1';
	81	fifo_1 <= fifo_1 + 1;
	82	fifo_2 <= fifo_1 + 1;
	83	END IF;
	84	ELSE
	85	fifo_in_reuse_s(fifo_2) <= '1';
	86	fifo_in_reuse_s(fifo_1) <= '1';
	87	fifo_2 <= fifo_2 + 1;
	88	END IF;
	89	END IF;
	90
	91	WHEN OTHERS => NULL;
	92	END CASE;
	93	END IF;
	94	END PROCESS;
	95
	96
	97	fifo_out_data(31 DOWNTO 0) <= fifo_in_data(311-1 DOWNTO 320) WHEN fifo_1 = 0 ELSE
	98	fifo_in_data(322-1 DOWNTO 321) WHEN fifo_1 = 1 ELSE
	99	fifo_in_data(323-1 DOWNTO 322) WHEN fifo_1 = 2 ELSE
	100	fifo_in_data(324-1 DOWNTO 323) WHEN fifo_1 = 3 ELSE
	101	fifo_in_data(325-1 DOWNTO 324);-- WHEN fifo_1 = 4
	102
	103
	104	fifo_out_data(63 DOWNTO 32) <= fifo_in_data(311-1 DOWNTO 320) WHEN fifo_2 = 0 ELSE
	105	fifo_in_data(322-1 DOWNTO 321) WHEN fifo_2 = 1 ELSE
	106	fifo_in_data(323-1 DOWNTO 322) WHEN fifo_2 = 2 ELSE
	107	fifo_in_data(324-1 DOWNTO 323) WHEN fifo_2 = 3 ELSE
	108	fifo_in_data(325-1 DOWNTO 324);-- WHEN fifo_2 = 4
	109
	110	fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
	111	fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
	112	fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
	113	fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
	114	fifo_in_empty(4);
	115
	116	fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
	117	fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
	118	fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
	119	fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
	120	fifo_in_empty(4);
	121
	122
	123	all_fifo: FOR I IN 0 TO 4 GENERATE
	124	fifo_in_ren(I) <= fifo_out_ren(I) WHEN fifo_1 = I ELSE
	125	fifo_out_ren(I) WHEN fifo_2 = I ELSE
	126	'1';
	127	END GENERATE all_fifo;
	128
	129	END beh;

designs/Validation_LFR_SpectralMatrix/Makefile +1 0

             VHDLIB=../..
             SCRIPTSDIR=$(VHDLIB)/scripts/
             GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
             TOP=TB
             CMD_VLIB=vlib
             CMD_VMAP=vmap
             CMD_VCOM=@vcom -quiet -93 -work
             ##################  project specific targets ##########################
             all:
             	@echo "make vsim"
             	@echo "make libs"
             	@echo "make clean"
             	@echo "make vcom_grlib vcom_lpp vcom_tb"
             run:
             	@vsim work.TB -do run.do
             #	@vsim work.TB
             #	@vsim lpp.lpp_lfr_ms
             vsim:   libs vcom run
             libs:
             	@$(CMD_VLIB) modelsim
             	@$(CMD_VMAP) modelsim modelsim
             	@$(CMD_VLIB) modelsim/techmap
             	@$(CMD_VMAP) techmap modelsim/techmap
             	@$(CMD_VLIB) modelsim/grlib
             	@$(CMD_VMAP) grlib modelsim/grlib
             	@$(CMD_VLIB) modelsim/gaisler
             	@$(CMD_VMAP) gaisler modelsim/gaisler
             	@$(CMD_VLIB) modelsim/work
             	@$(CMD_VMAP) work modelsim/work
             	@$(CMD_VLIB) modelsim/lpp
             	@$(CMD_VMAP) lpp modelsim/lpp
             	@echo "libs done"
             clean:
             	@rm -Rf modelsim
             	@rm -Rf modelsim.ini
             	@rm -Rf *~
             	@rm -Rf transcript
             	@rm -Rf wlft*
             	@rm -Rf *.wlf
             	@rm -Rf vish_stacktrace.vstf
             	@rm -Rf libs.do
             vcom: vcom_grlib vcom_techmap vcom_gaisler vcom_lpp vcom_tb
             vcom_tb:
             	$(CMD_VCOM) lpp  lpp_memory.vhd
             	$(CMD_VCOM) lpp  lppFIFOxN.vhd
             	$(CMD_VCOM) lpp  lpp_FIFO.vhd
             	$(CMD_VCOM) lpp  spectral_matrix_package.vhd
             	$(CMD_VCOM) lpp  spectral_matrix_switch_f0.vhd
             	$(CMD_VCOM) lpp  spectral_matrix_time_managment.vhd
             	$(CMD_VCOM) lpp  lpp_lfr_ms.vhd
             	$(CMD_VCOM) work TB.vhd
             	@echo "vcom done"
             vcom_grlib:
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/version.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config_types.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/config.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/stdio.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/stdlib/testlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/ftlib/mtie_ftlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/util/util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/sparc_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/sparc/cpu_disas.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/multlib.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/modgen/leaves.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/devices.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/defmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbctrl.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ahbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/apbmon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/ambamon.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/dma2ahb_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/amba/amba_tp.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv_pkg.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_util.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_mst.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_slv.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahbs.vhd
             	$(CMD_VCOM) grlib $(GRLIB)/lib/grlib/atf/at_ahb_ctrl.vhd
             	@echo "vcom grlib done"
             vcom_gaisler:
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/arith.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/mul32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/arith/div32.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/memctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdctrl64.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/sdmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/srctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ssrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrlc.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrl.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlc.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsrctrl8.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdmctrlx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrlcx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftmctrl.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/memctrl/ftsdctrl64.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpu/mtie_grlfpu.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpc/mtie_grlfpc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/grlfpcft/mtie_grlfpcft.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuconf# ig.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmuiface.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/libmmu.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlbcam.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulrue.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmulru.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutlb.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmutw.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/srmmu/mmu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/leon3.vhd
             # #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libiu.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/libcache.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/tbufmem.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/dsu3_2x.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xsync.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/clk2xqual.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3/grfpushwx.vhd
             # 	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/libproc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/cachemem.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_icache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_dcache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_acache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mmu_cache.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/iu3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/mfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grlfpwx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/proc3.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3s.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3cg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/grfpwxsh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3v1/leon3sh.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/leon3ftv2/mtie_leon3ftv2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqmp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/irqmp/irqamp2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mod.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_mc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/canmux.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_rd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/can_oc_core.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/can/grcan.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/misc.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/rstgen.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gptimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbdpram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbtrace_mmb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpio.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ftahbram2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbstat.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/logan.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbps2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom_package.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/charrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/apbvga.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb2ahb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbbridge.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/svgactrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grfifo.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gradcdac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grsysmon.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/gracectrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgpreg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbmst2.vhd
             ##	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/memscrub.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahb_mst_iface.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grgprbank.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grclkgate2x.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grtimer.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grpulse.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/grversion.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/misc/ahbfrom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbp.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/ambatest/ahbtbm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/net/net.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/uart.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/libdcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/apbuart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/dcom_uart.vhd
             # $(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/uart/ahbuart.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sim.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sramft.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/sram16.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/phy.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ahbrep.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/delay_wire.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/pwm_check.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/ramback.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/zbtssram.vhd
             	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/sim/slavecheck.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/libjtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagcom.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/ahbjtag_bsd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanctrl.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregs.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/bscanregsbd.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/jtag/jtagtst.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/ethernet_mac.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/greth_gbit_mb.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/grethm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/greth/rgmii.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/spacewire.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspwm.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw2_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/spacewire/grspw_phy.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/gr1553b_pads.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/gr1553b/simtrans1553.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandpkg.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrlx.vhd
             #	$(CMD_VCOM) gaisler $(GRLIB)/lib/gaisler/nand/nandfctrl.vhd
             	@echo "vcom gaisler done"
             vcom_techmap:
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/gencomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/gencomp/netcomp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/memory_inferred.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/tap_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/mul_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddr_phy_inferred.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/ddrphy_datapath.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/inferred/sim_pll.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/buffer_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/clkgen_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/ddr_proasic3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/memory_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/pads_apa3e.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/proasic3e/tap_proasic3e.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allclkgen.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allddr.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmem.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allmul.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/allpads.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/alltap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkgen.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkmux.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkand.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_ireg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddr_oreg.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ddrphy.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram64.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2p.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_dp.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncfifo.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/regfile_3p.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/tap.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techbuf.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/nandtree.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/clkpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iodpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/lvds_combo.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/odpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ds.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/toutpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/skew_outpad.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grspwc2_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grlfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grfpw4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/leon4_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mul_61x61.vhd
             	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/cpu_disas_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/ringosc.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/corepcif_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/pci_arb_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grpci2_phy_net.vhd
             #	$(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/system_monitor.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/grgates.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/inpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/outpad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/iopad_ddr.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram256bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram128.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram156bw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/techmult.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/spictrl_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/scanreg.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncrambw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/syncram_2pbw.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/obt1553_net.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/sdram_phy.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/from.vhd
             # $(CMD_VCOM) techmap $(GRLIB)/lib/techmap/maps/mtie_maps.vhd
             	@echo "vcom techmap done"
             vcom_lpp:
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./lpp_amba/lpp_amba.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/iir_filter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/fft_components.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/dsp/iir_filter/FILTERcfg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_dma/lpp_dma_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/lpp_matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ALU_Driver.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/ReUse_CTRLR.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Dispatch.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/DriveInputs.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/GetResult.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/MatriceSpectrale.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/Matrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/TopSpecMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
+            	$(CMD_VCOM) lpp  lpp_memory.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
             	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
             	@echo "vcom lpp done"
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_amba/apb_devices_list.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_purpose.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ADDRcntr.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/ALU.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Adder.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_Divider2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clk_divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_CONTROLER.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MAC_REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUX2.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/MUXN.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Multiplier.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/REG.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_FF.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Shifter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/TwoComplementer.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/Clock_Divider.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_to_level.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/lpp_front_positive_detection.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/SYNC_VALID_BIT.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/RR_Arbiter_4.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/general_purpose/general_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/lfr_time_management.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/fine_time_counter.vhd
             # 	$(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lfr_time_management/coarse_time_counter.vhd
             # 	@echo "vcom lpp done"
             #include Makefile_vcom_lpp

designs/Validation_LFR_SpectralMatrix/lpp_lfr_ms.vhd +4 0

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
                 Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 dma_valid       : OUT STD_LOGIC;
                 dma_valid_burst : OUT STD_LOGIC;
                 dma_ren         : IN  STD_LOGIC;
                 dma_done        : IN  STD_LOGIC;
                 -- Reg out
                 ready_matrix_f0_0             : OUT STD_LOGIC;
                 ready_matrix_f0_1             : OUT STD_LOGIC;
                 ready_matrix_f1               : OUT STD_LOGIC;
                 ready_matrix_f2               : OUT STD_LOGIC;
                 error_anticipating_empty_fifo : OUT STD_LOGIC;
                 error_bad_component_error     : OUT STD_LOGIC;
                 debug_reg                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0_0             : IN STD_LOGIC;
                 status_ready_matrix_f0_1             : IN STD_LOGIC;
                 status_ready_matrix_f1               : IN STD_LOGIC;
                 status_ready_matrix_f2               : IN STD_LOGIC;
                 status_error_anticipating_empty_fifo : IN STD_LOGIC;
                 status_error_bad_component_error     : IN STD_LOGIC;
                 config_active_interruption_onNewMatrix : IN STD_LOGIC;
                 config_active_interruption_onError     : IN STD_LOGIC;
                 addr_matrix_f0_0                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 matrix_time_f0_0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f1   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f2   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
               SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
               SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read            : STD_LOGIC;
               SIGNAL fft_pong            : STD_LOGIC;
               SIGNAL fft_data_im         : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re         : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid      : STD_LOGIC;
               SIGNAL fft_ready           : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty : STD_LOGIC;
               SIGNAL current_fifo_locked : STD_LOGIC;
               SIGNAL current_fifo_full : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData      : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData  : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL HEAD_SM_Param       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL HEAD_WorkFreq       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL HEAD_SM_Wen         : STD_LOGIC;
               SIGNAL HEAD_Valid          : STD_LOGIC;
               SIGNAL HEAD_Data           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL HEAD_Empty          : STD_LOGIC;
               SIGNAL HEAD_Read           : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_ReUse    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL DMA_Header          : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL DMA_Header_Val      : STD_LOGIC;
               SIGNAL DMA_Header_Ack      : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
               SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_update_f0_A : STD_LOGIC;
               SIGNAL time_update_f0_B : STD_LOGIC;
               SIGNAL time_update_f1   : STD_LOGIC;
               SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
               -----------------------------------------------------------------------------
             BEGIN
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 16,
                   Addr_sz      => 8,
                   FifoCnt      => 5)
                 PORT MAP (
                   clk   => clk,
                   rstn  => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f0_A_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_A_ren,
                   rdata       => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 16,
                   Addr_sz      => 8,
                   FifoCnt      => 5)
                 PORT MAP (
                   clk   => clk,
                   rstn  => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 16,
                   Addr_sz      => 8,
                   FifoCnt      => 5)
                 PORT MAP (
                   clk   => clk,
                   rstn  => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f1_wen,
                   wdata       => sample_f1_wdata,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full = "00000" THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 16,
                   Addr_sz      => 8,
                   FifoCnt      => 5)
                 PORT MAP (
                   clk   => clk,
                   rstn  => rstn,
                   ReUse => (OTHERS => '0'),
                   wen         => sample_f2_wen,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
               sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
                   next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
                   next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= sample_valid_r AND sample_load;
               sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
                              sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
                              sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
                              sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               CoreFFT_1 : CoreFFT
                 GENERIC MAP (
                   LOGPTS      => gLOGPTS,
                   LOGLOGPTS   => gLOGLOGPTS,
                   WSIZE       => gWSIZE,
                   TWIDTH      => gTWIDTH,
                   DWIDTH      => gDWIDTH,
                   TDWIDTH     => gTDWIDTH,
                   RND_MODE    => gRND_MODE,
                   SCALE_MODE  => gSCALE_MODE,
                   PTS         => gPTS,
                   HALFPTS     => gHALFPTS,
                   inBuf_RWDLY => gInBuf_RWDLY)
                 PORT MAP (
                   clk       => clk,
                   ifiStart  => '1',
                   ifiNreset => rstn,
                   ifiD_valid => sample_valid,       -- IN
                   ifiRead_y  => fft_read,
                   ifiD_im    => (OTHERS => '0'),    -- IN
                   ifiD_re    => sample_data,        -- IN
                   ifoLoad    => sample_load,        -- IN
                   ifoPong    => fft_pong,
                   ifoY_im    => fft_data_im,
                   ifoY_re    => fft_data_re,
                   ifoY_valid => fft_data_valid,
                   ifoY_rdy   => fft_ready);
               -----------------------------------------------------------------------------
               -- in   fft_data_im & fft_data_re
               -- in   fft_data_valid
               -- in   fft_ready
               -- out  fft_read
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load <= "00001";
                 ELSIF clk'event AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full  <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
                   MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                                AND state_fsm_load_MS_memory = LOAD_FIFO
                                                AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'event AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -- out SM_MEM_IN_wData
               -- out SM_MEM_IN_wen
               -- out SM_MEM_IN_Full
               -- out SM_MEM_IN_locked
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --Linker_FFT_1 : Linker_FFT
               --  GENERIC MAP (
               --    Data_sz => 16,
               --    NbData  => 256)
               --  PORT MAP (
               --    clk  => clk,
               --    rstn => rstn,
               --    Ready => fft_ready,
               --    Valid => fft_data_valid,
               --    Full => MEM_IN_SM_Full,
               --    Data_re => fft_data_re,
               --    Data_im => fft_data_im,
               --    Read    => fft_read,
               --    Write => MEM_IN_SM_wen,
               --    ReUse => fft_linker_ReUse,
               --    DATA  => MEM_IN_SM_wData);
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 32,               --16,
                   Addr_sz      => 7,                --8
                   FifoCnt      => 5)
                 PORT MAP (
                   clk => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren   => MEM_IN_SM_ren,
                   rdata => MEM_IN_SM_rData,
                   full  => MEM_IN_SM_Full,
                   empty => MEM_IN_SM_Empty);
               all_lock: FOR I IN 4 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     MEM_IN_SM_locked(I) <= '0';
                   ELSIF clk'event AND clk = '1' THEN
                     MEM_IN_SM_locked(I) <=   MEM_IN_SM_Full(I) OR  MEM_IN_SM_locked(I);  -- TODO
                   END IF;
                 END PROCESS;
               END GENERATE all_lock;
+              -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               SM0 : MatriceSpectrale
                 GENERIC MAP (
                   Input_SZ  => 16,
                   Result_SZ => 32)
                 PORT MAP (
                   clkm => clk,
                   rstn => rstn,
                   FifoIN_Full => MEM_IN_SM_Full,
                   Data_IN     => MEM_IN_SM_rData(79 DOWNTO 0),
                   Read        => MEM_IN_SM_ren,
                   ReUse       => MEM_IN_SM_ReUse,
                   SetReUse => fft_linker_ReUse,
                   Valid     => HEAD_Valid,
                   ACK       => DMA_Header_Ack,
                   SM_Write  => HEAD_SM_Wen,
                   FlagError => OPEN,
                   Statu     => HEAD_SM_Param,
                   Write     => MEM_OUT_SM_Write,
                   Data_OUT  => MEM_OUT_SM_Data_in);
               -----------------------------------------------------------------------------
               Mem_Out_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech         => 0,
                   Mem_use      => Mem_use,
                   Data_sz      => 32,
                   Addr_sz      => 8,
                   FifoCnt      => 2)
                 PORT MAP (
                   clk => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   wen   => MEM_OUT_SM_Write,
                   wdata => MEM_OUT_SM_Data_in,
                   ren   => MEM_OUT_SM_Read,
                   rdata => MEM_OUT_SM_Data_out,
                   full  => MEM_OUT_SM_Full,
                   empty => MEM_OUT_SM_Empty);
               -----------------------------------------------------------------------------
               Head0 : HeaderBuilder
                 GENERIC MAP (
                   Data_sz => 32)
                 PORT MAP (
                   clkm => clk,
                   rstn => rstn,
                   Statu        => HEAD_SM_Param,
                   Matrix_Type  => HEAD_WorkFreq,    -- TODO IN
                   Matrix_Write => HEAD_SM_Wen,
                   Valid        => HEAD_Valid,
                   dataIN  => MEM_OUT_SM_Data_out,
                   emptyIN => MEM_OUT_SM_Empty,
                   RenOUT  => MEM_OUT_SM_Read,
                   dataOUT  => HEAD_Data,
                   emptyOUT => HEAD_Empty,
                   RenIN    => HEAD_Read,
                   header     => DMA_Header,
                   header_val => DMA_Header_Val,
                   header_ack => DMA_Header_Ack);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   data_time => dma_time,
                   fifo_data  => HEAD_Data,
                   fifo_empty => HEAD_Empty,
                   fifo_ren   => HEAD_Read,
                   header     => DMA_Header,
                   header_val => DMA_Header_Val,
                   header_ack => DMA_Header_Ack,
                   dma_addr        => dma_addr,
                   dma_data        => dma_data,
                   dma_valid       => dma_valid,
                   dma_valid_burst => dma_valid_burst,
                   dma_ren         => dma_ren,
                   dma_done        => dma_done,
                   ready_matrix_f0_0                      => ready_matrix_f0_0,
                   ready_matrix_f0_1                      => ready_matrix_f0_1,
                   ready_matrix_f1                        => ready_matrix_f1,
                   ready_matrix_f2                        => ready_matrix_f2,
                   error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
                   error_bad_component_error              => error_bad_component_error,
                   debug_reg                              => debug_reg,
                   status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
                   status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
                   status_ready_matrix_f1                 => status_ready_matrix_f1,
                   status_ready_matrix_f2                 => status_ready_matrix_f2,
                   status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
                   status_error_bad_component_error       => status_error_bad_component_error,
                   config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
                   config_active_interruption_onError     => config_active_interruption_onError,
                   addr_matrix_f0_0                       => addr_matrix_f0_0,
                   addr_matrix_f0_1                       => addr_matrix_f0_1,
                   addr_matrix_f1                         => addr_matrix_f1,
                   addr_matrix_f2                         => addr_matrix_f2,
                   matrix_time_f0_0 => matrix_time_f0_0,
                   matrix_time_f0_1 => matrix_time_f0_1,
                   matrix_time_f1   => matrix_time_f1,
                   matrix_time_f2   => matrix_time_f2
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
               all_time         <= coarse_time & fine_time;
               --
               time_update_f0_A <= '0' WHEN sample_f0_A_wen = "11111" ELSE
                                   '1' WHEN sample_f0_A_empty = "11111" ELSE
                                   '0';
               s_m_t_m_f0_A : spectral_matrix_time_managment
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   time_in  => all_time,
                   update_1 => time_update_f0_A,
                   time_out => time_reg_f0_A);
               --
               time_update_f0_B <= '0' WHEN sample_f0_B_wen = "11111" ELSE
                                   '1' WHEN sample_f0_B_empty = "11111" ELSE
                                   '0';
               s_m_t_m_f0_B : spectral_matrix_time_managment
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   time_in  => all_time,
                   update_1 => time_update_f0_B,
                   time_out => time_reg_f0_B);
               --
               time_update_f1 <= '0' WHEN sample_f1_wen = "11111" ELSE
                                 '1' WHEN sample_f1_empty = "11111" ELSE
                                 '0';
               s_m_t_m_f1 : spectral_matrix_time_managment
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   time_in  => all_time,
                   update_1 => time_update_f1,
                   time_out => time_reg_f1);
               --
               time_update_f2 <= '0' WHEN sample_f2_wen = "11111" ELSE
                                 '1' WHEN sample_f2_empty = "11111" ELSE
                                 '0';
               s_m_t_m_f2 : spectral_matrix_time_managment
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   time_in  => all_time,
                   update_1 => time_update_f2,
                   time_out => time_reg_f2);
               -----------------------------------------------------------------------------
               dma_time <= (OTHERS => '0');         -- TODO
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_dma/lpp_dma_pkg.vhd +4 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE std.textio.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
-            LIBRARY lpp;
+            --LIBRARY lpp;
-            USE lpp.lpp_amba.ALL;
+            --USE lpp.lpp_amba.ALL;
-            USE lpp.apb_devices_list.ALL;
+            --USE lpp.apb_devices_list.ALL;
-            USE lpp.lpp_memory.ALL;
+            --USE lpp.lpp_memory.ALL;
             PACKAGE lpp_dma_pkg IS
               COMPONENT lpp_dma
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   apbi           : IN  apb_slv_in_type;
                   apbo           : OUT apb_slv_out_type;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   -- fifo interface
                   fifo_data      : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty     : IN  STD_LOGIC;
                   fifo_ren       : OUT STD_LOGIC;
                   -- header
                   header         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val     : IN  STD_LOGIC;
                   header_ack     : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_test_dma
                 GENERIC (
                   tech   : INTEGER;
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER);
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   apbi       : IN  apb_slv_in_type;
                   apbo       : OUT apb_slv_out_type;
                   -- fifo interface
                   fifo_data  : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : OUT STD_LOGIC;
                   fifo_ren   : IN  STD_LOGIC;
                   -- header
                   header     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val : OUT STD_LOGIC;
                   header_ack : IN  STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT lpp_dma_apbreg
                 GENERIC (
                   pindex : INTEGER;
                   paddr  : INTEGER;
                   pmask  : INTEGER;
                   pirq   : INTEGER);
                 PORT (
                   HCLK                          : IN  STD_ULOGIC;
                   HRESETn                       : IN  STD_ULOGIC;
                   apbi                          : IN  apb_slv_in_type;
                   apbo                          : OUT apb_slv_out_type;
                   -- IN
                   ready_matrix_f0_0             : IN  STD_LOGIC;
                   ready_matrix_f0_1             : IN  STD_LOGIC;
                   ready_matrix_f1               : IN  STD_LOGIC;
                   ready_matrix_f2               : IN  STD_LOGIC;
                   error_anticipating_empty_fifo : IN  STD_LOGIC;
                   error_bad_component_error     : IN  STD_LOGIC;
                   debug_reg                     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                   -- OUT
                   status_ready_matrix_f0_0             : OUT STD_LOGIC;
                   status_ready_matrix_f0_1             : OUT STD_LOGIC;
                   status_ready_matrix_f1               : OUT STD_LOGIC;
                   status_ready_matrix_f2               : OUT STD_LOGIC;
                   status_error_anticipating_empty_fifo : OUT STD_LOGIC;
                   status_error_bad_component_error     : OUT STD_LOGIC;
                   config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                   config_active_interruption_onError     : OUT STD_LOGIC;
                   addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_dma_send_1word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_send_16word
                 PORT (
                   HCLK    : IN  STD_ULOGIC;
                   HRESETn : IN  STD_ULOGIC;
                   DMAIn   : OUT DMA_In_Type;
                   DMAOut  : IN  DMA_OUt_Type;
                   send    : IN  STD_LOGIC;
                   address : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data    : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   ren     : OUT STD_LOGIC;
                   send_ok : OUT STD_LOGIC;
                   send_ko : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT fifo_latency_correction
                 PORT (
                   HCLK       : IN  STD_ULOGIC;
                   HRESETn    : IN  STD_ULOGIC;
                   fifo_data  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty : IN  STD_LOGIC;
                   fifo_ren   : OUT STD_LOGIC;
                   dma_data   : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_empty  : OUT STD_LOGIC;
                   dma_ren    : IN  STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_dma_ip
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK                                   : IN  STD_ULOGIC;
                   HRESETn                                : IN  STD_ULOGIC;
                   AHB_Master_In                          : IN  AHB_Mst_In_Type;
                   AHB_Master_Out                         : OUT AHB_Mst_Out_Type;
                   fifo_data                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty                             : IN  STD_LOGIC;
                   fifo_ren                               : OUT STD_LOGIC;
                   header                                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   header_val                             : IN  STD_LOGIC;
                   header_ack                             : OUT STD_LOGIC;
                   ready_matrix_f0_0                      : OUT STD_LOGIC;
                   ready_matrix_f0_1                      : OUT STD_LOGIC;
                   ready_matrix_f1                        : OUT STD_LOGIC;
                   ready_matrix_f2                        : OUT STD_LOGIC;
                   error_anticipating_empty_fifo          : OUT STD_LOGIC;
                   error_bad_component_error              : OUT STD_LOGIC;
                   debug_reg                              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   status_ready_matrix_f0_0               : IN  STD_LOGIC;
                   status_ready_matrix_f0_1               : IN  STD_LOGIC;
                   status_ready_matrix_f1                 : IN  STD_LOGIC;
                   status_ready_matrix_f2                 : IN  STD_LOGIC;
                   status_error_anticipating_empty_fifo   : IN  STD_LOGIC;
                   status_error_bad_component_error       : IN  STD_LOGIC;
                   config_active_interruption_onNewMatrix : IN  STD_LOGIC;
                   config_active_interruption_onError     : IN  STD_LOGIC;
                   addr_matrix_f0_0                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f0_1                       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2                         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_dma_singleOrBurst
                 GENERIC (
                   tech   : INTEGER;
                   hindex : INTEGER);
                 PORT (
                   HCLK           : IN  STD_ULOGIC;
                   HRESETn        : IN  STD_ULOGIC;
                   run            : IN  STD_LOGIC;
                   AHB_Master_In  : IN  AHB_Mst_In_Type;
                   AHB_Master_Out : OUT AHB_Mst_Out_Type;
                   send           : IN  STD_LOGIC;
                   valid_burst    : IN  STD_LOGIC;
                   done           : OUT STD_LOGIC;
                   ren            : OUT STD_LOGIC;
                   address        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data           : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   debug_dmaout_okay : OUT STD_LOGIC);
               END COMPONENT;
             END;

General Comments 0

Write
Preview

You need to be logged in to leave comments. Login now

No TODOs yet

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages