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r359:ddd83014c899 JC
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@@ -0,0 +1,129
1 LIBRARY IEEE;
2 USE IEEE.std_logic_1164.ALL;
3 USE IEEE.numeric_std.ALL;
4
5 ENTITY MS_control IS
6 PORT (
7 clk : IN STD_LOGIC;
8 rstn : IN STD_LOGIC;
9
10 -- IN
11 fifo_in_lock : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
12 fifo_in_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
13 fifo_in_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
14 fifo_in_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
15 fifo_in_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
16 fifo_in_reuse : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
17 -- OUT
18 fifo_out_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
19 fifo_out_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
20 fifo_out_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
21 -- OUT
22 correlation_start : OUT STD_LOGIC;
23 correlation_auto : OUT STD_LOGIC; -- 1 => auto correlation / 0 => inter correlation
24 correlation_done : IN STD_LOGIC
25 );
26 END MS_control;
27
28 ARCHITECTURE beh OF MS_control IS
29
30 TYPE fsm_control_MS IS (WAIT_DATA, CORRELATION_ONGOING);
31 SIGNAL state : fsm_control_MS;
32
33 SUBTYPE fifo_pointer IS RANGE 0 TO 4;
34 SIGNAL fifo_1 : fifo_pointer;
35 SIGNAL fifo_2 : fifo_pointer;
36
37 SIGNAL fifo_in_lock_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
38 SIGNAL fifo_in_reuse_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
39
40 BEGIN -- beh
41
42 fifo_in_lock <= fifo_in_lock_s;
43 fifo_in_reuse <= fifo_in_reuse_s;
44
45 PROCESS (clk, rstn)
46 BEGIN
47 IF rstn = '0' THEN
48 state <= WAIT_DATA;
49 fifo_1 <= 0;
50 fifo_2 <= 0;
51 fifo_in_lock_s <= (OTHERS => '0');
52 fifo_in_reuse_s <= (OTHERS => '0');
53 correlation_start <= '0';
54 correlation_auto <= '0';
55 ELSIF clk'event AND clk = '1' THEN
56 CASE state IS
57 WHEN WAIT_DATA =>
58 fifo_in_reuse_s <= (OTHERS => '0');
59 IF fifo_in_full[fifo_1] = '1' AND fifo_in_full[fifo_2] = '1' THEN
60 fifo_in_lock_s(fifo_1) <= '1';
61 fifo_in_lock_s(fifo_2) <= '1';
62 correlation_start <= '1';
63 IF fifo_1 = fifo_2 THEN
64 correlation_auto <= '1';
65 END IF;
66 state <= CORRELATION_ONGOING;
67 END IF;
68
69 WHEN CORRELATION_ONGOING =>
70 correlation_start <= '0';
71 correlation_auto <= '0';
72 IF correlation_done = '1' THEN
73 state <= WAIT_DATA;
74 IF fifo_2 = 4 THEN
75 fifo_in_lock_s(fifo_1) <= '0';
76 IF fifo_1 = 4 THEN
77 fifo_1 <= 0;
78 fifo_2 <= 0;
79 ELSE
80 fifo_in_reuse_s(fifo_2) <= '1';
81 fifo_1 <= fifo_1 + 1;
82 fifo_2 <= fifo_1 + 1;
83 END IF;
84 ELSE
85 fifo_in_reuse_s(fifo_2) <= '1';
86 fifo_in_reuse_s(fifo_1) <= '1';
87 fifo_2 <= fifo_2 + 1;
88 END IF;
89 END IF;
90
91 WHEN OTHERS => NULL;
92 END CASE;
93 END IF;
94 END PROCESS;
95
96
97 fifo_out_data(31 DOWNTO 0) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_1 = 0 ELSE
98 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_1 = 1 ELSE
99 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_1 = 2 ELSE
100 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_1 = 3 ELSE
101 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_1 = 4
102
103
104 fifo_out_data(63 DOWNTO 32) <= fifo_in_data(31*1-1 DOWNTO 32*0) WHEN fifo_2 = 0 ELSE
105 fifo_in_data(32*2-1 DOWNTO 32*1) WHEN fifo_2 = 1 ELSE
106 fifo_in_data(32*3-1 DOWNTO 32*2) WHEN fifo_2 = 2 ELSE
107 fifo_in_data(32*4-1 DOWNTO 32*3) WHEN fifo_2 = 3 ELSE
108 fifo_in_data(32*5-1 DOWNTO 32*4);-- WHEN fifo_2 = 4
109
110 fifo_out_empty(0) <= fifo_in_empty(0) WHEN fifo_1 = 0 ELSE
111 fifo_in_empty(1) WHEN fifo_1 = 1 ELSE
112 fifo_in_empty(2) WHEN fifo_1 = 2 ELSE
113 fifo_in_empty(3) WHEN fifo_1 = 3 ELSE
114 fifo_in_empty(4);
115
116 fifo_out_empty(1) <= fifo_in_empty(0) WHEN fifo_2 = 0 ELSE
117 fifo_in_empty(1) WHEN fifo_2 = 1 ELSE
118 fifo_in_empty(2) WHEN fifo_2 = 2 ELSE
119 fifo_in_empty(3) WHEN fifo_2 = 3 ELSE
120 fifo_in_empty(4);
121
122
123 all_fifo: FOR I IN 0 TO 4 GENERATE
124 fifo_in_ren(I) <= fifo_out_ren(I) WHEN fifo_1 = I ELSE
125 fifo_out_ren(I) WHEN fifo_2 = I ELSE
126 '1';
127 END GENERATE all_fifo;
128
129 END beh;
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@@ -388,6 +388,7 vcom_lpp:
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
388 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_matrix/SpectralMatrix.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
389 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/lpp_Header.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
390 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_Header/HeaderBuilder.vhd
391 $(CMD_VCOM) lpp lpp_memory.vhd
391 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/./dsp/lpp_fft/CoreFFT_simu.vhd
392 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
393 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
394 $(CMD_VCOM) lpp $(VHDLIB)/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
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@@ -697,7 +697,11 BEGIN
697 END PROCESS;
697 END PROCESS;
698 END GENERATE all_lock;
698 END GENERATE all_lock;
699
699
700 -----------------------------------------------------------------------------
701
700
702
703
704
701
705
702 -----------------------------------------------------------------------------
706 -----------------------------------------------------------------------------
703 SM0 : MatriceSpectrale
707 SM0 : MatriceSpectrale
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@@ -31,10 +31,10 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 LIBRARY lpp;
34 --LIBRARY lpp;
35 USE lpp.lpp_amba.ALL;
35 --USE lpp.lpp_amba.ALL;
36 USE lpp.apb_devices_list.ALL;
36 --USE lpp.apb_devices_list.ALL;
37 USE lpp.lpp_memory.ALL;
37 --USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
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