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r365:d9d8ceb0e9b3 JC
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@@ -0,0 +1,76
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
16
17 ENTITY lpp_lfr_ms_FFT IS
18 PORT (
19 clk : IN STD_LOGIC;
20 rstn : IN STD_LOGIC;
21 -- IN
22 sample_valid : IN STD_LOGIC;
23 fft_read : IN STD_LOGIC;
24 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
25 sample_load : OUT STD_LOGIC;
26
27 --OUT
28 fft_pong : OUT STD_LOGIC;
29 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
30 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
31 fft_data_valid : OUT STD_LOGIC;
32 fft_ready : OUT STD_LOGIC
33
34 );
35 END;
36
37 ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS
38
39 BEGIN
40
41 -----------------------------------------------------------------------------
42 -- FFT
43 -----------------------------------------------------------------------------
44 CoreFFT_1 : CoreFFT
45 GENERIC MAP (
46 LOGPTS => gLOGPTS,
47 LOGLOGPTS => gLOGLOGPTS,
48 WSIZE => gWSIZE,
49 TWIDTH => gTWIDTH,
50 DWIDTH => gDWIDTH,
51 TDWIDTH => gTDWIDTH,
52 RND_MODE => gRND_MODE,
53 SCALE_MODE => gSCALE_MODE,
54 PTS => gPTS,
55 HALFPTS => gHALFPTS,
56 inBuf_RWDLY => gInBuf_RWDLY)
57 PORT MAP (
58 clk => clk,
59 ifiStart => '0', -- '1'
60 ifiNreset => rstn,
61
62 ifiD_valid => sample_valid, -- IN
63 ifiRead_y => fft_read,
64 ifiD_im => (OTHERS => '0'), -- IN
65 ifiD_re => sample_data, -- IN
66 ifoLoad => sample_load, -- IN
67
68 ifoPong => fft_pong,
69 ifoY_im => fft_data_im,
70 ifoY_re => fft_data_re,
71 ifoY_valid => fft_data_valid,
72 ifoY_rdy => fft_ready);
73
74 -----------------------------------------------------------------------------
75
76 END Behavioral;
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@@ -426,7 +426,7 BEGIN -- beh
426 pirq_ms => 6,
426 pirq_ms => 6,
427 pirq_wfp => 14,
427 pirq_wfp => 14,
428 hindex => 2,
428 hindex => 2,
429 top_lfr_version => X"00010B") -- aa.bb.cc version
429 top_lfr_version => X"00010C") -- aa.bb.cc version
430 PORT MAP (
430 PORT MAP (
431 clk => clk_25,
431 clk => clk_25,
432 rstn => reset,
432 rstn => reset,
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@@ -137,19 +137,19 ARCHITECTURE beh OF lpp_lfr IS
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 SIGNAL status_error_bad_component_error : STD_LOGIC;
148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
155
@@ -292,11 +292,14 ARCHITECTURE beh OF lpp_lfr IS
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
292 SIGNAL ms_softandhard_rstn : STD_LOGIC;
293
293
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
294 SIGNAL matrix_time_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
295 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
296 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
297 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
298
298
299
299
300 SIGNAL error_buffer_full : STD_LOGIC;
301 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
302
300 BEGIN
303 BEGIN
301
304
302 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
305 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -351,30 +354,33 BEGIN
351 run_ms => run_ms,
354 run_ms => run_ms,
352
355
353 ready_matrix_f0_0 => ready_matrix_f0_0,
356 ready_matrix_f0_0 => ready_matrix_f0_0,
354 ready_matrix_f0_1 => ready_matrix_f0_1,
357 -- ready_matrix_f0_1 => ready_matrix_f0_1,
355 ready_matrix_f1 => ready_matrix_f1,
358 ready_matrix_f1 => ready_matrix_f1,
356 ready_matrix_f2 => ready_matrix_f2,
359 ready_matrix_f2 => ready_matrix_f2,
357 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
360 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
358 error_bad_component_error => error_bad_component_error,
361 error_bad_component_error => error_bad_component_error,
362 error_buffer_full => error_buffer_full, -- TODO
363 error_input_fifo_write => error_input_fifo_write, -- TODO
359 debug_reg => debug_reg,
364 debug_reg => debug_reg,
360 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
365 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
361 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
366 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
362 status_ready_matrix_f1 => status_ready_matrix_f1,
367 status_ready_matrix_f1 => status_ready_matrix_f1,
363 status_ready_matrix_f2 => status_ready_matrix_f2,
368 status_ready_matrix_f2 => status_ready_matrix_f2,
364 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
369 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
365 status_error_bad_component_error => status_error_bad_component_error,
370 -- status_error_bad_component_error => status_error_bad_component_error,
366 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
371 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
367 config_active_interruption_onError => config_active_interruption_onError,
372 config_active_interruption_onError => config_active_interruption_onError,
368
373
369 matrix_time_f0_0 => matrix_time_f0_0,
374 matrix_time_f0_0 => matrix_time_f0_0,
370 matrix_time_f0_1 => matrix_time_f0_1,
375 -- matrix_time_f0_1 => matrix_time_f0_1,
371 matrix_time_f1 => matrix_time_f1,
376 matrix_time_f1 => matrix_time_f1,
372 matrix_time_f2 => matrix_time_f2,
377 matrix_time_f2 => matrix_time_f2,
373
378
374 addr_matrix_f0_0 => addr_matrix_f0_0,
379 addr_matrix_f0_0 => addr_matrix_f0_0,
375 addr_matrix_f0_1 => addr_matrix_f0_1,
380 -- addr_matrix_f0_1 => addr_matrix_f0_1,
376 addr_matrix_f1 => addr_matrix_f1,
381 addr_matrix_f1 => addr_matrix_f1,
377 addr_matrix_f2 => addr_matrix_f2,
382 addr_matrix_f2 => addr_matrix_f2,
383 -------------------------------------------------------------------------
378 status_full => status_full,
384 status_full => status_full,
379 status_full_ack => status_full_ack,
385 status_full_ack => status_full_ack,
380 status_full_err => status_full_err,
386 status_full_err => status_full_err,
@@ -741,9 +747,11 BEGIN
741 ready_matrix_f2 => ready_matrix_f2,
747 ready_matrix_f2 => ready_matrix_f2,
742 --error_anticipating_empty_fifo => error_anticipating_empty_fifo,
748 --error_anticipating_empty_fifo => error_anticipating_empty_fifo,
743 error_bad_component_error => error_bad_component_error,
749 error_bad_component_error => error_bad_component_error,
744 error_buffer_full => OPEN, -- TODO
750 error_buffer_full => error_buffer_full, -- TODO
745 error_input_fifo_write => OPEN, -- TODO
751 error_input_fifo_write => error_input_fifo_write, -- TODO
752
746 debug_reg => observation_reg,
753 debug_reg => observation_reg,
754
747 status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename
755 status_ready_matrix_f0 => status_ready_matrix_f0_0,-- TODO rename
748 status_ready_matrix_f1 => status_ready_matrix_f1,
756 status_ready_matrix_f1 => status_ready_matrix_f1,
749 status_ready_matrix_f2 => status_ready_matrix_f2,
757 status_ready_matrix_f2 => status_ready_matrix_f2,
@@ -759,4 +767,4 BEGIN
759 matrix_time_f1 => matrix_time_f1,
767 matrix_time_f1 => matrix_time_f1,
760 matrix_time_f2 => matrix_time_f2);
768 matrix_time_f2 => matrix_time_f2);
761
769
762 END beh;
770 END beh; No newline at end of file
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@@ -62,31 +62,30 ENTITY lpp_lfr_apbreg IS
62 run_ms : OUT STD_LOGIC;
62 run_ms : OUT STD_LOGIC;
63 -- IN
63 -- IN
64 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_0 : IN STD_LOGIC;
65 ready_matrix_f0_1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
68 error_anticipating_empty_fifo : IN STD_LOGIC;
67
69 error_bad_component_error : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
69 error_buffer_full : in STD_LOGIC; -- TODO
70 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71
70 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71
73
72 -- OUT
74 -- OUT
73 status_ready_matrix_f0_0 : OUT STD_LOGIC;
75 status_ready_matrix_f0_0 : OUT STD_LOGIC;
74 status_ready_matrix_f0_1 : OUT STD_LOGIC;
75 status_ready_matrix_f1 : OUT STD_LOGIC;
76 status_ready_matrix_f1 : OUT STD_LOGIC;
76 status_ready_matrix_f2 : OUT STD_LOGIC;
77 status_ready_matrix_f2 : OUT STD_LOGIC;
77 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
78 status_error_bad_component_error : OUT STD_LOGIC;
79
78
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
82
81
83 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87
86
88 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
91 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
92
91
@@ -158,18 +157,20 ARCHITECTURE beh OF lpp_lfr_apbreg IS
158 config_active_interruption_onError : STD_LOGIC;
157 config_active_interruption_onError : STD_LOGIC;
159 config_ms_run : STD_LOGIC;
158 config_ms_run : STD_LOGIC;
160 status_ready_matrix_f0_0 : STD_LOGIC;
159 status_ready_matrix_f0_0 : STD_LOGIC;
161 status_ready_matrix_f0_1 : STD_LOGIC;
160 -- status_ready_matrix_f0_1 : STD_LOGIC;
162 status_ready_matrix_f1 : STD_LOGIC;
161 status_ready_matrix_f1 : STD_LOGIC;
163 status_ready_matrix_f2 : STD_LOGIC;
162 status_ready_matrix_f2 : STD_LOGIC;
164 status_error_anticipating_empty_fifo : STD_LOGIC;
163 -- status_error_anticipating_empty_fifo : STD_LOGIC;
165 status_error_bad_component_error : STD_LOGIC;
164 status_error_bad_component_error : STD_LOGIC;
165 status_error_buffer_full : STD_LOGIC; -- TODO
166 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
166 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 -- addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170
171
171 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 -- coarse_time_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 coarse_time_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 coarse_time_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175
176
@@ -228,16 +229,16 ARCHITECTURE beh OF lpp_lfr_apbreg IS
228 BEGIN -- beh
229 BEGIN -- beh
229
230
230 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
231 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
231 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
232 -- status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
232 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
233 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
233 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
234 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
234 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
235 -- status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
235 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
236 -- status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
236
237
237 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
238 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
238 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
239 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
239 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
240 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
240 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
241 -- addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
241 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
242 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
242 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
243 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
243
244
@@ -283,18 +284,21 BEGIN -- beh
283 reg_sp.config_active_interruption_onError <= '0';
284 reg_sp.config_active_interruption_onError <= '0';
284 reg_sp.config_ms_run <= '1';
285 reg_sp.config_ms_run <= '1';
285 reg_sp.status_ready_matrix_f0_0 <= '0';
286 reg_sp.status_ready_matrix_f0_0 <= '0';
286 reg_sp.status_ready_matrix_f0_1 <= '0';
287 -- reg_sp.status_ready_matrix_f0_1 <= '0';
287 reg_sp.status_ready_matrix_f1 <= '0';
288 reg_sp.status_ready_matrix_f1 <= '0';
288 reg_sp.status_ready_matrix_f2 <= '0';
289 reg_sp.status_ready_matrix_f2 <= '0';
289 reg_sp.status_error_anticipating_empty_fifo <= '0';
290 -- reg_sp.status_error_anticipating_empty_fifo <= '0';
290 reg_sp.status_error_bad_component_error <= '0';
291 reg_sp.status_error_bad_component_error <= '0';
292 reg_sp.status_error_buffer_full <= '0';
293 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
294
291 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
295 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
292 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
296 -- reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
293 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
297 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
294 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
298 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
295
299
296 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
300 reg_sp.coarse_time_f0_0 <= (OTHERS => '0');
297 reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
301 -- reg_sp.coarse_time_f0_1 <= (OTHERS => '0');
298 reg_sp.coarse_time_f1 <= (OTHERS => '0');
302 reg_sp.coarse_time_f1 <= (OTHERS => '0');
299 reg_sp.coarse_time_f2 <= (OTHERS => '0');
303 reg_sp.coarse_time_f2 <= (OTHERS => '0');
300 --reg_sp.fine_time_f0_0 <= (OTHERS => '0');
304 --reg_sp.fine_time_f0_0 <= (OTHERS => '0');
@@ -340,7 +344,7 BEGIN -- beh
340 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
344 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
341
345
342 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
346 reg_sp.coarse_time_f0_0 <= matrix_time_f0_0(31 DOWNTO 0);
343 reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
347 -- reg_sp.coarse_time_f0_1 <= matrix_time_f0_1(31 DOWNTO 0);
344 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
348 reg_sp.coarse_time_f1 <= matrix_time_f1 (31 DOWNTO 0);
345 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
349 reg_sp.coarse_time_f2 <= matrix_time_f2 (31 DOWNTO 0);
346
350
@@ -352,12 +356,20 BEGIN -- beh
352 status_full_ack <= (OTHERS => '0');
356 status_full_ack <= (OTHERS => '0');
353
357
354 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
358 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
355 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
359 -- reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
356 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
360 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
357 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
361 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
358
362
359 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
363 -- reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
360 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
364 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
365
366 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
367 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
368 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
369 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
370
371
372
361 all_status: FOR I IN 3 DOWNTO 0 LOOP
373 all_status: FOR I IN 3 DOWNTO 0 LOOP
362 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
374 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
363 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
375 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
@@ -378,22 +390,26 BEGIN -- beh
378 prdata(1) <= reg_sp.config_active_interruption_onError;
390 prdata(1) <= reg_sp.config_active_interruption_onError;
379 prdata(2) <= reg_sp.config_ms_run;
391 prdata(2) <= reg_sp.config_ms_run;
380 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
392 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
381 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
393 -- prdata(1) <= reg_sp.status_ready_matrix_f0_1;
382 prdata(2) <= reg_sp.status_ready_matrix_f1;
394 prdata(2) <= reg_sp.status_ready_matrix_f1;
383 prdata(3) <= reg_sp.status_ready_matrix_f2;
395 prdata(3) <= reg_sp.status_ready_matrix_f2;
384 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
396 -- prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
385 prdata(5) <= reg_sp.status_error_bad_component_error;
397 prdata(5) <= reg_sp.status_error_bad_component_error;
398 prdata(6) <= reg_sp.status_error_buffer_full;
399 prdata(7) <= reg_sp.status_error_input_fifo_write(0);
400 prdata(8) <= reg_sp.status_error_input_fifo_write(1);
401 prdata(9) <= reg_sp.status_error_input_fifo_write(2);
386 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
402 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
387 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
403 -- WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
388 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
404 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
389 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
405 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
390
406
391 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
407 WHEN "000110" => prdata <= reg_sp.coarse_time_f0_0;
392 WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
408 -- WHEN "000111" => prdata <= reg_sp.coarse_time_f0_1;
393 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
409 WHEN "001000" => prdata <= reg_sp.coarse_time_f1;
394 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
410 WHEN "001001" => prdata <= reg_sp.coarse_time_f2;
395 WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
411 WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;
396 WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
412 -- WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;
397 WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
413 WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1 (15 DOWNTO 0);--reg_sp.fine_time_f1;
398 WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
414 WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2 (15 DOWNTO 0);--reg_sp.fine_time_f2;
399
415
@@ -450,13 +466,17 BEGIN -- beh
450 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
466 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
451 reg_sp.config_ms_run <= apbi.pwdata(2);
467 reg_sp.config_ms_run <= apbi.pwdata(2);
452 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
468 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
453 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
469 -- reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
454 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
470 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
455 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
471 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
456 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
472 -- reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
457 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
473 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
474 reg_sp.status_error_buffer_full <= apbi.pwdata(6);
475 reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(7);
476 reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(8);
477 reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(9);
458 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
478 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
459 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
479 -- WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
460 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
480 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
461 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
481 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
462 --
482 --
@@ -500,13 +520,18 BEGIN -- beh
500 END IF;
520 END IF;
501
521
502 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
522 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
503 ready_matrix_f0_1 OR
523 -- ready_matrix_f0_1 OR
504 ready_matrix_f1 OR
524 ready_matrix_f1 OR
505 ready_matrix_f2)
525 ready_matrix_f2)
506 )
526 )
507 OR
527 OR
508 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
528 (reg_sp.config_active_interruption_onError AND (
509 error_bad_component_error)
529 --error_anticipating_empty_fifo OR
530 error_bad_component_error
531 OR error_buffer_full
532 OR error_input_fifo_write(0)
533 OR error_input_fifo_write(1)
534 OR error_input_fifo_write(2))
510 ));
535 ));
511
536
512 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
537 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
@@ -541,4 +566,4 BEGIN -- beh
541
566
542 run_ms <= reg_sp.config_ms_run;
567 run_ms <= reg_sp.config_ms_run;
543
568
544 END beh; No newline at end of file
569 END beh;
Show file before | Show file after | Hide comments
@@ -50,10 +50,8 ENTITY lpp_lfr_ms IS
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 -- ready_matrix_f0 : OUT STD_LOGIC;
54 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
55 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
56 --error_anticipating_empty_fifo : OUT STD_LOGIC;
57 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
58 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
59 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
@@ -62,22 +60,16 ENTITY lpp_lfr_ms IS
62
60
63 -- Reg In
61 -- Reg In
64 status_ready_matrix_f0 : IN STD_LOGIC;
62 status_ready_matrix_f0 : IN STD_LOGIC;
65 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
63 status_ready_matrix_f1 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
64 status_ready_matrix_f2 : IN STD_LOGIC;
68 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
69 -- status_error_bad_component_error : IN STD_LOGIC;
70 -- status_error_buffer_full : IN STD_LOGIC;
71
65
72 config_active_interruption_onNewMatrix : IN STD_LOGIC;
66 config_active_interruption_onNewMatrix : IN STD_LOGIC;
73 config_active_interruption_onError : IN STD_LOGIC;
67 config_active_interruption_onError : IN STD_LOGIC;
74 -- addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78
71
79 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
72 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
80 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
81 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
73 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
82 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
74 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
83
75
@@ -187,18 +179,12 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
187 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
179 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
188 SIGNAL SM_correlation_begin : STD_LOGIC;
180 SIGNAL SM_correlation_begin : STD_LOGIC;
189
181
190 -- SIGNAL temp_ongoing : STD_LOGIC;
191 -- SIGNAL temp_auto : STD_LOGIC;
192
193 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
182 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
194 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
184 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
196
185
197 SIGNAL current_matrix_write : STD_LOGIC;
186 SIGNAL current_matrix_write : STD_LOGIC;
198 SIGNAL current_matrix_wait_empty : STD_LOGIC;
187 SIGNAL current_matrix_wait_empty : STD_LOGIC;
199
200 --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0);
201
202 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
203 SIGNAL fifo_0_ready : STD_LOGIC;
189 SIGNAL fifo_0_ready : STD_LOGIC;
204 SIGNAL fifo_1_ready : STD_LOGIC;
190 SIGNAL fifo_1_ready : STD_LOGIC;
@@ -208,27 +194,13 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
208 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
194 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
209 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
196 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
211
212 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
213 -- SIGNAL HEAD_SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 --SIGNAL HEAD_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
215 --SIGNAL HEAD_SM_Wen : STD_LOGIC;
216 --SIGNAL HEAD_Valid : STD_LOGIC;
217 --SIGNAL HEAD_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 --SIGNAL HEAD_Empty : STD_LOGIC;
219 --SIGNAL HEAD_Read : STD_LOGIC;
220 -----------------------------------------------------------------------------
221 -- SIGNAL MEM_OUT_SM_ReUse : STD_LOGIC_VECTOR(1 DOWNTO 0);
222 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
223 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
199 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
224 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
200 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
225 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
226 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
227 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
228 -----------------------------------------------------------------------------
229 --SIGNAL DMA_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
230 --SIGNAL DMA_Header_Val : STD_LOGIC;
231 --SIGNAL DMA_Header_Ack : STD_LOGIC;
232
204
233 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
234 -- TIME REG & INFOs
206 -- TIME REG & INFOs
@@ -251,12 +223,8 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
251
223
252 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
224 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
253 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
225 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
254 -- SIGNAL status_component_fifo_0_new : STD_LOGIC;
255 -- SIGNAL status_component_fifo_1_new : STD_LOGIC;
256 SIGNAL status_component_fifo_0_end : STD_LOGIC;
226 SIGNAL status_component_fifo_0_end : STD_LOGIC;
257 SIGNAL status_component_fifo_1_end : STD_LOGIC;
227 SIGNAL status_component_fifo_1_end : STD_LOGIC;
258
259 SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
260 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
261
229
262 BEGIN
230 BEGIN
@@ -598,16 +566,12 BEGIN
598 fft_ready => fft_ready);
566 fft_ready => fft_ready);
599
567
600 -----------------------------------------------------------------------------
568 -----------------------------------------------------------------------------
601 -- in fft_data_im & fft_data_re
602 -- in fft_data_valid
603 -- in fft_ready
604 -- out fft_read
605 PROCESS (clk, rstn)
569 PROCESS (clk, rstn)
606 BEGIN
570 BEGIN
607 IF rstn = '0' THEN
571 IF rstn = '0' THEN
608 state_fsm_load_MS_memory <= IDLE;
572 state_fsm_load_MS_memory <= IDLE;
609 current_fifo_load <= "00001";
573 current_fifo_load <= "00001";
610 ELSIF clk'event AND clk = '1' THEN
574 ELSIF clk'EVENT AND clk = '1' THEN
611 CASE state_fsm_load_MS_memory IS
575 CASE state_fsm_load_MS_memory IS
612 WHEN IDLE =>
576 WHEN IDLE =>
613 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
577 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
@@ -659,7 +623,7 BEGIN
659 BEGIN
623 BEGIN
660 IF rstn = '0' THEN
624 IF rstn = '0' THEN
661 MEM_IN_SM_wen <= (OTHERS => '1');
625 MEM_IN_SM_wen <= (OTHERS => '1');
662 ELSIF clk'event AND clk = '1' THEN
626 ELSIF clk'EVENT AND clk = '1' THEN
663 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
627 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
664 END IF;
628 END IF;
665 END PROCESS;
629 END PROCESS;
@@ -670,37 +634,6 BEGIN
670 (fft_data_im & fft_data_re) &
634 (fft_data_im & fft_data_re) &
671 (fft_data_im & fft_data_re);
635 (fft_data_im & fft_data_re);
672
636
673
674 -- out SM_MEM_IN_wData
675 -- out SM_MEM_IN_wen
676 -- out SM_MEM_IN_Full
677
678 -- out SM_MEM_IN_locked
679 -----------------------------------------------------------------------------
680 -----------------------------------------------------------------------------
681 -----------------------------------------------------------------------------
682 -----------------------------------------------------------------------------
683 --Linker_FFT_1 : Linker_FFT
684 -- GENERIC MAP (
685 -- Data_sz => 16,
686 -- NbData => 256)
687 -- PORT MAP (
688 -- clk => clk,
689 -- rstn => rstn,
690
691 -- Ready => fft_ready,
692 -- Valid => fft_data_valid,
693
694 -- Full => MEM_IN_SM_Full,
695
696 -- Data_re => fft_data_re,
697 -- Data_im => fft_data_im,
698 -- Read => fft_read,
699
700 -- Write => MEM_IN_SM_wen,
701 -- ReUse => fft_linker_ReUse,
702 -- DATA => MEM_IN_SM_wData);
703
704 -----------------------------------------------------------------------------
637 -----------------------------------------------------------------------------
705 Mem_In_SpectralMatrix : lppFIFOxN
638 Mem_In_SpectralMatrix : lppFIFOxN
706 GENERIC MAP (
639 GENERIC MAP (
@@ -724,18 +657,6 BEGIN
724 empty => MEM_IN_SM_Empty,
657 empty => MEM_IN_SM_Empty,
725 almost_full => OPEN);
658 almost_full => OPEN);
726
659
727
728 --all_lock: FOR I IN 4 DOWNTO 0 GENERATE
729 -- PROCESS (clk, rstn)
730 -- BEGIN
731 -- IF rstn = '0' THEN
732 -- MEM_IN_SM_locked(I) <= '0';
733 -- ELSIF clk'event AND clk = '1' THEN
734 -- MEM_IN_SM_locked(I) <= MEM_IN_SM_Full(I) OR MEM_IN_SM_locked(I); -- TODO
735 -- END IF;
736 -- END PROCESS;
737 --END GENERATE all_lock;
738
739 -----------------------------------------------------------------------------
660 -----------------------------------------------------------------------------
740 MS_control_1: MS_control
661 MS_control_1 : MS_control
741 PORT MAP (
662 PORT MAP (
@@ -788,32 +709,22 BEGIN
788 current_matrix_wait_empty <= '1';
709 current_matrix_wait_empty <= '1';
789 status_component_fifo_0 <= (OTHERS => '0');
710 status_component_fifo_0 <= (OTHERS => '0');
790 status_component_fifo_1 <= (OTHERS => '0');
711 status_component_fifo_1 <= (OTHERS => '0');
791 -- status_component_fifo_0_new <= '0';
792 -- status_component_fifo_1_new <= '0';
793 status_component_fifo_0_end <= '0';
712 status_component_fifo_0_end <= '0';
794 status_component_fifo_1_end <= '0';
713 status_component_fifo_1_end <= '0';
795 SM_correlation_done_reg1 <= '0';
714 SM_correlation_done_reg1 <= '0';
796 SM_correlation_done_reg2 <= '0';
715 SM_correlation_done_reg2 <= '0';
797 SM_correlation_done_reg3 <= '0';
716 SM_correlation_done_reg3 <= '0';
798
717
799 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
718 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
800 SM_correlation_done_reg1 <= SM_correlation_done;
719 SM_correlation_done_reg1 <= SM_correlation_done;
801 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
720 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
802 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
721 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
803
804 -- status_component_fifo_0_new <= '0';
805 -- status_component_fifo_1_new <= '0';
806 status_component_fifo_0_end <= '0';
722 status_component_fifo_0_end <= '0';
807 status_component_fifo_1_end <= '0';
723 status_component_fifo_1_end <= '0';
808
809
810
811 IF SM_correlation_begin = '1' THEN
724 IF SM_correlation_begin = '1' THEN
812 IF current_matrix_write = '0' THEN
725 IF current_matrix_write = '0' THEN
813 -- status_component_fifo_0_new <= '1';
814 status_component_fifo_0 <= status_component;
726 status_component_fifo_0 <= status_component;
815 ELSE
727 ELSE
816 -- status_component_fifo_1_new <= '1';
817 status_component_fifo_1 <= status_component;
728 status_component_fifo_1 <= status_component;
818 END IF;
729 END IF;
819 END IF;
730 END IF;
@@ -884,7 +795,7 BEGIN
884 fifo_0_ready <= '0';
795 fifo_0_ready <= '0';
885 fifo_1_ready <= '0';
796 fifo_1_ready <= '0';
886 fifo_ongoing <= '0';
797 fifo_ongoing <= '0';
887 ELSIF clk'event AND clk = '1' THEN
798 ELSIF clk'EVENT AND clk = '1' THEN
888 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
799 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
889 fifo_ongoing <= '1';
800 fifo_ongoing <= '1';
890 fifo_0_ready <= '0';
801 fifo_0_ready <= '0';
@@ -933,17 +844,6 BEGIN
933 fifo_empty => FSM_DMA_fifo_empty,
844 fifo_empty => FSM_DMA_fifo_empty,
934 fifo_ren => FSM_DMA_fifo_ren,
845 fifo_ren => FSM_DMA_fifo_ren,
935
846
936 ---- FIFO IN
937 --data_time => dma_time,
938
939 --fifo_data => HEAD_Data,
940 --fifo_empty => HEAD_Empty,
941 --fifo_ren => HEAD_Read,
942
943 --header => DMA_Header,
944 --header_val => DMA_Header_Val,
945 --header_ack => DMA_Header_Ack,
946
947 dma_addr => dma_addr,
847 dma_addr => dma_addr,
948 dma_data => dma_data,
848 dma_data => dma_data,
949 dma_valid => dma_valid,
849 dma_valid => dma_valid,
@@ -952,29 +852,25 BEGIN
952 dma_done => dma_done,
852 dma_done => dma_done,
953
853
954 ready_matrix_f0 => ready_matrix_f0,
854 ready_matrix_f0 => ready_matrix_f0,
955 -- ready_matrix_f0_1 => ready_matrix_f0_1,
956 ready_matrix_f1 => ready_matrix_f1,
855 ready_matrix_f1 => ready_matrix_f1,
957 ready_matrix_f2 => ready_matrix_f2,
856 ready_matrix_f2 => ready_matrix_f2,
958 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
857
959 error_bad_component_error => error_bad_component_error,
858 error_bad_component_error => error_bad_component_error,
960 error_buffer_full => error_buffer_full,
859 error_buffer_full => error_buffer_full,
860
961 debug_reg => debug_reg,
861 debug_reg => debug_reg,
962 status_ready_matrix_f0 => status_ready_matrix_f0,
862 status_ready_matrix_f0 => status_ready_matrix_f0,
963 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
964 status_ready_matrix_f1 => status_ready_matrix_f1,
863 status_ready_matrix_f1 => status_ready_matrix_f1,
965 status_ready_matrix_f2 => status_ready_matrix_f2,
864 status_ready_matrix_f2 => status_ready_matrix_f2,
966 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
865
967 -- status_error_bad_component_error => status_error_bad_component_error,
968 -- status_error_buffer_full => status_error_buffer_full,
969 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
866 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
970 config_active_interruption_onError => config_active_interruption_onError,
867 config_active_interruption_onError => config_active_interruption_onError,
868
971 addr_matrix_f0 => addr_matrix_f0,
869 addr_matrix_f0 => addr_matrix_f0,
972 -- addr_matrix_f0_1 => addr_matrix_f0_1,
973 addr_matrix_f1 => addr_matrix_f1,
870 addr_matrix_f1 => addr_matrix_f1,
974 addr_matrix_f2 => addr_matrix_f2,
871 addr_matrix_f2 => addr_matrix_f2,
975
872
976 matrix_time_f0 => matrix_time_f0,
873 matrix_time_f0 => matrix_time_f0,
977 -- matrix_time_f0_1 => matrix_time_f0_1,
978 matrix_time_f1 => matrix_time_f1,
874 matrix_time_f1 => matrix_time_f1,
979 matrix_time_f2 => matrix_time_f2
875 matrix_time_f2 => matrix_time_f2
980 );
876 );
@@ -984,24 +880,6 BEGIN
984
880
985
881
986
882
987
988
989
990
991
992
993 -----------------------------------------------------------------------------
994 -----------------------------------------------------------------------------
995 -----------------------------------------------------------------------------
996 -----------------------------------------------------------------------------
997 -----------------------------------------------------------------------------
998 -----------------------------------------------------------------------------
999
1000
1001
1002
1003
1004
1005 -----------------------------------------------------------------------------
883 -----------------------------------------------------------------------------
1006 -- TIME MANAGMENT
884 -- TIME MANAGMENT
1007 -----------------------------------------------------------------------------
885 -----------------------------------------------------------------------------
@@ -1059,8 +937,6 BEGIN
1059 time_out => time_reg_f2);
937 time_out => time_reg_f2);
1060
938
1061 -----------------------------------------------------------------------------
939 -----------------------------------------------------------------------------
1062 dma_time <= (OTHERS => '0'); -- TODO
1063 -----------------------------------------------------------------------------
1064
940
1065
941
1066
942
Show file before | Show file after | Hide comments
@@ -65,32 +65,25 ENTITY lpp_lfr_ms_fsmdma IS
65 ---------------------------------------------------------------------------
65 ---------------------------------------------------------------------------
66 -- Reg out
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
67 ready_matrix_f0 : OUT STD_LOGIC;
68 -- ready_matrix_f0_1 : OUT STD_LOGIC;
69 ready_matrix_f1 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
70 ready_matrix_f2 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
71 --error_anticipating_empty_fifo : OUT STD_LOGIC;
70
72 error_bad_component_error : OUT STD_LOGIC;
71 error_bad_component_error : OUT STD_LOGIC;
73 error_buffer_full : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
74 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
75
74
76 -- Reg In
75 -- Reg In
77 status_ready_matrix_f0 : IN STD_LOGIC;
76 status_ready_matrix_f0 : IN STD_LOGIC;
78 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
79 status_ready_matrix_f1 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
80 status_ready_matrix_f2 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
81 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
82 -- status_error_bad_component_error : IN STD_LOGIC;
83 -- status_error_buffer_full : IN STD_LOGIC;
84
79
85 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
86 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
87 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --s addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
91
85
92 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
93 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
94 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
95 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
96
89
@@ -114,27 +107,20 ARCHITECTURE Behavioral OF lpp_lfr_ms_fs
114 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
115 SIGNAL header_check_ok : STD_LOGIC;
108 SIGNAL header_check_ok : STD_LOGIC;
116 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
117 -- SIGNAL send_matrix : STD_LOGIC;
118 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
121
113
122 SIGNAL component_send : STD_LOGIC;
114 SIGNAL component_send : STD_LOGIC;
123 SIGNAL component_send_ok : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
124 -- SIGNAL component_send_ko : STD_LOGIC;
125 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
126 SIGNAL fifo_ren_trash : STD_LOGIC;
117 SIGNAL fifo_ren_trash : STD_LOGIC;
127 -- SIGNAL component_fifo_ren : STD_LOGIC;
128
118
129 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
130 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
132 SIGNAL log_empty_fifo : STD_LOGIC;
122 SIGNAL log_empty_fifo : STD_LOGIC;
133 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
134 --SIGNAL header_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
135 --SIGNAL header_reg_val : STD_LOGIC;
136 --SIGNAL header_reg_ack : STD_LOGIC;
137 -- SIGNAL header_error : STD_LOGIC;
138
124
139 SIGNAL matrix_buffer_ready : STD_LOGIC;
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
140 BEGIN
126 BEGIN
@@ -143,7 +129,6 BEGIN
143
129
144
130
145 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
146 --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
147 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
148 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
149 '0';
134 '0';
@@ -154,12 +139,11 BEGIN
154 '0';
139 '0';
155
140
156 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
157 --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
158 addr_matrix_f1 WHEN matrix_type = "01" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
159 addr_matrix_f2 WHEN matrix_type = "10" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
160 (OTHERS => '0');
144 (OTHERS => '0');
161
145
162 debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0');
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
163 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
164 -- DMA control
148 -- DMA control
165 -----------------------------------------------------------------------------
149 -----------------------------------------------------------------------------
@@ -170,10 +154,8 BEGIN
170 component_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
171 state <= IDLE;
155 state <= IDLE;
172 ready_matrix_f0 <= '0';
156 ready_matrix_f0 <= '0';
173 -- ready_matrix_f0_1 <= '0';
174 ready_matrix_f1 <= '0';
157 ready_matrix_f1 <= '0';
175 ready_matrix_f2 <= '0';
158 ready_matrix_f2 <= '0';
176 -- error_anticipating_empty_fifo <= '0';
177 error_bad_component_error <= '0';
159 error_bad_component_error <= '0';
178 error_buffer_full <= '0'; -- TODO
160 error_buffer_full <= '0'; -- TODO
179 component_type_pre <= "0000";
161 component_type_pre <= "0000";
@@ -182,6 +164,10 BEGIN
182 address <= (OTHERS => '0');
164 address <= (OTHERS => '0');
183
165
184 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
185
171
186 log_empty_fifo <= '0';
172 log_empty_fifo <= '0';
187
173
@@ -190,9 +176,21 BEGIN
190 matrix_time_f2 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
191
177
192 ELSIF HCLK'EVENT AND HCLK = '1' THEN
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
179 --
180 debug_reg_s(3) <= status_ready_matrix_f0;
181 debug_reg_s(4) <= status_ready_matrix_f0;
182 debug_reg_s(5) <= status_ready_matrix_f0;
183 debug_reg_s(6) <= '0';
184 debug_reg_s(7) <= '0';
185 debug_reg_s(8) <= '0';
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
188
189 --
190
191
193
192
194 ready_matrix_f0 <= '0';
193 ready_matrix_f0 <= '0';
195 -- ready_matrix_f0_1 <= '0';
196 ready_matrix_f1 <= '0';
194 ready_matrix_f1 <= '0';
197 ready_matrix_f2 <= '0';
195 ready_matrix_f2 <= '0';
198 error_bad_component_error <= '0';
196 error_bad_component_error <= '0';
@@ -237,7 +235,6 BEGIN
237 debug_reg_s(2 DOWNTO 0) <= "100";
235 debug_reg_s(2 DOWNTO 0) <= "100";
238
236
239 error_bad_component_error <= '0';
237 error_bad_component_error <= '0';
240 -- error_anticipating_empty_fifo <= '0';
241 IF fifo_empty = '1' THEN
238 IF fifo_empty = '1' THEN
242 state <= IDLE;
239 state <= IDLE;
243 fifo_ren_trash <= '1';
240 fifo_ren_trash <= '1';
@@ -246,15 +243,21 BEGIN
246 END IF;
243 END IF;
247
244
248 WHEN SEND_DATA =>
245 WHEN SEND_DATA =>
249 debug_reg_s(2 DOWNTO 0) <= "101";
246 debug_reg_s(2 DOWNTO 0) <= "010";
250
247
251 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
252 state <= IDLE;
249 state <= IDLE;
253 IF component_type = "1110" THEN
250 IF component_type = "1110" THEN
254 CASE matrix_type IS
251 CASE matrix_type IS
255 WHEN "00" => ready_matrix_f0 <= '1';
252 WHEN "00" =>
256 WHEN "01" => ready_matrix_f1 <= '1';
253 ready_matrix_f0 <= '1';
257 WHEN "10" => ready_matrix_f2 <= '1';
254 debug_reg_s(6) <= '1';
255 WHEN "01" =>
256 ready_matrix_f1 <= '1';
257 debug_reg_s(7) <= '1';
258 WHEN "10" =>
259 ready_matrix_f2 <= '1';
260 debug_reg_s(8) <= '1';
258 WHEN OTHERS => NULL;
261 WHEN OTHERS => NULL;
259 END CASE;
262 END CASE;
260 END IF;
263 END IF;
@@ -267,15 +270,12 BEGIN
267 WHEN WAIT_DATA_ACK =>
270 WHEN WAIT_DATA_ACK =>
268 log_empty_fifo <= fifo_empty OR log_empty_fifo;
271 log_empty_fifo <= fifo_empty OR log_empty_fifo;
269
272
270 debug_reg_s(2 DOWNTO 0) <= "110";
273 debug_reg_s(2 DOWNTO 0) <= "011";
271
274
272 component_send <= '0';
275 component_send <= '0';
273 IF component_send_ok = '1' THEN
276 IF component_send_ok = '1' THEN
274 address <= address + 64;
277 address <= address + 64;
275 state <= SEND_DATA;
278 state <= SEND_DATA;
276 -- ELSIF component_send_ko = '1' THEN
277 -- error_anticipating_empty_fifo <= '0';
278 -- state <= TRASH_FIFO;
279 END IF;
279 END IF;
280
280
281 WHEN OTHERS => NULL;
281 WHEN OTHERS => NULL;
@@ -291,6 +291,5 BEGIN
291 fifo_ren <= dma_ren AND fifo_ren_trash;
291 fifo_ren <= dma_ren AND fifo_ren_trash;
292
292
293 component_send_ok <= dma_done;
293 component_send_ok <= dma_done;
294 -- component_send_ko <= '0';
295
294
296 END Behavioral;
295 END Behavioral;
Show file before | Show file after | Hide comments
@@ -277,8 +277,6 PACKAGE lpp_lfr_pkg IS
277 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
277 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
278 END COMPONENT;
278 END COMPONENT;
279 -----------------------------------------------------------------------------
279 -----------------------------------------------------------------------------
280
281
282 COMPONENT lpp_lfr_apbreg
280 COMPONENT lpp_lfr_apbreg
283 GENERIC (
281 GENERIC (
284 nb_data_by_buffer_size : INTEGER;
282 nb_data_by_buffer_size : INTEGER;
@@ -299,30 +297,25 PACKAGE lpp_lfr_pkg IS
299 apbo : OUT apb_slv_out_type;
297 apbo : OUT apb_slv_out_type;
300 run_ms : OUT STD_LOGIC;
298 run_ms : OUT STD_LOGIC;
301 ready_matrix_f0_0 : IN STD_LOGIC;
299 ready_matrix_f0_0 : IN STD_LOGIC;
302 ready_matrix_f0_1 : IN STD_LOGIC;
303 ready_matrix_f1 : IN STD_LOGIC;
300 ready_matrix_f1 : IN STD_LOGIC;
304 ready_matrix_f2 : IN STD_LOGIC;
301 ready_matrix_f2 : IN STD_LOGIC;
305 error_anticipating_empty_fifo : IN STD_LOGIC;
306 error_bad_component_error : IN STD_LOGIC;
302 error_bad_component_error : IN STD_LOGIC;
303 error_buffer_full : in STD_LOGIC;
304 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
307 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
305 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
308 status_ready_matrix_f0_0 : OUT STD_LOGIC;
306 status_ready_matrix_f0_0 : OUT STD_LOGIC;
309 status_ready_matrix_f0_1 : OUT STD_LOGIC;
310 status_ready_matrix_f1 : OUT STD_LOGIC;
307 status_ready_matrix_f1 : OUT STD_LOGIC;
311 status_ready_matrix_f2 : OUT STD_LOGIC;
308 status_ready_matrix_f2 : OUT STD_LOGIC;
312 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
313 status_error_bad_component_error : OUT STD_LOGIC;
314 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
309 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
315 config_active_interruption_onError : OUT STD_LOGIC;
310 config_active_interruption_onError : OUT STD_LOGIC;
316 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
311 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
317 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
312 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
318 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
313 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320
321 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
315 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
322 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325
326 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
319 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
320 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
321 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -353,7 +346,6 PACKAGE lpp_lfr_pkg IS
353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
346 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
347 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
348 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356 ---------------------------------------------------------------------------
357 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
349 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
358 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
350 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
359 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
351 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -364,6 +356,8 PACKAGE lpp_lfr_pkg IS
364 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
356 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
365 END COMPONENT;
357 END COMPONENT;
366
358
359
360
367 COMPONENT lpp_top_ms
361 COMPONENT lpp_top_ms
368 GENERIC (
362 GENERIC (
369 Mem_use : INTEGER;
363 Mem_use : INTEGER;
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