diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
--- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
+++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
@@ -426,7 +426,7 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"00010B")  -- aa.bb.cc version
+      top_lfr_version        => X"00010C")  -- aa.bb.cc version
     PORT MAP (
       clk             => clk_25,
       rstn            => reset,
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
@@ -1,762 +1,770 @@
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
-USE ieee.numeric_std.ALL;
-
-LIBRARY lpp;
-USE lpp.lpp_ad_conv.ALL;
-USE lpp.iir_filter.ALL;
-USE lpp.FILTERcfg.ALL;
-USE lpp.lpp_memory.ALL;
-USE lpp.lpp_waveform_pkg.ALL;
-USE lpp.lpp_dma_pkg.ALL;
-USE lpp.lpp_top_lfr_pkg.ALL;
-USE lpp.lpp_lfr_pkg.ALL;
-USE lpp.general_purpose.ALL;
-
-LIBRARY techmap;
-USE techmap.gencomp.ALL;
-
-LIBRARY grlib;
-USE grlib.amba.ALL;
-USE grlib.stdlib.ALL;
-USE grlib.devices.ALL;
-USE GRLIB.DMA2AHB_Package.ALL;
-
-ENTITY lpp_lfr IS
-  GENERIC (
-    Mem_use                : INTEGER := use_RAM;
-    nb_data_by_buffer_size : INTEGER := 11;
-    nb_word_by_buffer_size : INTEGER := 11;
-    nb_snapshot_param_size : INTEGER := 11;
-    delta_vector_size      : INTEGER := 20;
-    delta_vector_size_f0_2 : INTEGER := 7;
-
-    pindex   : INTEGER := 4;
-    paddr    : INTEGER := 4;
-    pmask    : INTEGER := 16#fff#;
-    pirq_ms  : INTEGER := 0;
-    pirq_wfp : INTEGER := 1;
-
-    hindex : INTEGER := 2;
-
-    top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
-
-    );
-  PORT (
-    clk             : IN  STD_LOGIC;
-    rstn            : IN  STD_LOGIC;
-    -- SAMPLE
-    sample_B        : IN  Samples(2 DOWNTO 0);
-    sample_E        : IN  Samples(4 DOWNTO 0);
-    sample_val      : IN  STD_LOGIC;
-    -- APB
-    apbi            : IN  apb_slv_in_type;
-    apbo            : OUT apb_slv_out_type;
-    -- AHB
-    ahbi            : IN  AHB_Mst_In_Type;
-    ahbo            : OUT AHB_Mst_Out_Type;
-    -- TIME
-    coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
-    fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
-    -- 
-    data_shaping_BW : OUT STD_LOGIC;
-    --
-    observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-
-    --debug
-    --debug_f0_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
-    --debug_f0_data_valid : OUT STD_LOGIC;
-    --debug_f1_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
-    --debug_f1_data_valid : OUT STD_LOGIC;
-    --debug_f2_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
-    --debug_f2_data_valid : OUT STD_LOGIC;
-    --debug_f3_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
-    --debug_f3_data_valid : OUT STD_LOGIC;
-
-    ---- debug FIFO_IN
-    --debug_f0_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
-    --debug_f1_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
-    --debug_f2_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
-    --debug_f3_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
-
-    ----debug FIFO OUT
-    --debug_f0_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
-    --debug_f1_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
-    --debug_f2_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
-    --debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
-
-    ----debug DMA IN
-    --debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
-    --debug_f1_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
-    --debug_f2_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
-    --debug_f3_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    --debug_f3_data_dma_in_valid : OUT STD_LOGIC
-    );
-END lpp_lfr;
-
-ARCHITECTURE beh OF lpp_lfr IS
-  --SIGNAL sample           : Samples14v(7 DOWNTO 0);
-  SIGNAL sample_s         : Samples(7 DOWNTO 0);
-  --
-  SIGNAL data_shaping_SP0 : STD_LOGIC;
-  SIGNAL data_shaping_SP1 : STD_LOGIC;
-  SIGNAL data_shaping_R0  : STD_LOGIC;
-  SIGNAL data_shaping_R1  : STD_LOGIC;
-  --
-  SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  --
-  SIGNAL sample_f0_val    : STD_LOGIC;
-  SIGNAL sample_f1_val    : STD_LOGIC;
-  SIGNAL sample_f2_val    : STD_LOGIC;
-  SIGNAL sample_f3_val    : STD_LOGIC;
-  --
-  SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  --
-  SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-  SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-  SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-
-  -- SM
-  SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
-  SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
-  SIGNAL ready_matrix_f1                        : STD_LOGIC;
-  SIGNAL ready_matrix_f2                        : STD_LOGIC;
-  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
-  SIGNAL error_bad_component_error              : STD_LOGIC;
-  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
-  SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
-  SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
-  SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
-  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
-  SIGNAL status_error_bad_component_error       : STD_LOGIC;
-  SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
-  SIGNAL config_active_interruption_onError     : STD_LOGIC;
-  SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  -- WFP
-  SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
-  SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
-  SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
-  SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
-  SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
-
-  SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
-  SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
-  SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
-  SIGNAL enable_f0         : STD_LOGIC;
-  SIGNAL enable_f1         : STD_LOGIC;
-  SIGNAL enable_f2         : STD_LOGIC;
-  SIGNAL enable_f3         : STD_LOGIC;
-  SIGNAL burst_f0          : STD_LOGIC;
-  SIGNAL burst_f1          : STD_LOGIC;
-  SIGNAL burst_f2          : STD_LOGIC;
-  SIGNAL addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  SIGNAL run        : STD_LOGIC;
-  SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
-
-  SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f0_data_out_valid       : STD_LOGIC;
-  SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
-  SIGNAL data_f0_data_out_ren         : STD_LOGIC;
-  --f1
-  SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f1_data_out_valid       : STD_LOGIC;
-  SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
-  SIGNAL data_f1_data_out_ren         : STD_LOGIC;
-  --f2
-  SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f2_data_out_valid       : STD_LOGIC;
-  SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
-  SIGNAL data_f2_data_out_ren         : STD_LOGIC;
-  --f3
-  SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f3_data_out_valid       : STD_LOGIC;
-  SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
-  SIGNAL data_f3_data_out_ren         : STD_LOGIC;
-
-  -----------------------------------------------------------------------------
-  -- 
-  -----------------------------------------------------------------------------
-  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
-  --f1
-  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
-  --f2
-  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
-  --f3
-  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
-  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
-
-  -----------------------------------------------------------------------------
-  -- DMA RR
-  -----------------------------------------------------------------------------
-  SIGNAL dma_sel_valid   : STD_LOGIC;
-  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-
-  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
-
-  -----------------------------------------------------------------------------
-  -- DMA_REG
-  -----------------------------------------------------------------------------
-  SIGNAL ongoing_reg         : STD_LOGIC;
-  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  SIGNAL dma_send_reg        : STD_LOGIC;
-  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
-  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-
-  -----------------------------------------------------------------------------
-  -- DMA
-  -----------------------------------------------------------------------------
-  SIGNAL dma_send        : STD_LOGIC;
-  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
-  SIGNAL dma_done        : STD_LOGIC;
-  SIGNAL dma_ren         : STD_LOGIC;
-  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  -----------------------------------------------------------------------------
-  -- DEBUG
-  -----------------------------------------------------------------------------
-  --
-  SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-  SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
-
-  SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-  -----------------------------------------------------------------------------
-  -- MS
-  -----------------------------------------------------------------------------
-
-  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL data_ms_valid       : STD_LOGIC;
-  SIGNAL data_ms_valid_burst : STD_LOGIC;
-  SIGNAL data_ms_ren         : STD_LOGIC;
-  SIGNAL data_ms_done        : STD_LOGIC;
-
-  SIGNAL run_ms              : STD_LOGIC;
-  SIGNAL ms_softandhard_rstn : STD_LOGIC;
-  
-  SIGNAL matrix_time_f0_0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
-  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
-  SIGNAL matrix_time_f1      : STD_LOGIC_VECTOR(47 DOWNTO 0);
-  SIGNAL matrix_time_f2      : STD_LOGIC_VECTOR(47 DOWNTO 0);
-  
-  
-BEGIN
-  
-  sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
-  sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
-
-  --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
-  --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
-  --END GENERATE all_channel;
-
-  -----------------------------------------------------------------------------
-  lpp_lfr_filter_1 : lpp_lfr_filter
-    GENERIC MAP (
-      Mem_use => Mem_use)
-    PORT MAP (
-      sample           => sample_s,
-      sample_val       => sample_val,
-      clk              => clk,
-      rstn             => rstn,
-      data_shaping_SP0 => data_shaping_SP0,
-      data_shaping_SP1 => data_shaping_SP1,
-      data_shaping_R0  => data_shaping_R0,
-      data_shaping_R1  => data_shaping_R1,
-      sample_f0_val    => sample_f0_val,
-      sample_f1_val    => sample_f1_val,
-      sample_f2_val    => sample_f2_val,
-      sample_f3_val    => sample_f3_val,
-      sample_f0_wdata  => sample_f0_data,
-      sample_f1_wdata  => sample_f1_data,
-      sample_f2_wdata  => sample_f2_data,
-      sample_f3_wdata  => sample_f3_data);
-
-  -----------------------------------------------------------------------------
-  lpp_lfr_apbreg_1 : lpp_lfr_apbreg
-    GENERIC MAP (
-      nb_data_by_buffer_size => nb_data_by_buffer_size,
-      nb_word_by_buffer_size => nb_word_by_buffer_size,
-      nb_snapshot_param_size => nb_snapshot_param_size,
-      delta_vector_size      => delta_vector_size,
-      delta_vector_size_f0_2 => delta_vector_size_f0_2,
-      pindex                 => pindex,
-      paddr                  => paddr,
-      pmask                  => pmask,
-      pirq_ms                => pirq_ms,
-      pirq_wfp               => pirq_wfp,
-      top_lfr_version        => top_lfr_version)
-    PORT MAP (
-      HCLK    => clk,
-      HRESETn => rstn,
-      apbi    => apbi,
-      apbo    => apbo,
-
-      run_ms => run_ms,
-
-      ready_matrix_f0_0                      => ready_matrix_f0_0,
-      ready_matrix_f0_1                      => ready_matrix_f0_1,
-      ready_matrix_f1                        => ready_matrix_f1,
-      ready_matrix_f2                        => ready_matrix_f2,
-      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
-      error_bad_component_error              => error_bad_component_error,
-      debug_reg                              => debug_reg,
-      status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
-      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
-      status_ready_matrix_f1                 => status_ready_matrix_f1,
-      status_ready_matrix_f2                 => status_ready_matrix_f2,
-      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
-      status_error_bad_component_error       => status_error_bad_component_error,
-      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
-      config_active_interruption_onError     => config_active_interruption_onError,
-
-      matrix_time_f0_0 => matrix_time_f0_0,
-      matrix_time_f0_1 => matrix_time_f0_1,
-      matrix_time_f1   => matrix_time_f1,
-      matrix_time_f2   => matrix_time_f2,
-
-      addr_matrix_f0_0  => addr_matrix_f0_0,
-      addr_matrix_f0_1  => addr_matrix_f0_1,
-      addr_matrix_f1    => addr_matrix_f1,
-      addr_matrix_f2    => addr_matrix_f2,
-      status_full       => status_full,
-      status_full_ack   => status_full_ack,
-      status_full_err   => status_full_err,
-      status_new_err    => status_new_err,
-      data_shaping_BW   => data_shaping_BW,
-      data_shaping_SP0  => data_shaping_SP0,
-      data_shaping_SP1  => data_shaping_SP1,
-      data_shaping_R0   => data_shaping_R0,
-      data_shaping_R1   => data_shaping_R1,
-      delta_snapshot    => delta_snapshot,
-      delta_f0          => delta_f0,
-      delta_f0_2        => delta_f0_2,
-      delta_f1          => delta_f1,
-      delta_f2          => delta_f2,
-      nb_data_by_buffer => nb_data_by_buffer,
-      nb_word_by_buffer => nb_word_by_buffer,
-      nb_snapshot_param => nb_snapshot_param,
-      enable_f0         => enable_f0,
-      enable_f1         => enable_f1,
-      enable_f2         => enable_f2,
-      enable_f3         => enable_f3,
-      burst_f0          => burst_f0,
-      burst_f1          => burst_f1,
-      burst_f2          => burst_f2,
-      run               => run,
-      addr_data_f0      => addr_data_f0,
-      addr_data_f1      => addr_data_f1,
-      addr_data_f2      => addr_data_f2,
-      addr_data_f3      => addr_data_f3,
-      start_date        => start_date,
-      ---------------------------------------------------------------------------
-      debug_reg0        => debug_reg0,
-      debug_reg1        => debug_reg1,
-      debug_reg2        => debug_reg2,
-      debug_reg3        => debug_reg3,
-      debug_reg4        => debug_reg4,
-      debug_reg5        => debug_reg5,
-      debug_reg6        => debug_reg6,
-      debug_reg7        => debug_reg7);
-
-  debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
-  debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
-  debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
-  -----------------------------------------------------------------------------
-  --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357";  -- TODO : debug
-  --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB";  -- TODO : debug
-  --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773";  -- TODO : debug
-  --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612";  -- TODO : debug
-
-
-  -----------------------------------------------------------------------------
-  lpp_waveform_1 : lpp_waveform
-    GENERIC MAP (
-      tech                   => inferred,
-      data_size              => 6*16,
-      nb_data_by_buffer_size => nb_data_by_buffer_size,
-      nb_word_by_buffer_size => nb_word_by_buffer_size,
-      nb_snapshot_param_size => nb_snapshot_param_size,
-      delta_vector_size      => delta_vector_size,
-      delta_vector_size_f0_2 => delta_vector_size_f0_2
-      )
-    PORT MAP (
-      clk  => clk,
-      rstn => rstn,
-
-      reg_run            => run,
-      reg_start_date     => start_date,
-      reg_delta_snapshot => delta_snapshot,
-      reg_delta_f0       => delta_f0,
-      reg_delta_f0_2     => delta_f0_2,
-      reg_delta_f1       => delta_f1,
-      reg_delta_f2       => delta_f2,
-
-      enable_f0 => enable_f0,
-      enable_f1 => enable_f1,
-      enable_f2 => enable_f2,
-      enable_f3 => enable_f3,
-      burst_f0  => burst_f0,
-      burst_f1  => burst_f1,
-      burst_f2  => burst_f2,
-
-      nb_data_by_buffer => nb_data_by_buffer,
-      nb_word_by_buffer => nb_word_by_buffer,
-      nb_snapshot_param => nb_snapshot_param,
-      status_full       => status_full,
-      status_full_ack   => status_full_ack,
-      status_full_err   => status_full_err,
-      status_new_err    => status_new_err,
-
-      coarse_time => coarse_time,
-      fine_time   => fine_time,
-
-      --f0
-      addr_data_f0                 => addr_data_f0,
-      data_f0_in_valid             => sample_f0_val,
-      data_f0_in                   => sample_f0_data,  -- sample_f0_data_debug,  -- TODO : debug
-      --f1
-      addr_data_f1                 => addr_data_f1,
-      data_f1_in_valid             => sample_f1_val,
-      data_f1_in                   => sample_f1_data,  -- sample_f1_data_debug,  -- TODO : debug,
-      --f2
-      addr_data_f2                 => addr_data_f2,
-      data_f2_in_valid             => sample_f2_val,
-      data_f2_in                   => sample_f2_data,  -- sample_f2_data_debug,  -- TODO : debug,
-      --f3
-      addr_data_f3                 => addr_data_f3,
-      data_f3_in_valid             => sample_f3_val,
-      data_f3_in                   => sample_f3_data,  -- sample_f3_data_debug,  -- TODO : debug,
-      -- OUTPUT -- DMA interface
-      --f0
-      data_f0_addr_out             => data_f0_addr_out_s,
-      data_f0_data_out             => data_f0_data_out,
-      data_f0_data_out_valid       => data_f0_data_out_valid_s,
-      data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
-      data_f0_data_out_ren         => data_f0_data_out_ren,
-      --f1
-      data_f1_addr_out             => data_f1_addr_out_s,
-      data_f1_data_out             => data_f1_data_out,
-      data_f1_data_out_valid       => data_f1_data_out_valid_s,
-      data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
-      data_f1_data_out_ren         => data_f1_data_out_ren,
-      --f2
-      data_f2_addr_out             => data_f2_addr_out_s,
-      data_f2_data_out             => data_f2_data_out,
-      data_f2_data_out_valid       => data_f2_data_out_valid_s,
-      data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
-      data_f2_data_out_ren         => data_f2_data_out_ren,
-      --f3
-      data_f3_addr_out             => data_f3_addr_out_s,
-      data_f3_data_out             => data_f3_data_out,
-      data_f3_data_out_valid       => data_f3_data_out_valid_s,
-      data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
-      data_f3_data_out_ren         => data_f3_data_out_ren ,
-
-      -------------------------------------------------------------------------
-      observation_reg => OPEN 
-
-      );
-
-
-  -----------------------------------------------------------------------------
-  -- TEMP
-  -----------------------------------------------------------------------------
-
-  PROCESS (clk, rstn)
-  BEGIN  -- PROCESS
-    IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      data_f0_data_out_valid       <= '0';
-      data_f0_data_out_valid_burst <= '0';
-      data_f1_data_out_valid       <= '0';
-      data_f1_data_out_valid_burst <= '0';
-      data_f2_data_out_valid       <= '0';
-      data_f2_data_out_valid_burst <= '0';
-      data_f3_data_out_valid       <= '0';
-      data_f3_data_out_valid_burst <= '0';
-    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge        
-      data_f0_data_out_valid       <= data_f0_data_out_valid_s;
-      data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
-      data_f1_data_out_valid       <= data_f1_data_out_valid_s;
-      data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
-      data_f2_data_out_valid       <= data_f2_data_out_valid_s;
-      data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
-      data_f3_data_out_valid       <= data_f3_data_out_valid_s;
-      data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
-    END IF;
-  END PROCESS;
-
-  data_f0_addr_out <= data_f0_addr_out_s;
-  data_f1_addr_out <= data_f1_addr_out_s;
-  data_f2_addr_out <= data_f2_addr_out_s;
-  data_f3_addr_out <= data_f3_addr_out_s;
-
-  -----------------------------------------------------------------------------
-  -- RoundRobin Selection For DMA
-  -----------------------------------------------------------------------------
-
-  dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
-  dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
-  dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
-  dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
-
-  RR_Arbiter_4_1 : RR_Arbiter_4
-    PORT MAP (
-      clk       => clk,
-      rstn      => rstn,
-      in_valid  => dma_rr_valid,
-      out_grant => dma_rr_grant_s);
-
-  dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
-  dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
-  dma_rr_valid_ms(2) <= '0';
-  dma_rr_valid_ms(3) <= '0';
-
-  RR_Arbiter_4_2 : RR_Arbiter_4
-    PORT MAP (
-      clk       => clk,
-      rstn      => rstn,
-      in_valid  => dma_rr_valid_ms,
-      out_grant => dma_rr_grant_ms);
-
-  dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
-
-
-  -----------------------------------------------------------------------------
-  -- in  : dma_rr_grant
-  --       send
-  -- out : dma_sel
-  --       dma_valid_burst
-  --       dma_sel_valid
-  -----------------------------------------------------------------------------
-  PROCESS (clk, rstn)
-  BEGIN  -- PROCESS
-    IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      dma_sel         <= (OTHERS => '0');
-      dma_send        <= '0';
-      dma_valid_burst <= '0';
-      data_ms_done    <= '0';
-    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-      IF run = '1' THEN
-        data_ms_done <= '0';
-        IF dma_sel = "00000" OR dma_done = '1' THEN
-          dma_sel <= dma_rr_grant;
-          IF dma_rr_grant(0) = '1' THEN
-            dma_send        <= '1';
-            dma_valid_burst <= data_f0_data_out_valid_burst;
-            dma_sel_valid   <= data_f0_data_out_valid;
-          ELSIF dma_rr_grant(1) = '1' THEN
-            dma_send        <= '1';
-            dma_valid_burst <= data_f1_data_out_valid_burst;
-            dma_sel_valid   <= data_f1_data_out_valid;
-          ELSIF dma_rr_grant(2) = '1' THEN
-            dma_send        <= '1';
-            dma_valid_burst <= data_f2_data_out_valid_burst;
-            dma_sel_valid   <= data_f2_data_out_valid;
-          ELSIF dma_rr_grant(3) = '1' THEN
-            dma_send        <= '1';
-            dma_valid_burst <= data_f3_data_out_valid_burst;
-            dma_sel_valid   <= data_f3_data_out_valid;
-          ELSIF dma_rr_grant(4) = '1' THEN
-            dma_send        <= '1';
-            dma_valid_burst <= data_ms_valid_burst;
-            dma_sel_valid   <= data_ms_valid;
-          END IF;
-
-          IF dma_sel(4) = '1' THEN
-            data_ms_done <= '1';
-          END IF;
-        ELSE
-          dma_sel  <= dma_sel;
-          dma_send <= '0';
-        END IF;
-      ELSE
-        data_ms_done    <= '0';
-        dma_sel         <= (OTHERS => '0');
-        dma_send        <= '0';
-        dma_valid_burst <= '0';
-      END IF;
-    END IF;
-  END PROCESS;
-
-
-  dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
-                 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
-                 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
-                 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
-                 data_ms_addr;
-  
-  dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
-              data_f1_data_out WHEN dma_sel(1) = '1' ELSE
-              data_f2_data_out WHEN dma_sel(2) = '1' ELSE
-              data_f3_data_out WHEN dma_sel(3) = '1' ELSE
-              data_ms_data;
-  
-  data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
-  data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
-  data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
-  data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
-  data_ms_ren          <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
-
-  dma_data_2 <= dma_data;
-
-
-
-
-
-  -----------------------------------------------------------------------------
-  -- DEBUG -- DMA IN
-  --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
-  --debug_f0_data_dma_in       <= dma_data;
-  --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
-  --debug_f1_data_dma_in       <= dma_data;
-  --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
-  --debug_f2_data_dma_in       <= dma_data;
-  --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
-  --debug_f3_data_dma_in       <= dma_data;
-  -----------------------------------------------------------------------------
-
-  -----------------------------------------------------------------------------
-  -- DMA
-  -----------------------------------------------------------------------------
-  lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
-    GENERIC MAP (
-      tech   => inferred,
-      hindex => hindex)
-    PORT MAP (
-      HCLK           => clk,
-      HRESETn        => rstn,
-      run            => run,
-      AHB_Master_In  => ahbi,
-      AHB_Master_Out => ahbo,
-
-      send        => dma_send,
-      valid_burst => dma_valid_burst,
-      done        => dma_done,
-      ren         => dma_ren,
-      address     => dma_address,
-      data        => dma_data_2);       
-
-  -----------------------------------------------------------------------------
-  -- Matrix Spectral
-  -----------------------------------------------------------------------------
-  sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
-                   NOT(sample_f0_val) & NOT(sample_f0_val);
-  sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
-                   NOT(sample_f1_val) & NOT(sample_f1_val);
-  sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
-                   NOT(sample_f3_val) & NOT(sample_f3_val);
-
-  sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
-  sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
-  sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
-
-  -------------------------------------------------------------------------------
-
-  ms_softandhard_rstn <= rstn AND run_ms AND run;
-
-  -----------------------------------------------------------------------------
-  lpp_lfr_ms_1 : lpp_lfr_ms
-    GENERIC MAP (
-      Mem_use => Mem_use)
-    PORT MAP (
-      clk  => clk,
-      rstn => ms_softandhard_rstn,      --rstn,
-
-      coarse_time => coarse_time,
-      fine_time   => fine_time,
-
-      sample_f0_wen   => sample_f0_wen,
-      sample_f0_wdata => sample_f0_wdata,
-      sample_f1_wen   => sample_f1_wen,
-      sample_f1_wdata => sample_f1_wdata,
-      sample_f2_wen   => sample_f3_wen,  -- TODO verify that it's the good data
-      sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data
-
-      dma_addr        => data_ms_addr,         --
-      dma_data        => data_ms_data,         --
-      dma_valid       => data_ms_valid,        --
-      dma_valid_burst => data_ms_valid_burst,  --
-      dma_ren         => data_ms_ren,          --
-      dma_done        => data_ms_done,         --
-
-      ready_matrix_f0                        => ready_matrix_f0_0,-- TODO rename
-      ready_matrix_f1                        => ready_matrix_f1,
-      ready_matrix_f2                        => ready_matrix_f2,
-      --error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
-      error_bad_component_error              => error_bad_component_error,
-      error_buffer_full             => OPEN,  -- TODO
-      error_input_fifo_write        => OPEN,  -- TODO
-      debug_reg                              => observation_reg,  
-      status_ready_matrix_f0                 => status_ready_matrix_f0_0,-- TODO rename
-      status_ready_matrix_f1                 => status_ready_matrix_f1,
-      status_ready_matrix_f2                 => status_ready_matrix_f2,
---      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,-- TODO
---      status_error_bad_component_error       => status_error_bad_component_error,-- TODO
-      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
-      config_active_interruption_onError     => config_active_interruption_onError,
-      addr_matrix_f0                         => addr_matrix_f0_0,-- TODO rename
-      addr_matrix_f1                         => addr_matrix_f1,
-      addr_matrix_f2                         => addr_matrix_f2,
-
-      matrix_time_f0                         => matrix_time_f0_0,-- TODO rename
-      matrix_time_f1                         => matrix_time_f1,
-      matrix_time_f2                         => matrix_time_f2);
-
-END beh;
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY lpp;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.iir_filter.ALL;
+USE lpp.FILTERcfg.ALL;
+USE lpp.lpp_memory.ALL;
+USE lpp.lpp_waveform_pkg.ALL;
+USE lpp.lpp_dma_pkg.ALL;
+USE lpp.lpp_top_lfr_pkg.ALL;
+USE lpp.lpp_lfr_pkg.ALL;
+USE lpp.general_purpose.ALL;
+
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+USE grlib.devices.ALL;
+USE GRLIB.DMA2AHB_Package.ALL;
+
+ENTITY lpp_lfr IS
+  GENERIC (
+    Mem_use                : INTEGER := use_RAM;
+    nb_data_by_buffer_size : INTEGER := 11;
+    nb_word_by_buffer_size : INTEGER := 11;
+    nb_snapshot_param_size : INTEGER := 11;
+    delta_vector_size      : INTEGER := 20;
+    delta_vector_size_f0_2 : INTEGER := 7;
+
+    pindex   : INTEGER := 4;
+    paddr    : INTEGER := 4;
+    pmask    : INTEGER := 16#fff#;
+    pirq_ms  : INTEGER := 0;
+    pirq_wfp : INTEGER := 1;
+
+    hindex : INTEGER := 2;
+
+    top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
+
+    );
+  PORT (
+    clk             : IN  STD_LOGIC;
+    rstn            : IN  STD_LOGIC;
+    -- SAMPLE
+    sample_B        : IN  Samples(2 DOWNTO 0);
+    sample_E        : IN  Samples(4 DOWNTO 0);
+    sample_val      : IN  STD_LOGIC;
+    -- APB
+    apbi            : IN  apb_slv_in_type;
+    apbo            : OUT apb_slv_out_type;
+    -- AHB
+    ahbi            : IN  AHB_Mst_In_Type;
+    ahbo            : OUT AHB_Mst_Out_Type;
+    -- TIME
+    coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
+    fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
+    -- 
+    data_shaping_BW : OUT STD_LOGIC;
+    --
+    observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+
+    --debug
+    --debug_f0_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+    --debug_f0_data_valid : OUT STD_LOGIC;
+    --debug_f1_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+    --debug_f1_data_valid : OUT STD_LOGIC;
+    --debug_f2_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+    --debug_f2_data_valid : OUT STD_LOGIC;
+    --debug_f3_data       : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
+    --debug_f3_data_valid : OUT STD_LOGIC;
+
+    ---- debug FIFO_IN
+    --debug_f0_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
+    --debug_f1_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
+    --debug_f2_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
+    --debug_f3_data_fifo_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
+
+    ----debug FIFO OUT
+    --debug_f0_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
+    --debug_f1_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
+    --debug_f2_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
+    --debug_f3_data_fifo_out       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
+
+    ----debug DMA IN
+    --debug_f0_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
+    --debug_f1_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
+    --debug_f2_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
+    --debug_f3_data_dma_in       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    --debug_f3_data_dma_in_valid : OUT STD_LOGIC
+    );
+END lpp_lfr;
+
+ARCHITECTURE beh OF lpp_lfr IS
+  --SIGNAL sample           : Samples14v(7 DOWNTO 0);
+  SIGNAL sample_s         : Samples(7 DOWNTO 0);
+  --
+  SIGNAL data_shaping_SP0 : STD_LOGIC;
+  SIGNAL data_shaping_SP1 : STD_LOGIC;
+  SIGNAL data_shaping_R0  : STD_LOGIC;
+  SIGNAL data_shaping_R1  : STD_LOGIC;
+  --
+  SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  --
+  SIGNAL sample_f0_val    : STD_LOGIC;
+  SIGNAL sample_f1_val    : STD_LOGIC;
+  SIGNAL sample_f2_val    : STD_LOGIC;
+  SIGNAL sample_f3_val    : STD_LOGIC;
+  --
+  SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  --
+  SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+  SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+  SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+
+  -- SM
+  SIGNAL ready_matrix_f0_0                      : STD_LOGIC;
+  SIGNAL ready_matrix_f0_1                      : STD_LOGIC;
+  SIGNAL ready_matrix_f1                        : STD_LOGIC;
+  SIGNAL ready_matrix_f2                        : STD_LOGIC;
+--  SIGNAL error_anticipating_empty_fifo          : STD_LOGIC;
+  SIGNAL error_bad_component_error              : STD_LOGIC;
+  SIGNAL debug_reg                              : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL status_ready_matrix_f0_0               : STD_LOGIC;
+  SIGNAL status_ready_matrix_f0_1               : STD_LOGIC;
+  SIGNAL status_ready_matrix_f1                 : STD_LOGIC;
+  SIGNAL status_ready_matrix_f2                 : STD_LOGIC;
+--  SIGNAL status_error_anticipating_empty_fifo   : STD_LOGIC;
+--  SIGNAL status_error_bad_component_error       : STD_LOGIC;
+  SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
+  SIGNAL config_active_interruption_onError     : STD_LOGIC;
+  SIGNAL addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SIGNAL addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  -- WFP
+  SIGNAL status_full     : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
+  SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
+  SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
+  SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
+  SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
+
+  SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
+  SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
+  SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
+  SIGNAL enable_f0         : STD_LOGIC;
+  SIGNAL enable_f1         : STD_LOGIC;
+  SIGNAL enable_f2         : STD_LOGIC;
+  SIGNAL enable_f3         : STD_LOGIC;
+  SIGNAL burst_f0          : STD_LOGIC;
+  SIGNAL burst_f1          : STD_LOGIC;
+  SIGNAL burst_f2          : STD_LOGIC;
+  SIGNAL addr_data_f0      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f1      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL addr_data_f3      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  SIGNAL run        : STD_LOGIC;
+  SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
+
+  SIGNAL data_f0_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f0_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f0_data_out_valid       : STD_LOGIC;
+  SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
+  SIGNAL data_f0_data_out_ren         : STD_LOGIC;
+  --f1
+  SIGNAL data_f1_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f1_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f1_data_out_valid       : STD_LOGIC;
+  SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
+  SIGNAL data_f1_data_out_ren         : STD_LOGIC;
+  --f2
+  SIGNAL data_f2_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f2_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f2_data_out_valid       : STD_LOGIC;
+  SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
+  SIGNAL data_f2_data_out_ren         : STD_LOGIC;
+  --f3
+  SIGNAL data_f3_addr_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f3_data_out             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f3_data_out_valid       : STD_LOGIC;
+  SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
+  SIGNAL data_f3_data_out_ren         : STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  -- 
+  -----------------------------------------------------------------------------
+  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
+  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
+  --f1
+  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
+  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
+  --f2
+  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
+  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
+  --f3
+  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
+  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
+
+  -----------------------------------------------------------------------------
+  -- DMA RR
+  -----------------------------------------------------------------------------
+  SIGNAL dma_sel_valid   : STD_LOGIC;
+  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
+  -----------------------------------------------------------------------------
+  -- DMA_REG
+  -----------------------------------------------------------------------------
+  SIGNAL ongoing_reg         : STD_LOGIC;
+  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+  SIGNAL dma_send_reg        : STD_LOGIC;
+  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
+  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+
+  -----------------------------------------------------------------------------
+  -- DMA
+  -----------------------------------------------------------------------------
+  SIGNAL dma_send        : STD_LOGIC;
+  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
+  SIGNAL dma_done        : STD_LOGIC;
+  SIGNAL dma_ren         : STD_LOGIC;
+  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  -----------------------------------------------------------------------------
+  -- DEBUG
+  -----------------------------------------------------------------------------
+  --
+  SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+  SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
+
+  SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  -----------------------------------------------------------------------------
+  -- MS
+  -----------------------------------------------------------------------------
+
+  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL data_ms_valid       : STD_LOGIC;
+  SIGNAL data_ms_valid_burst : STD_LOGIC;
+  SIGNAL data_ms_ren         : STD_LOGIC;
+  SIGNAL data_ms_done        : STD_LOGIC;
+
+  SIGNAL run_ms              : STD_LOGIC;
+  SIGNAL ms_softandhard_rstn : STD_LOGIC;
+  
+  SIGNAL matrix_time_f0_0    : STD_LOGIC_VECTOR(47 DOWNTO 0);
+--  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  SIGNAL matrix_time_f1      : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  SIGNAL matrix_time_f2      : STD_LOGIC_VECTOR(47 DOWNTO 0);
+  
+  
+  SIGNAL error_buffer_full         :  STD_LOGIC;
+  SIGNAL error_input_fifo_write    :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+  
+BEGIN
+  
+  sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
+  sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
+
+  --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
+  --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
+  --END GENERATE all_channel;
+
+  -----------------------------------------------------------------------------
+  lpp_lfr_filter_1 : lpp_lfr_filter
+    GENERIC MAP (
+      Mem_use => Mem_use)
+    PORT MAP (
+      sample           => sample_s,
+      sample_val       => sample_val,
+      clk              => clk,
+      rstn             => rstn,
+      data_shaping_SP0 => data_shaping_SP0,
+      data_shaping_SP1 => data_shaping_SP1,
+      data_shaping_R0  => data_shaping_R0,
+      data_shaping_R1  => data_shaping_R1,
+      sample_f0_val    => sample_f0_val,
+      sample_f1_val    => sample_f1_val,
+      sample_f2_val    => sample_f2_val,
+      sample_f3_val    => sample_f3_val,
+      sample_f0_wdata  => sample_f0_data,
+      sample_f1_wdata  => sample_f1_data,
+      sample_f2_wdata  => sample_f2_data,
+      sample_f3_wdata  => sample_f3_data);
+
+  -----------------------------------------------------------------------------
+  lpp_lfr_apbreg_1 : lpp_lfr_apbreg
+    GENERIC MAP (
+      nb_data_by_buffer_size => nb_data_by_buffer_size,
+      nb_word_by_buffer_size => nb_word_by_buffer_size,
+      nb_snapshot_param_size => nb_snapshot_param_size,
+      delta_vector_size      => delta_vector_size,
+      delta_vector_size_f0_2 => delta_vector_size_f0_2,
+      pindex                 => pindex,
+      paddr                  => paddr,
+      pmask                  => pmask,
+      pirq_ms                => pirq_ms,
+      pirq_wfp               => pirq_wfp,
+      top_lfr_version        => top_lfr_version)
+    PORT MAP (
+      HCLK    => clk,
+      HRESETn => rstn,
+      apbi    => apbi,
+      apbo    => apbo,
+
+      run_ms => run_ms,
+
+      ready_matrix_f0_0                      => ready_matrix_f0_0,
+--      ready_matrix_f0_1                      => ready_matrix_f0_1,
+      ready_matrix_f1                        => ready_matrix_f1,
+      ready_matrix_f2                        => ready_matrix_f2,
+--      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
+      error_bad_component_error              => error_bad_component_error,
+      error_buffer_full                      => error_buffer_full,      -- TODO
+      error_input_fifo_write                 => error_input_fifo_write, -- TODO
+      debug_reg                              => debug_reg,
+      status_ready_matrix_f0_0               => status_ready_matrix_f0_0,
+--      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
+      status_ready_matrix_f1                 => status_ready_matrix_f1,
+      status_ready_matrix_f2                 => status_ready_matrix_f2,
+--      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
+--      status_error_bad_component_error       => status_error_bad_component_error,
+      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
+      config_active_interruption_onError     => config_active_interruption_onError,
+
+      matrix_time_f0_0 => matrix_time_f0_0,
+--      matrix_time_f0_1 => matrix_time_f0_1,
+      matrix_time_f1   => matrix_time_f1,
+      matrix_time_f2   => matrix_time_f2,
+
+      addr_matrix_f0_0  => addr_matrix_f0_0,
+--      addr_matrix_f0_1  => addr_matrix_f0_1,
+      addr_matrix_f1    => addr_matrix_f1,
+      addr_matrix_f2    => addr_matrix_f2,
+      -------------------------------------------------------------------------
+      status_full       => status_full,
+      status_full_ack   => status_full_ack,
+      status_full_err   => status_full_err,
+      status_new_err    => status_new_err,
+      data_shaping_BW   => data_shaping_BW,
+      data_shaping_SP0  => data_shaping_SP0,
+      data_shaping_SP1  => data_shaping_SP1,
+      data_shaping_R0   => data_shaping_R0,
+      data_shaping_R1   => data_shaping_R1,
+      delta_snapshot    => delta_snapshot,
+      delta_f0          => delta_f0,
+      delta_f0_2        => delta_f0_2,
+      delta_f1          => delta_f1,
+      delta_f2          => delta_f2,
+      nb_data_by_buffer => nb_data_by_buffer,
+      nb_word_by_buffer => nb_word_by_buffer,
+      nb_snapshot_param => nb_snapshot_param,
+      enable_f0         => enable_f0,
+      enable_f1         => enable_f1,
+      enable_f2         => enable_f2,
+      enable_f3         => enable_f3,
+      burst_f0          => burst_f0,
+      burst_f1          => burst_f1,
+      burst_f2          => burst_f2,
+      run               => run,
+      addr_data_f0      => addr_data_f0,
+      addr_data_f1      => addr_data_f1,
+      addr_data_f2      => addr_data_f2,
+      addr_data_f3      => addr_data_f3,
+      start_date        => start_date,
+      ---------------------------------------------------------------------------
+      debug_reg0        => debug_reg0,
+      debug_reg1        => debug_reg1,
+      debug_reg2        => debug_reg2,
+      debug_reg3        => debug_reg3,
+      debug_reg4        => debug_reg4,
+      debug_reg5        => debug_reg5,
+      debug_reg6        => debug_reg6,
+      debug_reg7        => debug_reg7);
+
+  debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
+  debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
+  debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
+  -----------------------------------------------------------------------------
+  --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357";  -- TODO : debug
+  --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB";  -- TODO : debug
+  --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773";  -- TODO : debug
+  --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612";  -- TODO : debug
+
+
+  -----------------------------------------------------------------------------
+  lpp_waveform_1 : lpp_waveform
+    GENERIC MAP (
+      tech                   => inferred,
+      data_size              => 6*16,
+      nb_data_by_buffer_size => nb_data_by_buffer_size,
+      nb_word_by_buffer_size => nb_word_by_buffer_size,
+      nb_snapshot_param_size => nb_snapshot_param_size,
+      delta_vector_size      => delta_vector_size,
+      delta_vector_size_f0_2 => delta_vector_size_f0_2
+      )
+    PORT MAP (
+      clk  => clk,
+      rstn => rstn,
+
+      reg_run            => run,
+      reg_start_date     => start_date,
+      reg_delta_snapshot => delta_snapshot,
+      reg_delta_f0       => delta_f0,
+      reg_delta_f0_2     => delta_f0_2,
+      reg_delta_f1       => delta_f1,
+      reg_delta_f2       => delta_f2,
+
+      enable_f0 => enable_f0,
+      enable_f1 => enable_f1,
+      enable_f2 => enable_f2,
+      enable_f3 => enable_f3,
+      burst_f0  => burst_f0,
+      burst_f1  => burst_f1,
+      burst_f2  => burst_f2,
+
+      nb_data_by_buffer => nb_data_by_buffer,
+      nb_word_by_buffer => nb_word_by_buffer,
+      nb_snapshot_param => nb_snapshot_param,
+      status_full       => status_full,
+      status_full_ack   => status_full_ack,
+      status_full_err   => status_full_err,
+      status_new_err    => status_new_err,
+
+      coarse_time => coarse_time,
+      fine_time   => fine_time,
+
+      --f0
+      addr_data_f0                 => addr_data_f0,
+      data_f0_in_valid             => sample_f0_val,
+      data_f0_in                   => sample_f0_data,  -- sample_f0_data_debug,  -- TODO : debug
+      --f1
+      addr_data_f1                 => addr_data_f1,
+      data_f1_in_valid             => sample_f1_val,
+      data_f1_in                   => sample_f1_data,  -- sample_f1_data_debug,  -- TODO : debug,
+      --f2
+      addr_data_f2                 => addr_data_f2,
+      data_f2_in_valid             => sample_f2_val,
+      data_f2_in                   => sample_f2_data,  -- sample_f2_data_debug,  -- TODO : debug,
+      --f3
+      addr_data_f3                 => addr_data_f3,
+      data_f3_in_valid             => sample_f3_val,
+      data_f3_in                   => sample_f3_data,  -- sample_f3_data_debug,  -- TODO : debug,
+      -- OUTPUT -- DMA interface
+      --f0
+      data_f0_addr_out             => data_f0_addr_out_s,
+      data_f0_data_out             => data_f0_data_out,
+      data_f0_data_out_valid       => data_f0_data_out_valid_s,
+      data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
+      data_f0_data_out_ren         => data_f0_data_out_ren,
+      --f1
+      data_f1_addr_out             => data_f1_addr_out_s,
+      data_f1_data_out             => data_f1_data_out,
+      data_f1_data_out_valid       => data_f1_data_out_valid_s,
+      data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
+      data_f1_data_out_ren         => data_f1_data_out_ren,
+      --f2
+      data_f2_addr_out             => data_f2_addr_out_s,
+      data_f2_data_out             => data_f2_data_out,
+      data_f2_data_out_valid       => data_f2_data_out_valid_s,
+      data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
+      data_f2_data_out_ren         => data_f2_data_out_ren,
+      --f3
+      data_f3_addr_out             => data_f3_addr_out_s,
+      data_f3_data_out             => data_f3_data_out,
+      data_f3_data_out_valid       => data_f3_data_out_valid_s,
+      data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
+      data_f3_data_out_ren         => data_f3_data_out_ren ,
+
+      -------------------------------------------------------------------------
+      observation_reg => OPEN 
+
+      );
+
+
+  -----------------------------------------------------------------------------
+  -- TEMP
+  -----------------------------------------------------------------------------
+
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      data_f0_data_out_valid       <= '0';
+      data_f0_data_out_valid_burst <= '0';
+      data_f1_data_out_valid       <= '0';
+      data_f1_data_out_valid_burst <= '0';
+      data_f2_data_out_valid       <= '0';
+      data_f2_data_out_valid_burst <= '0';
+      data_f3_data_out_valid       <= '0';
+      data_f3_data_out_valid_burst <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge        
+      data_f0_data_out_valid       <= data_f0_data_out_valid_s;
+      data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
+      data_f1_data_out_valid       <= data_f1_data_out_valid_s;
+      data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
+      data_f2_data_out_valid       <= data_f2_data_out_valid_s;
+      data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
+      data_f3_data_out_valid       <= data_f3_data_out_valid_s;
+      data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
+    END IF;
+  END PROCESS;
+
+  data_f0_addr_out <= data_f0_addr_out_s;
+  data_f1_addr_out <= data_f1_addr_out_s;
+  data_f2_addr_out <= data_f2_addr_out_s;
+  data_f3_addr_out <= data_f3_addr_out_s;
+
+  -----------------------------------------------------------------------------
+  -- RoundRobin Selection For DMA
+  -----------------------------------------------------------------------------
+
+  dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
+  dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
+  dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
+  dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
+
+  RR_Arbiter_4_1 : RR_Arbiter_4
+    PORT MAP (
+      clk       => clk,
+      rstn      => rstn,
+      in_valid  => dma_rr_valid,
+      out_grant => dma_rr_grant_s);
+
+  dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
+  dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
+  dma_rr_valid_ms(2) <= '0';
+  dma_rr_valid_ms(3) <= '0';
+
+  RR_Arbiter_4_2 : RR_Arbiter_4
+    PORT MAP (
+      clk       => clk,
+      rstn      => rstn,
+      in_valid  => dma_rr_valid_ms,
+      out_grant => dma_rr_grant_ms);
+
+  dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
+
+
+  -----------------------------------------------------------------------------
+  -- in  : dma_rr_grant
+  --       send
+  -- out : dma_sel
+  --       dma_valid_burst
+  --       dma_sel_valid
+  -----------------------------------------------------------------------------
+  PROCESS (clk, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                  -- asynchronous reset (active low)
+      dma_sel         <= (OTHERS => '0');
+      dma_send        <= '0';
+      dma_valid_burst <= '0';
+      data_ms_done    <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+      IF run = '1' THEN
+        data_ms_done <= '0';
+        IF dma_sel = "00000" OR dma_done = '1' THEN
+          dma_sel <= dma_rr_grant;
+          IF dma_rr_grant(0) = '1' THEN
+            dma_send        <= '1';
+            dma_valid_burst <= data_f0_data_out_valid_burst;
+            dma_sel_valid   <= data_f0_data_out_valid;
+          ELSIF dma_rr_grant(1) = '1' THEN
+            dma_send        <= '1';
+            dma_valid_burst <= data_f1_data_out_valid_burst;
+            dma_sel_valid   <= data_f1_data_out_valid;
+          ELSIF dma_rr_grant(2) = '1' THEN
+            dma_send        <= '1';
+            dma_valid_burst <= data_f2_data_out_valid_burst;
+            dma_sel_valid   <= data_f2_data_out_valid;
+          ELSIF dma_rr_grant(3) = '1' THEN
+            dma_send        <= '1';
+            dma_valid_burst <= data_f3_data_out_valid_burst;
+            dma_sel_valid   <= data_f3_data_out_valid;
+          ELSIF dma_rr_grant(4) = '1' THEN
+            dma_send        <= '1';
+            dma_valid_burst <= data_ms_valid_burst;
+            dma_sel_valid   <= data_ms_valid;
+          END IF;
+
+          IF dma_sel(4) = '1' THEN
+            data_ms_done <= '1';
+          END IF;
+        ELSE
+          dma_sel  <= dma_sel;
+          dma_send <= '0';
+        END IF;
+      ELSE
+        data_ms_done    <= '0';
+        dma_sel         <= (OTHERS => '0');
+        dma_send        <= '0';
+        dma_valid_burst <= '0';
+      END IF;
+    END IF;
+  END PROCESS;
+
+
+  dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
+                 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
+                 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
+                 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
+                 data_ms_addr;
+  
+  dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
+              data_f1_data_out WHEN dma_sel(1) = '1' ELSE
+              data_f2_data_out WHEN dma_sel(2) = '1' ELSE
+              data_f3_data_out WHEN dma_sel(3) = '1' ELSE
+              data_ms_data;
+  
+  data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
+  data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
+  data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
+  data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
+  data_ms_ren          <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
+
+  dma_data_2 <= dma_data;
+
+
+
+
+
+  -----------------------------------------------------------------------------
+  -- DEBUG -- DMA IN
+  --debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
+  --debug_f0_data_dma_in       <= dma_data;
+  --debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
+  --debug_f1_data_dma_in       <= dma_data;
+  --debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
+  --debug_f2_data_dma_in       <= dma_data;
+  --debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
+  --debug_f3_data_dma_in       <= dma_data;
+  -----------------------------------------------------------------------------
+
+  -----------------------------------------------------------------------------
+  -- DMA
+  -----------------------------------------------------------------------------
+  lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
+    GENERIC MAP (
+      tech   => inferred,
+      hindex => hindex)
+    PORT MAP (
+      HCLK           => clk,
+      HRESETn        => rstn,
+      run            => run,
+      AHB_Master_In  => ahbi,
+      AHB_Master_Out => ahbo,
+
+      send        => dma_send,
+      valid_burst => dma_valid_burst,
+      done        => dma_done,
+      ren         => dma_ren,
+      address     => dma_address,
+      data        => dma_data_2);       
+
+  -----------------------------------------------------------------------------
+  -- Matrix Spectral
+  -----------------------------------------------------------------------------
+  sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
+                   NOT(sample_f0_val) & NOT(sample_f0_val);
+  sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
+                   NOT(sample_f1_val) & NOT(sample_f1_val);
+  sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
+                   NOT(sample_f3_val) & NOT(sample_f3_val);
+
+  sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
+  sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
+  sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
+
+  -------------------------------------------------------------------------------
+
+  ms_softandhard_rstn <= rstn AND run_ms AND run;
+
+  -----------------------------------------------------------------------------
+  lpp_lfr_ms_1 : lpp_lfr_ms
+    GENERIC MAP (
+      Mem_use => Mem_use)
+    PORT MAP (
+      clk  => clk,
+      rstn => ms_softandhard_rstn,      --rstn,
+
+      coarse_time => coarse_time,
+      fine_time   => fine_time,
+
+      sample_f0_wen   => sample_f0_wen,
+      sample_f0_wdata => sample_f0_wdata,
+      sample_f1_wen   => sample_f1_wen,
+      sample_f1_wdata => sample_f1_wdata,
+      sample_f2_wen   => sample_f3_wen,  -- TODO verify that it's the good data
+      sample_f2_wdata => sample_f3_wdata,-- TODO verify that it's the good data
+
+      dma_addr        => data_ms_addr,         --
+      dma_data        => data_ms_data,         --
+      dma_valid       => data_ms_valid,        --
+      dma_valid_burst => data_ms_valid_burst,  --
+      dma_ren         => data_ms_ren,          --
+      dma_done        => data_ms_done,         --
+
+      ready_matrix_f0                        => ready_matrix_f0_0,-- TODO rename
+      ready_matrix_f1                        => ready_matrix_f1,
+      ready_matrix_f2                        => ready_matrix_f2,
+      --error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
+      error_bad_component_error              => error_bad_component_error,
+      error_buffer_full                      => error_buffer_full,      -- TODO
+      error_input_fifo_write                 => error_input_fifo_write, -- TODO
+      
+      debug_reg                              => observation_reg,
+      
+      status_ready_matrix_f0                 => status_ready_matrix_f0_0,-- TODO rename
+      status_ready_matrix_f1                 => status_ready_matrix_f1,
+      status_ready_matrix_f2                 => status_ready_matrix_f2,
+--      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,-- TODO
+--      status_error_bad_component_error       => status_error_bad_component_error,-- TODO
+      config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
+      config_active_interruption_onError     => config_active_interruption_onError,
+      addr_matrix_f0                         => addr_matrix_f0_0,-- TODO rename
+      addr_matrix_f1                         => addr_matrix_f1,
+      addr_matrix_f2                         => addr_matrix_f2,
+
+      matrix_time_f0                         => matrix_time_f0_0,-- TODO rename
+      matrix_time_f1                         => matrix_time_f1,
+      matrix_time_f2                         => matrix_time_f2);
+
+END beh;
\ No newline at end of file
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd
@@ -62,31 +62,30 @@ ENTITY lpp_lfr_apbreg IS
     run_ms                              : OUT STD_LOGIC;
     -- IN
     ready_matrix_f0_0                   : IN STD_LOGIC;
-    ready_matrix_f0_1                   : IN STD_LOGIC;
     ready_matrix_f1                     : IN STD_LOGIC;
     ready_matrix_f2                     : IN STD_LOGIC;
-    error_anticipating_empty_fifo       : IN STD_LOGIC;
+
     error_bad_component_error           : IN STD_LOGIC;
+    error_buffer_full                   : in STD_LOGIC;                         --  TODO
+    error_input_fifo_write              : in STD_LOGIC_VECTOR(2 DOWNTO 0);      --  TODO
+
     debug_reg                           : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
     -- OUT
     status_ready_matrix_f0_0             : OUT STD_LOGIC;
-    status_ready_matrix_f0_1             : OUT STD_LOGIC;
     status_ready_matrix_f1               : OUT STD_LOGIC;
     status_ready_matrix_f2               : OUT STD_LOGIC;
-    status_error_anticipating_empty_fifo : OUT STD_LOGIC;
-    status_error_bad_component_error     : OUT STD_LOGIC;
 
     config_active_interruption_onNewMatrix : OUT STD_LOGIC;
     config_active_interruption_onError     : OUT STD_LOGIC;
     
     addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-    addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+--    addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
     
     matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
-    matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+--    matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
     matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
     matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
     
@@ -158,18 +157,20 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS
     config_active_interruption_onError     : STD_LOGIC;
     config_ms_run                          : STD_LOGIC;
     status_ready_matrix_f0_0               : STD_LOGIC;
-    status_ready_matrix_f0_1               : STD_LOGIC;
+--    status_ready_matrix_f0_1               : STD_LOGIC;
     status_ready_matrix_f1                 : STD_LOGIC;
     status_ready_matrix_f2                 : STD_LOGIC;
-    status_error_anticipating_empty_fifo   : STD_LOGIC;
+--    status_error_anticipating_empty_fifo   : STD_LOGIC;
     status_error_bad_component_error       : STD_LOGIC;
+    status_error_buffer_full               : STD_LOGIC;                         --  TODO
+    status_error_input_fifo_write          : STD_LOGIC_VECTOR(2 DOWNTO 0);      --  TODO
     addr_matrix_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-    addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--    addr_matrix_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
     
     coarse_time_f0_0                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
-    coarse_time_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--    coarse_time_f0_1                       : STD_LOGIC_VECTOR(31 DOWNTO 0);
     coarse_time_f1                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
     coarse_time_f2                         : STD_LOGIC_VECTOR(31 DOWNTO 0);
     
@@ -228,16 +229,16 @@ ARCHITECTURE beh OF lpp_lfr_apbreg IS
 BEGIN  -- beh
 
   status_ready_matrix_f0_0             <= reg_sp.status_ready_matrix_f0_0;
-  status_ready_matrix_f0_1             <= reg_sp.status_ready_matrix_f0_1;
+--  status_ready_matrix_f0_1             <= reg_sp.status_ready_matrix_f0_1;
   status_ready_matrix_f1               <= reg_sp.status_ready_matrix_f1;
   status_ready_matrix_f2               <= reg_sp.status_ready_matrix_f2;
-  status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
-  status_error_bad_component_error     <= reg_sp.status_error_bad_component_error;
+--  status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
+--  status_error_bad_component_error     <= reg_sp.status_error_bad_component_error;
 
   config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
   config_active_interruption_onError     <= reg_sp.config_active_interruption_onError;
   addr_matrix_f0_0                       <= reg_sp.addr_matrix_f0_0;
-  addr_matrix_f0_1                       <= reg_sp.addr_matrix_f0_1;
+--  addr_matrix_f0_1                       <= reg_sp.addr_matrix_f0_1;
   addr_matrix_f1                         <= reg_sp.addr_matrix_f1;
   addr_matrix_f2                         <= reg_sp.addr_matrix_f2;
 
@@ -283,18 +284,21 @@ BEGIN  -- beh
       reg_sp.config_active_interruption_onError     <= '0';
       reg_sp.config_ms_run                          <= '1';
       reg_sp.status_ready_matrix_f0_0               <= '0';
-      reg_sp.status_ready_matrix_f0_1               <= '0';
+--      reg_sp.status_ready_matrix_f0_1               <= '0';
       reg_sp.status_ready_matrix_f1                 <= '0';
       reg_sp.status_ready_matrix_f2                 <= '0';
-      reg_sp.status_error_anticipating_empty_fifo   <= '0';
+--      reg_sp.status_error_anticipating_empty_fifo   <= '0';
       reg_sp.status_error_bad_component_error       <= '0';
+      reg_sp.status_error_buffer_full               <= '0';
+      reg_sp.status_error_input_fifo_write          <= (OTHERS => '0');
+      
       reg_sp.addr_matrix_f0_0                       <= (OTHERS => '0');
-      reg_sp.addr_matrix_f0_1                       <= (OTHERS => '0');
+--      reg_sp.addr_matrix_f0_1                       <= (OTHERS => '0');
       reg_sp.addr_matrix_f1                         <= (OTHERS => '0');
       reg_sp.addr_matrix_f2                         <= (OTHERS => '0');
       
       reg_sp.coarse_time_f0_0                       <= (OTHERS => '0');
-      reg_sp.coarse_time_f0_1                       <= (OTHERS => '0');
+--      reg_sp.coarse_time_f0_1                       <= (OTHERS => '0');
       reg_sp.coarse_time_f1                         <= (OTHERS => '0');
       reg_sp.coarse_time_f2                         <= (OTHERS => '0');
       --reg_sp.fine_time_f0_0                         <= (OTHERS => '0');
@@ -340,7 +344,7 @@ BEGIN  -- beh
     ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
       
       reg_sp.coarse_time_f0_0                       <= matrix_time_f0_0(31 DOWNTO 0);
-      reg_sp.coarse_time_f0_1                       <= matrix_time_f0_1(31 DOWNTO 0);
+--      reg_sp.coarse_time_f0_1                       <= matrix_time_f0_1(31 DOWNTO 0);
       reg_sp.coarse_time_f1                         <= matrix_time_f1  (31 DOWNTO 0);
       reg_sp.coarse_time_f2                         <= matrix_time_f2  (31 DOWNTO 0);
     
@@ -352,12 +356,20 @@ BEGIN  -- beh
       status_full_ack <= (OTHERS => '0');
 
       reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
-      reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
+--      reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
       reg_sp.status_ready_matrix_f1   <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
       reg_sp.status_ready_matrix_f2   <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
 
-      reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
+--      reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
       reg_sp.status_error_bad_component_error     <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
+      
+      reg_sp.status_error_buffer_full    <= reg_sp.status_error_buffer_full OR error_buffer_full;
+      reg_sp.status_error_input_fifo_write(0)    <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
+      reg_sp.status_error_input_fifo_write(1)    <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
+      reg_sp.status_error_input_fifo_write(2)    <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
+
+
+      
       all_status: FOR I IN 3 DOWNTO 0 LOOP
         --reg_wp.status_full(I)     <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
         --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I))  AND reg_wp.run;
@@ -378,22 +390,26 @@ BEGIN  -- beh
                            prdata(1) <= reg_sp.config_active_interruption_onError;
                            prdata(2) <= reg_sp.config_ms_run;
           WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
-                           prdata(1) <= reg_sp.status_ready_matrix_f0_1;
+--                           prdata(1) <= reg_sp.status_ready_matrix_f0_1;
                            prdata(2) <= reg_sp.status_ready_matrix_f1;
                            prdata(3) <= reg_sp.status_ready_matrix_f2;
-                           prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
+--                           prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
                            prdata(5) <= reg_sp.status_error_bad_component_error;
+                           prdata(6) <= reg_sp.status_error_buffer_full;            
+                           prdata(7) <= reg_sp.status_error_input_fifo_write(0);    
+                           prdata(8) <= reg_sp.status_error_input_fifo_write(1);    
+                           prdata(9) <= reg_sp.status_error_input_fifo_write(2);    
           WHEN "000010" => prdata    <= reg_sp.addr_matrix_f0_0;
-          WHEN "000011" => prdata    <= reg_sp.addr_matrix_f0_1;
+--          WHEN "000011" => prdata    <= reg_sp.addr_matrix_f0_1;
           WHEN "000100" => prdata    <= reg_sp.addr_matrix_f1;
           WHEN "000101" => prdata    <= reg_sp.addr_matrix_f2;
       
           WHEN "000110" => prdata    <= reg_sp.coarse_time_f0_0;
-          WHEN "000111" => prdata    <= reg_sp.coarse_time_f0_1;
+--          WHEN "000111" => prdata    <= reg_sp.coarse_time_f0_1;
           WHEN "001000" => prdata    <= reg_sp.coarse_time_f1;  
           WHEN "001001" => prdata    <= reg_sp.coarse_time_f2;  
           WHEN "001010" => prdata(15 downto 0) <= matrix_time_f0_0(15 DOWNTO 0);--reg_sp.fine_time_f0_0;  
-          WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;  
+--          WHEN "001011" => prdata(15 downto 0) <= matrix_time_f0_1(15 DOWNTO 0);--reg_sp.fine_time_f0_1;  
           WHEN "001100" => prdata(15 downto 0) <= matrix_time_f1  (15 DOWNTO 0);--reg_sp.fine_time_f1;    
           WHEN "001101" => prdata(15 downto 0) <= matrix_time_f2  (15 DOWNTO 0);--reg_sp.fine_time_f2;
                            
@@ -450,13 +466,17 @@ BEGIN  -- beh
                              reg_sp.config_active_interruption_onError     <= apbi.pwdata(1);
                              reg_sp.config_ms_run                          <= apbi.pwdata(2);
             WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
-                             reg_sp.status_ready_matrix_f0_1             <= apbi.pwdata(1);
+--                             reg_sp.status_ready_matrix_f0_1             <= apbi.pwdata(1);
                              reg_sp.status_ready_matrix_f1               <= apbi.pwdata(2);
                              reg_sp.status_ready_matrix_f2               <= apbi.pwdata(3);
-                             reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
+--                             reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
                              reg_sp.status_error_bad_component_error     <= apbi.pwdata(5);
+                           reg_sp.status_error_buffer_full              <= apbi.pwdata(6);            
+                           reg_sp.status_error_input_fifo_write(0)      <= apbi.pwdata(7);    
+                           reg_sp.status_error_input_fifo_write(1)      <= apbi.pwdata(8);    
+                           reg_sp.status_error_input_fifo_write(2)      <= apbi.pwdata(9);    
             WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
-            WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
+--            WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
             WHEN "000100" => reg_sp.addr_matrix_f1   <= apbi.pwdata;
             WHEN "000101" => reg_sp.addr_matrix_f2   <= apbi.pwdata;
                              --
@@ -500,13 +520,18 @@ BEGIN  -- beh
       END IF;
 
       apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
-                                                                                 ready_matrix_f0_1 OR
+--                                                                                 ready_matrix_f0_1 OR
                                                                                  ready_matrix_f1 OR
                                                                                  ready_matrix_f2)
                              )
                             OR
-                            (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
-                                                                            error_bad_component_error)
+                            (reg_sp.config_active_interruption_onError AND (
+                              --error_anticipating_empty_fifo OR
+                                                                            error_bad_component_error
+                                                                            OR error_buffer_full
+                                                                            OR error_input_fifo_write(0)
+                                                                            OR error_input_fifo_write(1)
+                                                                            OR error_input_fifo_write(2))
                              ));
       
       apbo.pirq(pirq_wfp) <= ored_irq_wfp;
@@ -541,4 +566,4 @@ BEGIN  -- beh
 
   run_ms <= reg_sp.config_ms_run;
   
-END beh;
\ No newline at end of file
+END beh;
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd
@@ -49,37 +49,29 @@ ENTITY lpp_lfr_ms IS
     dma_done        : IN  STD_LOGIC;
 
     -- Reg out
-    ready_matrix_f0               : OUT STD_LOGIC;
---    ready_matrix_f0             : OUT STD_LOGIC;
-    ready_matrix_f1               : OUT STD_LOGIC;
-    ready_matrix_f2               : OUT STD_LOGIC;
-    --error_anticipating_empty_fifo : OUT STD_LOGIC;
-    error_bad_component_error     : OUT STD_LOGIC;
-    error_buffer_full             : OUT STD_LOGIC;
-    error_input_fifo_write        : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
-    
-    debug_reg                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    ready_matrix_f0           : OUT STD_LOGIC;
+    ready_matrix_f1           : OUT STD_LOGIC;
+    ready_matrix_f2           : OUT STD_LOGIC;
+    error_bad_component_error : OUT STD_LOGIC;
+    error_buffer_full         : OUT STD_LOGIC;
+    error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+
+    debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 
     -- Reg In
-    status_ready_matrix_f0             : IN STD_LOGIC;
---    status_ready_matrix_f0_1             : IN STD_LOGIC;
-    status_ready_matrix_f1               : IN STD_LOGIC;
-    status_ready_matrix_f2               : IN STD_LOGIC;
---    status_error_anticipating_empty_fifo : IN STD_LOGIC;
---    status_error_bad_component_error     : IN STD_LOGIC;
---    status_error_buffer_full             : IN STD_LOGIC;
+    status_ready_matrix_f0 : IN STD_LOGIC;
+    status_ready_matrix_f1 : IN STD_LOGIC;
+    status_ready_matrix_f2 : IN STD_LOGIC;
 
     config_active_interruption_onNewMatrix : IN STD_LOGIC;
     config_active_interruption_onError     : IN STD_LOGIC;
---    addr_matrix_f0_0                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
     matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
---    matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
-    matrix_time_f1   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
-    matrix_time_f2   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+    matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
+    matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
 
     );
 END;
@@ -148,87 +140,67 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   -----------------------------------------------------------------------------
   -- FFT
   -----------------------------------------------------------------------------
-  SIGNAL fft_read            : STD_LOGIC;
-  SIGNAL fft_pong            : STD_LOGIC;
-  SIGNAL fft_data_im         : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  SIGNAL fft_data_re         : STD_LOGIC_VECTOR(15 DOWNTO 0);
-  SIGNAL fft_data_valid      : STD_LOGIC;
-  SIGNAL fft_ready           : STD_LOGIC;
+  SIGNAL fft_read                 : STD_LOGIC;
+  SIGNAL fft_pong                 : STD_LOGIC;
+  SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  SIGNAL fft_data_valid           : STD_LOGIC;
+  SIGNAL fft_ready                : STD_LOGIC;
   -----------------------------------------------------------------------------
 --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
   -----------------------------------------------------------------------------
   TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
   SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
-  SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL current_fifo_empty : STD_LOGIC;
-  SIGNAL current_fifo_locked : STD_LOGIC;
-  SIGNAL current_fifo_full : STD_LOGIC;
-  SIGNAL MEM_IN_SM_locked      : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  
+  SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL current_fifo_empty       : STD_LOGIC;
+  SIGNAL current_fifo_locked      : STD_LOGIC;
+  SIGNAL current_fifo_full        : STD_LOGIC;
+  SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
+
   -----------------------------------------------------------------------------
-  SIGNAL MEM_IN_SM_ReUse     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL MEM_IN_SM_wen     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL MEM_IN_SM_wen_s     : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL MEM_IN_SM_ren      : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL MEM_IN_SM_wData      : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
-  SIGNAL MEM_IN_SM_rData  : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
-  SIGNAL MEM_IN_SM_Full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL MEM_IN_SM_Empty      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
+  SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
+  SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
   -----------------------------------------------------------------------------
-  SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
-  SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
-  SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
+  SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
 
-  SIGNAL SM_correlation_start : STD_LOGIC;
-  SIGNAL SM_correlation_auto : STD_LOGIC;
-  SIGNAL SM_correlation_done : STD_LOGIC;
+  SIGNAL SM_correlation_start     : STD_LOGIC;
+  SIGNAL SM_correlation_auto      : STD_LOGIC;
+  SIGNAL SM_correlation_done      : STD_LOGIC;
   SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
   SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
   SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
-  SIGNAL SM_correlation_begin : STD_LOGIC;
-  
---  SIGNAL temp_ongoing : STD_LOGIC;
---  SIGNAL temp_auto : STD_LOGIC;
+  SIGNAL SM_correlation_begin     : STD_LOGIC;
 
-  SIGNAL MEM_OUT_SM_Full_s     : STD_LOGIC;
-  SIGNAL MEM_OUT_SM_Data_in_s  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  SIGNAL MEM_OUT_SM_Write_s    : STD_LOGIC;
+  SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
+  SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
 
-  SIGNAL   current_matrix_write       : STD_LOGIC;
-  SIGNAL   current_matrix_wait_empty  : STD_LOGIC;
-
-  --SIGNAL MEM_OUT_SM_BURST_available : STD_LOGIC_VECTOR(1 DOWNTO 0);
-
+  SIGNAL current_matrix_write      : STD_LOGIC;
+  SIGNAL current_matrix_wait_empty : STD_LOGIC;
   -----------------------------------------------------------------------------
-  SIGNAL   fifo_0_ready : STD_LOGIC;
-  SIGNAL   fifo_1_ready : STD_LOGIC;
-  SIGNAL   fifo_ongoing : STD_LOGIC;
+  SIGNAL fifo_0_ready              : STD_LOGIC;
+  SIGNAL fifo_1_ready              : STD_LOGIC;
+  SIGNAL fifo_ongoing              : STD_LOGIC;
 
-  SIGNAL FSM_DMA_fifo_ren  : STD_LOGIC;
-  SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
-  SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
+  SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
+  SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
   SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
-  
   -----------------------------------------------------------------------------
---  SIGNAL HEAD_SM_Param       : STD_LOGIC_VECTOR(3 DOWNTO 0);
-  --SIGNAL HEAD_WorkFreq       : STD_LOGIC_VECTOR(1 DOWNTO 0);
-  --SIGNAL HEAD_SM_Wen         : STD_LOGIC;
-  --SIGNAL HEAD_Valid          : STD_LOGIC;
-  --SIGNAL HEAD_Data           : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  --SIGNAL HEAD_Empty          : STD_LOGIC;
-  --SIGNAL HEAD_Read           : STD_LOGIC;
-  -----------------------------------------------------------------------------
---  SIGNAL MEM_OUT_SM_ReUse    : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
   SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
-  -----------------------------------------------------------------------------
-  --SIGNAL DMA_Header          : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  --SIGNAL DMA_Header_Val      : STD_LOGIC;
-  --SIGNAL DMA_Header_Ack      : STD_LOGIC;
 
   -----------------------------------------------------------------------------
   -- TIME REG & INFOs
@@ -248,23 +220,19 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms IS
   SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
   SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
   SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
-  
-  SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
-  SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
---  SIGNAL status_component_fifo_0_new : STD_LOGIC;
---  SIGNAL status_component_fifo_1_new : STD_LOGIC;
+
+  SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+  SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 0);
   SIGNAL status_component_fifo_0_end : STD_LOGIC;
   SIGNAL status_component_fifo_1_end : STD_LOGIC;
-  
-  SIGNAL dma_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
   -----------------------------------------------------------------------------
 
 BEGIN
 
   
-  error_input_fifo_write <=  error_wen_f2 & error_wen_f1 & error_wen_f0;
+  error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
 
-  
+
   switch_f0_inst : spectral_matrix_switch_f0
     PORT MAP (
       clk  => clk,
@@ -287,67 +255,67 @@ BEGIN
   -----------------------------------------------------------------------------
   lppFIFOxN_f0_a : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 16,
-      Addr_sz      => 8,
-      FifoCnt      => 5)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 16,
+      Addr_sz => 8,
+      FifoCnt => 5)
     PORT MAP (
-      clk   => clk,
-      rstn  => rstn,
-      
+      clk  => clk,
+      rstn => rstn,
+
       ReUse => (OTHERS => '0'),
 
-      wen         => sample_f0_A_wen,   
-      wdata       => sample_f0_wdata,   
-      
-      ren         => sample_f0_A_ren,   
-      rdata       => sample_f0_A_rdata, 
-      
-      empty       => sample_f0_A_empty, 
-      full        => sample_f0_A_full,  
+      wen   => sample_f0_A_wen,
+      wdata => sample_f0_wdata,
+
+      ren   => sample_f0_A_ren,
+      rdata => sample_f0_A_rdata,
+
+      empty       => sample_f0_A_empty,
+      full        => sample_f0_A_full,
       almost_full => OPEN);             
 
   lppFIFOxN_f0_b : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 16,
-      Addr_sz      => 8,
-      FifoCnt      => 5)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 16,
+      Addr_sz => 8,
+      FifoCnt => 5)
     PORT MAP (
-      clk   => clk,
-      rstn  => rstn,
-      
+      clk  => clk,
+      rstn => rstn,
+
       ReUse => (OTHERS => '0'),
 
-      wen         => sample_f0_B_wen,   
-      wdata       => sample_f0_wdata,   
-      ren         => sample_f0_B_ren,   
-      rdata       => sample_f0_B_rdata, 
-      empty       => sample_f0_B_empty, 
-      full        => sample_f0_B_full,  
+      wen         => sample_f0_B_wen,
+      wdata       => sample_f0_wdata,
+      ren         => sample_f0_B_ren,
+      rdata       => sample_f0_B_rdata,
+      empty       => sample_f0_B_empty,
+      full        => sample_f0_B_full,
       almost_full => OPEN);             
 
   lppFIFOxN_f1 : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 16,
-      Addr_sz      => 8,
-      FifoCnt      => 5)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 16,
+      Addr_sz => 8,
+      FifoCnt => 5)
     PORT MAP (
-      clk   => clk,
-      rstn  => rstn,
-      
+      clk  => clk,
+      rstn => rstn,
+
       ReUse => (OTHERS => '0'),
 
-      wen         => sample_f1_wen,          
-      wdata       => sample_f1_wdata,        
-      ren         => sample_f1_ren,          
-      rdata       => sample_f1_rdata,        
-      empty       => sample_f1_empty,        
-      full        => sample_f1_full,         
+      wen         => sample_f1_wen,
+      wdata       => sample_f1_wdata,
+      ren         => sample_f1_ren,
+      rdata       => sample_f1_rdata,
+      empty       => sample_f1_empty,
+      full        => sample_f1_full,
       almost_full => sample_f1_almost_full); 
 
 
@@ -371,23 +339,23 @@ BEGIN
 
   lppFIFOxN_f2 : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 16,
-      Addr_sz      => 8,
-      FifoCnt      => 5)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 16,
+      Addr_sz => 8,
+      FifoCnt => 5)
     PORT MAP (
-      clk   => clk,
-      rstn  => rstn,
-      
+      clk  => clk,
+      rstn => rstn,
+
       ReUse => (OTHERS => '0'),
 
-      wen         => sample_f2_wen,     
-      wdata       => sample_f2_wdata,   
-      ren         => sample_f2_ren,     
-      rdata       => sample_f2_rdata,   
-      empty       => sample_f2_empty,   
-      full        => sample_f2_full,    
+      wen         => sample_f2_wen,
+      wdata       => sample_f2_wdata,
+      ren         => sample_f2_ren,
+      rdata       => sample_f2_rdata,
+      empty       => sample_f2_empty,
+      full        => sample_f2_full,
       almost_full => OPEN);             
 
 
@@ -505,7 +473,7 @@ BEGIN
     IF rstn = '0' THEN
       sample_ren_s       <= (OTHERS => '1');
       state_fsm_load_FFT <= IDLE;
-      status_MS_input <= (OTHERS => '0');
+      status_MS_input    <= (OTHERS => '0');
       --next_state_fsm_load_FFT <= IDLE;
       --sample_valid              <= '0';
     ELSIF clk'EVENT AND clk = '1' THEN
@@ -515,7 +483,7 @@ BEGIN
           sample_ren_s <= (OTHERS => '1');
           IF sample_full = "11111" AND sample_load = '1' THEN
             state_fsm_load_FFT <= FIFO_1;
-            status_MS_input <= status_channel;
+            status_MS_input    <= status_channel;
           END IF;
           
         WHEN FIFO_1 =>
@@ -583,7 +551,7 @@ BEGIN
   -----------------------------------------------------------------------------
   -- FFT
   -----------------------------------------------------------------------------
-  lpp_lfr_ms_FFT_1: lpp_lfr_ms_FFT
+  lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
     PORT MAP (
       clk            => clk,
       rstn           => rstn,
@@ -598,16 +566,12 @@ BEGIN
       fft_ready      => fft_ready);
 
   -----------------------------------------------------------------------------
-  -- in   fft_data_im & fft_data_re
-  -- in   fft_data_valid
-  -- in   fft_ready
-  -- out  fft_read
   PROCESS (clk, rstn)
   BEGIN
     IF rstn = '0' THEN
       state_fsm_load_MS_memory <= IDLE;
-      current_fifo_load <= "00001";
-    ELSIF clk'event AND clk = '1' THEN
+      current_fifo_load        <= "00001";
+    ELSIF clk'EVENT AND clk = '1' THEN
       CASE state_fsm_load_MS_memory IS
         WHEN IDLE =>
           IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
@@ -620,38 +584,38 @@ BEGIN
         WHEN TRASH_FFT =>
           IF fft_ready = '0' THEN
             state_fsm_load_MS_memory <= IDLE;
-            current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
-          END IF;          
+            current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
+          END IF;
         WHEN OTHERS => NULL;
       END CASE;
       
     END IF;
   END PROCESS;
-  
+
   current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                         MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                         MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                         MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
-                        MEM_IN_SM_Empty(4);-- WHEN current_fifo_load(3) = '1' ELSE
-                        
-  current_fifo_full  <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
-                        MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
-                        MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
-                        MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
-                        MEM_IN_SM_Full(4);-- WHEN current_fifo_load(3) = '1' ELSE
-                        
+                        MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
+  
+  current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
+                       MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
+                       MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
+                       MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
+                       MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
+  
   current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                          MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                          MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                          MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
-                         MEM_IN_SM_locked(4);-- WHEN current_fifo_load(3) = '1' ELSE
-                        
+                         MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
+  
   fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
 
-  all_fifo: FOR I IN 4 DOWNTO 0 GENERATE
-      MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
-                                   AND state_fsm_load_MS_memory = LOAD_FIFO
-                                   AND current_fifo_load(I) = '1'
+  all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
+    MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
+                          AND state_fsm_load_MS_memory = LOAD_FIFO
+                          AND current_fifo_load(I) = '1'
                           ELSE '1';
   END GENERATE all_fifo;
 
@@ -659,101 +623,58 @@ BEGIN
   BEGIN
     IF rstn = '0' THEN
       MEM_IN_SM_wen <= (OTHERS => '1');
-    ELSIF clk'event AND clk = '1' THEN
-      MEM_IN_SM_wen <= MEM_IN_SM_wen_s;      
+    ELSIF clk'EVENT AND clk = '1' THEN
+      MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
     END IF;
   END PROCESS;
-  
+
   MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                      (fft_data_im & fft_data_re) &
                      (fft_data_im & fft_data_re) &
                      (fft_data_im & fft_data_re) &
                      (fft_data_im & fft_data_re);
-  
 
-  -- out SM_MEM_IN_wData
-  -- out SM_MEM_IN_wen
-  -- out SM_MEM_IN_Full
-  
-  -- out SM_MEM_IN_locked
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  --Linker_FFT_1 : Linker_FFT
-  --  GENERIC MAP (
-  --    Data_sz => 16,
-  --    NbData  => 256)
-  --  PORT MAP (
-  --    clk  => clk,
-  --    rstn => rstn,
-
-  --    Ready => fft_ready,
-  --    Valid => fft_data_valid,
-
-  --    Full => MEM_IN_SM_Full,
-
-  --    Data_re => fft_data_re,
-  --    Data_im => fft_data_im,
-  --    Read    => fft_read,
-
-  --    Write => MEM_IN_SM_wen,
-  --    ReUse => fft_linker_ReUse,
-  --    DATA  => MEM_IN_SM_wData);
-  
   -----------------------------------------------------------------------------
   Mem_In_SpectralMatrix : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 32,               --16,
-      Addr_sz      => 7,                --8
-      FifoCnt      => 5)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 32,                    --16,
+      Addr_sz => 7,                     --8
+      FifoCnt => 5)
     PORT MAP (
-      clk => clk,
+      clk  => clk,
       rstn => rstn,
 
       ReUse => MEM_IN_SM_ReUse,
-      
+
       wen   => MEM_IN_SM_wen,
       wdata => MEM_IN_SM_wData,
-      
-      ren   => MEM_IN_SM_ren,
-      rdata => MEM_IN_SM_rData,
-      full  => MEM_IN_SM_Full,
-      empty => MEM_IN_SM_Empty,    
+
+      ren         => MEM_IN_SM_ren,
+      rdata       => MEM_IN_SM_rData,
+      full        => MEM_IN_SM_Full,
+      empty       => MEM_IN_SM_Empty,
       almost_full => OPEN);
 
-
-  --all_lock: FOR I IN 4 DOWNTO 0 GENERATE
-  --  PROCESS (clk, rstn)
-  --  BEGIN
-  --    IF rstn = '0' THEN
-  --      MEM_IN_SM_locked(I) <= '0';
-  --    ELSIF clk'event AND clk = '1' THEN 
-  --      MEM_IN_SM_locked(I) <=   MEM_IN_SM_Full(I) OR  MEM_IN_SM_locked(I);  -- TODO
-  --    END IF;
-  --  END PROCESS;    
-  --END GENERATE all_lock;
-  
   -----------------------------------------------------------------------------
-  MS_control_1: MS_control
+  MS_control_1 : MS_control
     PORT MAP (
-      clk               => clk,
-      rstn              => rstn,
+      clk  => clk,
+      rstn => rstn,
 
       current_status_ms => status_MS_input,
-      
-      fifo_in_lock      => MEM_IN_SM_locked,
-      fifo_in_data      => MEM_IN_SM_rdata,
-      fifo_in_full      => MEM_IN_SM_Full,
-      fifo_in_empty     => MEM_IN_SM_Empty,
-      fifo_in_ren       => MEM_IN_SM_ren,
-      fifo_in_reuse     => MEM_IN_SM_ReUse,
-      
-      fifo_out_data     => SM_in_data,
-      fifo_out_ren      => SM_in_ren,
-      fifo_out_empty    => SM_in_empty,
+
+      fifo_in_lock  => MEM_IN_SM_locked,
+      fifo_in_data  => MEM_IN_SM_rdata,
+      fifo_in_full  => MEM_IN_SM_Full,
+      fifo_in_empty => MEM_IN_SM_Empty,
+      fifo_in_ren   => MEM_IN_SM_ren,
+      fifo_in_reuse => MEM_IN_SM_ReUse,
+
+      fifo_out_data  => SM_in_data,
+      fifo_out_ren   => SM_in_ren,
+      fifo_out_empty => SM_in_empty,
 
       current_status_component => status_component,
 
@@ -762,72 +683,62 @@ BEGIN
       correlation_done  => SM_correlation_done);
 
 
-  MS_calculation_1: MS_calculation
+  MS_calculation_1 : MS_calculation
     PORT MAP (
-      clk               => clk,
-      rstn              => rstn,
-      
-      fifo_in_data      => SM_in_data,
-      fifo_in_ren       => SM_in_ren,
-      fifo_in_empty     => SM_in_empty,
-      
-      fifo_out_data     => MEM_OUT_SM_Data_in_s,  --    TODO
-      fifo_out_wen      => MEM_OUT_SM_Write_s,  --      TODO
-      fifo_out_full     => MEM_OUT_SM_Full_s,  --       TODO
-      
+      clk  => clk,
+      rstn => rstn,
+
+      fifo_in_data  => SM_in_data,
+      fifo_in_ren   => SM_in_ren,
+      fifo_in_empty => SM_in_empty,
+
+      fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
+      fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
+      fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
+
       correlation_start => SM_correlation_start,
       correlation_auto  => SM_correlation_auto,
       correlation_begin => SM_correlation_begin,
       correlation_done  => SM_correlation_done);
-  
+
   -----------------------------------------------------------------------------
   PROCESS (clk, rstn)
   BEGIN  -- PROCESS
     IF rstn = '0' THEN                  -- asynchronous reset (active low)
-      current_matrix_write      <= '0';
-      current_matrix_wait_empty <= '1';
-      status_component_fifo_0 <= (OTHERS => '0');
-      status_component_fifo_1 <= (OTHERS => '0');
---    status_component_fifo_0_new <= '0';
---    status_component_fifo_1_new <= '0';
+      current_matrix_write        <= '0';
+      current_matrix_wait_empty   <= '1';
+      status_component_fifo_0     <= (OTHERS => '0');
+      status_component_fifo_1     <= (OTHERS => '0');
       status_component_fifo_0_end <= '0';
       status_component_fifo_1_end <= '0';
-      SM_correlation_done_reg1 <= '0';
-      SM_correlation_done_reg2 <= '0';
-      SM_correlation_done_reg3 <= '0';
+      SM_correlation_done_reg1    <= '0';
+      SM_correlation_done_reg2    <= '0';
+      SM_correlation_done_reg3    <= '0';
       
-    ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
-      SM_correlation_done_reg1 <= SM_correlation_done;
-      SM_correlation_done_reg2 <= SM_correlation_done_reg1;
-      SM_correlation_done_reg3 <= SM_correlation_done_reg2;
-      
---      status_component_fifo_0_new <= '0';
---      status_component_fifo_1_new <= '0';
+    ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+      SM_correlation_done_reg1    <= SM_correlation_done;
+      SM_correlation_done_reg2    <= SM_correlation_done_reg1;
+      SM_correlation_done_reg3    <= SM_correlation_done_reg2;
       status_component_fifo_0_end <= '0';
       status_component_fifo_1_end <= '0';
-
-
-      
       IF SM_correlation_begin = '1' THEN
         IF current_matrix_write = '0' THEN
---          status_component_fifo_0_new   <= '1';
-          status_component_fifo_0       <= status_component;
+          status_component_fifo_0 <= status_component;
         ELSE
---          status_component_fifo_1_new   <= '1';
-          status_component_fifo_1       <= status_component;
+          status_component_fifo_1 <= status_component;
         END IF;
       END IF;
-      
+
       IF SM_correlation_done_reg3 = '1' THEN
         IF current_matrix_write = '0' THEN
-          status_component_fifo_0_end   <= '1';
+          status_component_fifo_0_end <= '1';
         ELSE
-          status_component_fifo_1_end   <= '1';
+          status_component_fifo_1_end <= '1';
         END IF;
         current_matrix_wait_empty <= '1';
         current_matrix_write      <= NOT current_matrix_write;
       END IF;
-      
+
       IF current_matrix_wait_empty <= '1' THEN
         IF current_matrix_write = '0' THEN
           current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
@@ -839,69 +750,69 @@ BEGIN
     END IF;
   END PROCESS;
 
-  MEM_OUT_SM_Full_s <= '1'                WHEN SM_correlation_done      = '1' ELSE
-                       '1'                WHEN SM_correlation_done_reg1 = '1' ELSE
-                       '1'                WHEN SM_correlation_done_reg2 = '1' ELSE
-                       '1'                WHEN SM_correlation_done_reg3 = '1' ELSE
+  MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
+                       '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
+                       '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
+                       '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                        '1'                WHEN current_matrix_wait_empty = '1' ELSE
-                       MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
+                       MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                        MEM_OUT_SM_Full(1);
 
   MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
   MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
 
-  MEM_OUT_SM_Data_in  <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
+  MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
   -----------------------------------------------------------------------------
-  
+
   Mem_Out_SpectralMatrix : lppFIFOxN
     GENERIC MAP (
-      tech         => 0,
-      Mem_use      => Mem_use,
-      Data_sz      => 32,
-      Addr_sz      => 8,
-      FifoCnt      => 2)
+      tech    => 0,
+      Mem_use => Mem_use,
+      Data_sz => 32,
+      Addr_sz => 8,
+      FifoCnt => 2)
     PORT MAP (
-      clk => clk,
+      clk  => clk,
       rstn => rstn,
 
       ReUse => (OTHERS => '0'),
 
       wen   => MEM_OUT_SM_Write,
       wdata => MEM_OUT_SM_Data_in,
-      
+
       ren   => MEM_OUT_SM_Read,
       rdata => MEM_OUT_SM_Data_out,
 
-      full  => MEM_OUT_SM_Full,
-      empty => MEM_OUT_SM_Empty,
+      full        => MEM_OUT_SM_Full,
+      empty       => MEM_OUT_SM_Empty,
       almost_full => OPEN);
-  
+
   -----------------------------------------------------------------------------
 --  MEM_OUT_SM_Read <= "00";
   PROCESS (clk, rstn)
-  BEGIN 
-    IF rstn = '0' THEN 
+  BEGIN
+    IF rstn = '0' THEN
       fifo_0_ready <= '0';
       fifo_1_ready <= '0';
       fifo_ongoing <= '0';
-    ELSIF clk'event AND clk = '1' THEN
+    ELSIF clk'EVENT AND clk = '1' THEN
       IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
-        fifo_ongoing <= '1'; 
+        fifo_ongoing <= '1';
         fifo_0_ready <= '0';
       ELSIF status_component_fifo_0_end = '1' THEN
-        fifo_0_ready <= '1';        
+        fifo_0_ready <= '1';
       END IF;
-      
+
       IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
         fifo_ongoing <= '0';
         fifo_1_ready <= '0';
       ELSIF status_component_fifo_1_end = '1' THEN
-        fifo_1_ready <= '1';        
+        fifo_1_ready <= '1';
       END IF;
       
     END IF;
   END PROCESS;
-  
+
   MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                         '1' WHEN fifo_0_ready = '0' ELSE
                         FSM_DMA_fifo_ren;
@@ -910,15 +821,15 @@ BEGIN
                         '1' WHEN fifo_1_ready = '0' ELSE
                         FSM_DMA_fifo_ren;
 
-  FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0)    WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
-                        MEM_OUT_SM_Empty(1)    WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
+  FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
+                        MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                         '1';
   
-  FSM_DMA_fifo_status <=  status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
-                          status_component_fifo_1;
+  FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
+                         status_component_fifo_1;
 
-  FSM_DMA_fifo_data   <= MEM_OUT_SM_Data_out(31 DOWNTO  0) WHEN fifo_ongoing = '0' ELSE
-                         MEM_OUT_SM_Data_out(63 DOWNTO 32);
+  FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
+                       MEM_OUT_SM_Data_out(63 DOWNTO 32);
 
   -----------------------------------------------------------------------------
   lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
@@ -926,23 +837,12 @@ BEGIN
       HCLK    => clk,
       HRESETn => rstn,
 
-      fifo_matrix_type      => FSM_DMA_fifo_status( 5 DOWNTO 4),
-      fifo_matrix_component => FSM_DMA_fifo_status( 3 DOWNTO 0),
+      fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
+      fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
       fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
       fifo_data             => FSM_DMA_fifo_data,
       fifo_empty            => FSM_DMA_fifo_empty,
       fifo_ren              => FSM_DMA_fifo_ren,
-      
-      ---- FIFO IN
-      --data_time => dma_time,           
-
-      --fifo_data  => HEAD_Data,
-      --fifo_empty => HEAD_Empty,
-      --fifo_ren   => HEAD_Read,
-
-      --header     => DMA_Header,
-      --header_val => DMA_Header_Val,
-      --header_ack => DMA_Header_Ack,
 
       dma_addr        => dma_addr,
       dma_data        => dma_data,
@@ -951,32 +851,28 @@ BEGIN
       dma_ren         => dma_ren,
       dma_done        => dma_done,
 
-      ready_matrix_f0                      => ready_matrix_f0,
---      ready_matrix_f0_1                      => ready_matrix_f0_1,
-      ready_matrix_f1                        => ready_matrix_f1,
-      ready_matrix_f2                        => ready_matrix_f2,
---      error_anticipating_empty_fifo          => error_anticipating_empty_fifo,
-      error_bad_component_error              => error_bad_component_error,
-      error_buffer_full                      => error_buffer_full,
-      debug_reg                              => debug_reg,
-      status_ready_matrix_f0               => status_ready_matrix_f0,
---      status_ready_matrix_f0_1               => status_ready_matrix_f0_1,
-      status_ready_matrix_f1                 => status_ready_matrix_f1,
-      status_ready_matrix_f2                 => status_ready_matrix_f2,
---      status_error_anticipating_empty_fifo   => status_error_anticipating_empty_fifo,
---      status_error_bad_component_error       => status_error_bad_component_error,
---      status_error_buffer_full               => status_error_buffer_full,
+      ready_matrix_f0 => ready_matrix_f0,
+      ready_matrix_f1 => ready_matrix_f1,
+      ready_matrix_f2 => ready_matrix_f2,
+
+      error_bad_component_error => error_bad_component_error,
+      error_buffer_full         => error_buffer_full,
+
+      debug_reg              => debug_reg,
+      status_ready_matrix_f0 => status_ready_matrix_f0,
+      status_ready_matrix_f1 => status_ready_matrix_f1,
+      status_ready_matrix_f2 => status_ready_matrix_f2,
+
       config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
       config_active_interruption_onError     => config_active_interruption_onError,
-      addr_matrix_f0                       => addr_matrix_f0,
---      addr_matrix_f0_1                       => addr_matrix_f0_1,
-      addr_matrix_f1                         => addr_matrix_f1,
-      addr_matrix_f2                         => addr_matrix_f2,
+
+      addr_matrix_f0 => addr_matrix_f0,
+      addr_matrix_f1 => addr_matrix_f1,
+      addr_matrix_f2 => addr_matrix_f2,
 
       matrix_time_f0 => matrix_time_f0,
---      matrix_time_f0_1 => matrix_time_f0_1,
-      matrix_time_f1   => matrix_time_f1,
-      matrix_time_f2   => matrix_time_f2
+      matrix_time_f1 => matrix_time_f1,
+      matrix_time_f2 => matrix_time_f2
       );
   -----------------------------------------------------------------------------
 
@@ -984,24 +880,6 @@ BEGIN
 
 
 
-
-
-
-
-
-  
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-  -----------------------------------------------------------------------------
-
-
-
-
-
-
   -----------------------------------------------------------------------------
   -- TIME MANAGMENT
   -----------------------------------------------------------------------------
@@ -1059,8 +937,6 @@ BEGIN
       time_out => time_reg_f2);
 
   -----------------------------------------------------------------------------
-  dma_time <= (OTHERS => '0');         -- TODO
-  -----------------------------------------------------------------------------
 
 
 
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
new file mode 100644
--- /dev/null
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_FFT.vhd
@@ -0,0 +1,76 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+
+LIBRARY lpp;
+USE lpp.lpp_memory.ALL;
+USE lpp.iir_filter.ALL;
+USE lpp.spectral_matrix_package.ALL;
+USE lpp.lpp_dma_pkg.ALL;
+USE lpp.lpp_Header.ALL;
+USE lpp.lpp_matrix.ALL;
+USE lpp.lpp_matrix.ALL;
+USE lpp.lpp_lfr_pkg.ALL;
+USE lpp.lpp_fft.ALL;
+USE lpp.fft_components.ALL;
+
+ENTITY lpp_lfr_ms_FFT IS
+  PORT (
+    clk  : IN STD_LOGIC;
+    rstn : IN STD_LOGIC;
+    -- IN
+    sample_valid : IN STD_LOGIC;
+    fft_read     : IN STD_LOGIC;
+    sample_data  : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+    sample_load  : OUT STD_LOGIC;
+
+    --OUT
+    fft_pong       : OUT STD_LOGIC;
+    fft_data_im    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    fft_data_re    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+    fft_data_valid : OUT STD_LOGIC;
+    fft_ready      : OUT STD_LOGIC
+    
+    );
+END;
+
+ARCHITECTURE Behavioral OF lpp_lfr_ms_FFT IS
+
+BEGIN
+
+  -----------------------------------------------------------------------------
+  -- FFT
+  -----------------------------------------------------------------------------
+  CoreFFT_1 : CoreFFT
+    GENERIC MAP (
+      LOGPTS      => gLOGPTS,
+      LOGLOGPTS   => gLOGLOGPTS,
+      WSIZE       => gWSIZE,
+      TWIDTH      => gTWIDTH,
+      DWIDTH      => gDWIDTH,
+      TDWIDTH     => gTDWIDTH,
+      RND_MODE    => gRND_MODE,
+      SCALE_MODE  => gSCALE_MODE,
+      PTS         => gPTS,
+      HALFPTS     => gHALFPTS,
+      inBuf_RWDLY => gInBuf_RWDLY)
+    PORT MAP (
+      clk       => clk,
+      ifiStart  => '0',                 -- '1'
+      ifiNreset => rstn,
+
+      ifiD_valid => sample_valid,       -- IN
+      ifiRead_y  => fft_read,
+      ifiD_im    => (OTHERS => '0'),    -- IN
+      ifiD_re    => sample_data,        -- IN
+      ifoLoad    => sample_load,        -- IN
+
+      ifoPong    => fft_pong,
+      ifoY_im    => fft_data_im,
+      ifoY_re    => fft_data_re,
+      ifoY_valid => fft_data_valid,
+      ifoY_rdy   => fft_ready);
+
+  -----------------------------------------------------------------------------
+
+END Behavioral;
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
@@ -65,32 +65,25 @@ ENTITY lpp_lfr_ms_fsmdma IS
     ---------------------------------------------------------------------------
     -- Reg out
     ready_matrix_f0             : OUT STD_LOGIC;
---    ready_matrix_f0_1             : OUT STD_LOGIC;
     ready_matrix_f1               : OUT STD_LOGIC;
     ready_matrix_f2               : OUT STD_LOGIC;
-    --error_anticipating_empty_fifo : OUT STD_LOGIC;
+    
     error_bad_component_error     : OUT STD_LOGIC;
     error_buffer_full             : OUT STD_LOGIC;
     debug_reg                     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 
     -- Reg In
     status_ready_matrix_f0             : IN STD_LOGIC;
---    status_ready_matrix_f0_1             : IN STD_LOGIC;
     status_ready_matrix_f1               : IN STD_LOGIC;
     status_ready_matrix_f2               : IN STD_LOGIC;
---    status_error_anticipating_empty_fifo : IN STD_LOGIC;
---    status_error_bad_component_error     : IN STD_LOGIC;
---    status_error_buffer_full             : IN STD_LOGIC;
 
     config_active_interruption_onNewMatrix : IN STD_LOGIC;
     config_active_interruption_onError     : IN STD_LOGIC;
     addr_matrix_f0                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
---s    addr_matrix_f0_1                       : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
     addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
     matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
---    matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
     matrix_time_f1   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
     matrix_time_f2   : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
 
@@ -114,27 +107,20 @@ ARCHITECTURE Behavioral OF lpp_lfr_ms_fs
   SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
   SIGNAL header_check_ok    : STD_LOGIC;
   SIGNAL address_matrix     : STD_LOGIC_VECTOR(31 DOWNTO 0);
---  SIGNAL send_matrix        : STD_LOGIC;
   SIGNAL Address            : STD_LOGIC_VECTOR(31 DOWNTO 0);
   -----------------------------------------------------------------------------
   -----------------------------------------------------------------------------
 
   SIGNAL component_send     : STD_LOGIC;
   SIGNAL component_send_ok  : STD_LOGIC;
---  SIGNAL component_send_ko  : STD_LOGIC;
   -----------------------------------------------------------------------------
   SIGNAL fifo_ren_trash     : STD_LOGIC;
---  SIGNAL component_fifo_ren : STD_LOGIC;
 
   -----------------------------------------------------------------------------
   SIGNAL debug_reg_s   : STD_LOGIC_VECTOR(31 DOWNTO 0);
   -----------------------------------------------------------------------------
   SIGNAL log_empty_fifo : STD_LOGIC;
   -----------------------------------------------------------------------------
-  --SIGNAL header_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-  --SIGNAL header_reg_val : STD_LOGIC;
-  --SIGNAL header_reg_ack : STD_LOGIC;
---  SIGNAL header_error   : STD_LOGIC;
 
   SIGNAL matrix_buffer_ready : STD_LOGIC;  
 BEGIN
@@ -143,7 +129,6 @@ BEGIN
 
   
   matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
-                         --'1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
                          '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0'   ELSE
                          '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0'   ELSE
                          '0';
@@ -154,12 +139,11 @@ BEGIN
                      '0';
 
   address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
-                    --addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
                     addr_matrix_f1   WHEN matrix_type = "01" ELSE
                     addr_matrix_f2   WHEN matrix_type = "10" ELSE
                     (OTHERS => '0');
 
-  debug_reg_s(31 DOWNTO 3) <= (OTHERS => '0');
+  debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
   -----------------------------------------------------------------------------
   -- DMA control
   -----------------------------------------------------------------------------
@@ -170,10 +154,8 @@ BEGIN
       component_type                <= (OTHERS => '0');
       state                         <= IDLE;
       ready_matrix_f0             <= '0';
---      ready_matrix_f0_1             <= '0';
       ready_matrix_f1               <= '0';
       ready_matrix_f2               <= '0';
---      error_anticipating_empty_fifo <= '0';
       error_bad_component_error     <= '0';
       error_buffer_full             <= '0';  -- TODO
       component_type_pre            <= "0000";
@@ -182,6 +164,10 @@ BEGIN
       address                       <= (OTHERS => '0');
 
       debug_reg_s(2 DOWNTO 0)  <= (OTHERS => '0');
+      debug_reg_s(5 DOWNTO 3)  <= (OTHERS => '0');
+      debug_reg_s(8 DOWNTO 6)  <= (OTHERS => '0');
+      debug_reg_s(10 DOWNTO 9)  <= (OTHERS => '0');
+      debug_reg_s(14 DOWNTO 11)  <= (OTHERS => '0');
 
       log_empty_fifo <= '0';
 
@@ -189,10 +175,22 @@ BEGIN
       matrix_time_f1 <= (OTHERS => '0');
       matrix_time_f2 <= (OTHERS => '0');
 
-    ELSIF HCLK'EVENT AND HCLK = '1' THEN 
+    ELSIF HCLK'EVENT AND HCLK = '1' THEN
+      --
+      debug_reg_s(3)  <= status_ready_matrix_f0;
+      debug_reg_s(4)  <= status_ready_matrix_f0;
+      debug_reg_s(5)  <= status_ready_matrix_f0;
+      debug_reg_s(6)  <= '0';
+      debug_reg_s(7)  <= '0';
+      debug_reg_s(8)  <= '0';
+      debug_reg_s(10 DOWNTO 9)  <= matrix_type;
+      debug_reg_s(14 DOWNTO 11)  <= component_type;
+      
+      --
+
+      
 
       ready_matrix_f0         <= '0';
---      ready_matrix_f0_1         <= '0';
       ready_matrix_f1           <= '0';
       ready_matrix_f2           <= '0';
       error_bad_component_error <= '0';
@@ -237,7 +235,6 @@ BEGIN
           debug_reg_s(2 DOWNTO 0) <= "100";
 
           error_bad_component_error     <= '0';
---          error_anticipating_empty_fifo <= '0';
           IF fifo_empty = '1' THEN
             state          <= IDLE;
             fifo_ren_trash <= '1';
@@ -246,15 +243,21 @@ BEGIN
           END IF;
 
         WHEN SEND_DATA =>
-          debug_reg_s(2 DOWNTO 0) <= "101";
+          debug_reg_s(2 DOWNTO 0) <= "010";
 
           IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
             state <= IDLE;
             IF component_type = "1110" THEN
               CASE matrix_type IS
-                WHEN "00"   => ready_matrix_f0   <= '1';
-                WHEN "01"   => ready_matrix_f1   <= '1';
-                WHEN "10"   => ready_matrix_f2   <= '1';
+                WHEN "00"   =>
+                  ready_matrix_f0   <= '1';
+                  debug_reg_s(6)    <= '1';
+                WHEN "01"   =>
+                  ready_matrix_f1   <= '1';
+                  debug_reg_s(7)    <= '1';
+                WHEN "10"   =>
+                  ready_matrix_f2   <= '1';
+                  debug_reg_s(8)    <= '1';
                 WHEN OTHERS => NULL;
               END CASE;
             END IF;
@@ -267,15 +270,12 @@ BEGIN
         WHEN WAIT_DATA_ACK =>
           log_empty_fifo <= fifo_empty OR log_empty_fifo;
 
-          debug_reg_s(2 DOWNTO 0) <= "110";
+          debug_reg_s(2 DOWNTO 0) <= "011";
 
           component_send <= '0';
           IF component_send_ok = '1' THEN
             address <= address + 64;
             state   <= SEND_DATA;
---          ELSIF component_send_ko = '1' THEN
---            error_anticipating_empty_fifo <= '0';
---            state                         <= TRASH_FIFO;
           END IF;
           
         WHEN OTHERS => NULL;
@@ -291,6 +291,5 @@ BEGIN
   fifo_ren        <= dma_ren AND fifo_ren_trash;
 
   component_send_ok <= dma_done;
---  component_send_ko <= '0';
   
 END Behavioral;
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
@@ -277,8 +277,6 @@ PACKAGE lpp_lfr_pkg IS
       observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
   END COMPONENT;
   -----------------------------------------------------------------------------
-  
-  
   COMPONENT lpp_lfr_apbreg
     GENERIC (
       nb_data_by_buffer_size : INTEGER;
@@ -299,30 +297,25 @@ PACKAGE lpp_lfr_pkg IS
       apbo                                   : OUT apb_slv_out_type;
       run_ms                                 : OUT STD_LOGIC;
       ready_matrix_f0_0                      : IN  STD_LOGIC;
-      ready_matrix_f0_1                      : IN  STD_LOGIC;
       ready_matrix_f1                        : IN  STD_LOGIC;
       ready_matrix_f2                        : IN  STD_LOGIC;
-      error_anticipating_empty_fifo          : IN  STD_LOGIC;
       error_bad_component_error              : IN  STD_LOGIC;
+      error_buffer_full                      : in  STD_LOGIC;
+      error_input_fifo_write                 : in  STD_LOGIC_VECTOR(2 DOWNTO 0);
       debug_reg                              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
       status_ready_matrix_f0_0               : OUT STD_LOGIC;
-      status_ready_matrix_f0_1               : OUT STD_LOGIC;
       status_ready_matrix_f1                 : OUT STD_LOGIC;
       status_ready_matrix_f2                 : OUT STD_LOGIC;
-      status_error_anticipating_empty_fifo   : OUT STD_LOGIC;
-      status_error_bad_component_error       : OUT STD_LOGIC;
       config_active_interruption_onNewMatrix : OUT STD_LOGIC;
       config_active_interruption_onError     : OUT STD_LOGIC;
       addr_matrix_f0_0                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-      addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+--      addr_matrix_f0_1                       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       addr_matrix_f1                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       addr_matrix_f2                         : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-
-      matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
-      matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
-      matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
-      matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
-    
+      matrix_time_f0_0                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
+--      matrix_time_f0_1                       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
+      matrix_time_f1                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
+      matrix_time_f2                         : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
       status_full                            : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
       status_full_ack                        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
       status_full_err                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -353,7 +346,6 @@ PACKAGE lpp_lfr_pkg IS
       addr_data_f2                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       addr_data_f3                           : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       start_date                             : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
-      ---------------------------------------------------------------------------
       debug_reg0                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
       debug_reg1                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
       debug_reg2                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -363,6 +355,8 @@ PACKAGE lpp_lfr_pkg IS
       debug_reg6                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
       debug_reg7                             : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
   END COMPONENT;
+  
+  
 
   COMPONENT lpp_top_ms
     GENERIC (