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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
48 ENTITY LFR_em IS
49
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
55 -- TAG --------------------------------------------------------------------
56 TAG3 : IN STD_ULOGIC; -- DSU rx data
57 TAG1 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
59 TAG4 : IN STD_ULOGIC; -- UART1 rx data
60 TAG2 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
89
90 END LFR_em;
91
92
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
123
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
127
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134
135 -----------------------------------------------------------------------------
136 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137
138 -----------------------------------------------------------------------------
139 SIGNAL rstn : STD_LOGIC;
140 BEGIN -- beh
141
142 -----------------------------------------------------------------------------
143 -- CLK
144 -----------------------------------------------------------------------------
145 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146
147 PROCESS(clk100MHz)
148 BEGIN
149 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 clk_50_s <= NOT clk_50_s;
151 END IF;
152 END PROCESS;
153
154 PROCESS(clk_50_s)
155 BEGIN
156 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 clk_25 <= NOT clk_25;
158 END IF;
159 END PROCESS;
160
161 PROCESS(clk49_152MHz)
162 BEGIN
163 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 clk_24 <= NOT clk_24;
165 END IF;
166 END PROCESS;
167
168 -----------------------------------------------------------------------------
169
170 PROCESS (clk_25, rstn)
171 BEGIN -- PROCESS
172 IF rstn = '0' THEN -- asynchronous reset (active low)
173 led(0) <= '0';
174 led(1) <= '0';
175 led(2) <= '0';
176 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 led(0) <= '0';
178 led(1) <= '1';
179 led(2) <= '1';
180 END IF;
181 END PROCESS;
182
183 --
184 leon3_soc_1 : leon3_soc
185 GENERIC MAP (
186 fabtech => apa3e,
187 memtech => apa3e,
188 padtech => inferred,
189 clktech => inferred,
190 disas => 0,
191 dbguart => 0,
192 pclow => 2,
193 clk_freq => 25000,
194 NB_CPU => 1,
195 ENABLE_FPU => 1,
196 FPU_NETLIST => 0,
197 ENABLE_DSU => 1,
198 ENABLE_AHB_UART => 1,
199 ENABLE_APB_UART => 1,
200 ENABLE_IRQMP => 1,
201 ENABLE_GPT => 1,
202 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE)
205 PORT MAP (
206 clk => clk_25,
207 reset => rstn,
208 errorn => OPEN,
209
210 ahbrxd => TAG3,
211 ahbtxd => TAG1,
212 urxd1 => TAG4,
213 utxd1 => TAG2,
214
215 address => address,
216 data => data,
217 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_WE => nSRAM_WE,
222 nSRAM_CE => nSRAM_CE,
223 nSRAM_OE => nSRAM_OE,
224
225 apbi_ext => apbi_ext,
226 apbo_ext => apbo_ext,
227 ahbi_s_ext => ahbi_s_ext,
228 ahbo_s_ext => ahbo_s_ext,
229 ahbi_m_ext => ahbi_m_ext,
230 ahbo_m_ext => ahbo_m_ext);
231
232
233 -------------------------------------------------------------------------------
234 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -------------------------------------------------------------------------------
236 apb_lfr_time_management_1 : apb_lfr_time_management
237 GENERIC MAP (
238 pindex => 6,
239 paddr => 6,
240 pmask => 16#fff#,
241 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 PORT MAP (
244 clk25MHz => clk_25,
245 clk24_576MHz => clk_24, -- 49.152MHz/2
246 resetn => rstn,
247 grspw_tick => swno.tickout,
248 apbi => apbi_ext,
249 apbo => apbo_ext(6),
250 coarse_time => coarse_time,
251 fine_time => fine_time);
252
253 -----------------------------------------------------------------------
254 --- SpaceWire --------------------------------------------------------
255 -----------------------------------------------------------------------
256
257 -- SPW_EN <= '1';
258
259 spw_clk <= clk_50_s;
260 spw_rxtxclk <= spw_clk;
261 spw_rxclkn <= NOT spw_rxtxclk;
262
263 -- PADS for SPW1
264 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 PORT MAP (spw1_din, dtmp(0));
266 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 PORT MAP (spw1_sin, stmp(0));
268 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 PORT MAP (spw1_dout, swno.d(0));
270 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 PORT MAP (spw1_sout, swno.s(0));
272 -- PADS FOR SPW2
273 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 PORT MAP (spw2_sin, dtmp(1));
275 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 PORT MAP (spw2_din, stmp(1));
277 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 PORT MAP (spw2_dout, swno.d(1));
279 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 PORT MAP (spw2_sout, swno.s(1));
281
282 -- GRSPW PHY
283 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_phy0 : grspw_phy
286 GENERIC MAP(
287 tech => apa3e,
288 rxclkbuftype => 1,
289 scantest => 0)
290 PORT MAP(
291 rxrst => swno.rxrst,
292 di => dtmp(j),
293 si => stmp(j),
294 rxclko => spw_rxclk(j),
295 do => swni.d(j),
296 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 END GENERATE spw_inputloop;
299
300 -- SPW core
301 sw0 : grspwm GENERIC MAP(
302 tech => apa3e,
303 hindex => 1,
304 pindex => 5,
305 paddr => 5,
306 pirq => 11,
307 sysfreq => 25000, -- CPU_FREQ
308 rmap => 1,
309 rmapcrc => 1,
310 fifosize1 => 16,
311 fifosize2 => 16,
312 rxclkbuftype => 1,
313 rxunaligned => 0,
314 rmapbufs => 4,
315 ft => 0,
316 netlist => 0,
317 ports => 2,
318 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 memtech => apa3e,
320 destkey => 2,
321 spwcore => 1
322 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 )
326 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 swni, swno);
330
331 swni.tickin <= '0';
332 swni.rmapen <= '1';
333 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.tickinraw <= '0';
335 swni.timein <= (OTHERS => '0');
336 swni.dcrstval <= (OTHERS => '0');
337 swni.timerrstval <= (OTHERS => '0');
338
339 -------------------------------------------------------------------------------
340 -- LFR ------------------------------------------------------------------------
341 -------------------------------------------------------------------------------
342 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 GENERIC MAP (
344 Mem_use => use_RAM,
345 nb_data_by_buffer_size => 32,
346 nb_word_by_buffer_size => 30,
347 nb_snapshot_param_size => 32,
348 delta_vector_size => 32,
349 delta_vector_size_f0_2 => 7, -- log2(96)
350 pindex => 15,
351 paddr => 15,
352 pmask => 16#fff#,
353 pirq_ms => 6,
354 pirq_wfp => 14,
355 hindex => 2,
356 top_lfr_version => X"000109") -- aa.bb.cc version
357 -- AA : BOARD NUMBER
358 -- 0 => MINI_LFR
359 -- 1 => EM
360 PORT MAP (
361 clk => clk_25,
362 rstn => rstn,
363 sample_B => sample(2 DOWNTO 0),
364 sample_E => sample(7 DOWNTO 3),
365 sample_val => sample_val,
366 apbi => apbi_ext,
367 apbo => apbo_ext(15),
368 ahbi => ahbi_m_ext,
369 ahbo => ahbo_m_ext(2),
370 coarse_time => coarse_time,
371 fine_time => fine_time,
372 data_shaping_BW => bias_fail_sw,
373 observation_reg => observation_reg);
374
375 -----------------------------------------------------------------------------
376 --
377 -----------------------------------------------------------------------------
378 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
379 GENERIC MAP (
380 ChanelCount => 8,
381 ncycle_cnv_high => 40, -- TODO : 79
382 ncycle_cnv => 250) -- TODO : 500
383 PORT MAP (
384 cnv_clk => clk_24, -- TODO : 49.152
385 cnv_rstn => rstn, -- ok
386 cnv => ADC_smpclk, -- ok
387 clk => clk_25, -- ok
388 rstn => rstn, -- ok
389 ADC_data => ADC_data, -- ok
390 ADC_nOE => ADC_OEB_bar_CH, -- ok
391 sample => sample, -- ok
392 sample_val => sample_val); -- ok
393
394 TAG8 <= ADC_smpclk;
395
396 END beh;
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_em
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-em.vhd
17 #VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
19 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
24
25 TECHLIBS = proasic3e
26
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc
29
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./lpp_cna \
38 ./lpp_uart \
39 ./lpp_usb \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd
46
47 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/software/leon3/Makefile
49
50 ################## project specific targets ##########################
51
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