diff --git a/designs/LFR-em-WFP_MS/.config b/designs/LFR-em-WFP_MS/.config
new file mode 100644
--- /dev/null
+++ b/designs/LFR-em-WFP_MS/.config
@@ -0,0 +1,288 @@
+#
+# Automatically generated make config: don't edit
+#
+
+#
+# Synthesis      
+#
+# CONFIG_SYN_INFERRED is not set
+# CONFIG_SYN_STRATIX is not set
+# CONFIG_SYN_STRATIXII is not set
+# CONFIG_SYN_STRATIXIII is not set
+# CONFIG_SYN_CYCLONEIII is not set
+# CONFIG_SYN_ALTERA is not set
+# CONFIG_SYN_AXCEL is not set
+# CONFIG_SYN_PROASIC is not set
+# CONFIG_SYN_PROASICPLUS is not set
+CONFIG_SYN_PROASIC3=y
+# CONFIG_SYN_UT025CRH is not set
+# CONFIG_SYN_ATC18 is not set
+# CONFIG_SYN_ATC18RHA is not set
+# CONFIG_SYN_CUSTOM1 is not set
+# CONFIG_SYN_EASIC90 is not set
+# CONFIG_SYN_IHP25 is not set
+# CONFIG_SYN_IHP25RH is not set
+# CONFIG_SYN_LATTICE is not set
+# CONFIG_SYN_ECLIPSE is not set
+# CONFIG_SYN_PEREGRINE is not set
+# CONFIG_SYN_RH_LIB18T is not set
+# CONFIG_SYN_RHUMC is not set
+# CONFIG_SYN_SMIC13 is not set
+# CONFIG_SYN_SPARTAN2 is not set
+# CONFIG_SYN_SPARTAN3 is not set
+# CONFIG_SYN_SPARTAN3E is not set
+# CONFIG_SYN_VIRTEX is not set
+# CONFIG_SYN_VIRTEXE is not set
+# CONFIG_SYN_VIRTEX2 is not set
+# CONFIG_SYN_VIRTEX4 is not set
+# CONFIG_SYN_VIRTEX5 is not set
+# CONFIG_SYN_UMC is not set
+# CONFIG_SYN_TSMC90 is not set
+# CONFIG_SYN_INFER_RAM is not set
+# CONFIG_SYN_INFER_PADS is not set
+# CONFIG_SYN_NO_ASYNC is not set
+# CONFIG_SYN_SCAN is not set
+
+#
+# Clock generation
+#
+# CONFIG_CLK_INFERRED is not set
+# CONFIG_CLK_HCLKBUF is not set
+# CONFIG_CLK_ALTDLL is not set
+# CONFIG_CLK_LATDLL is not set
+CONFIG_CLK_PRO3PLL=y
+# CONFIG_CLK_LIB18T is not set
+# CONFIG_CLK_RHUMC is not set
+# CONFIG_CLK_CLKDLL is not set
+# CONFIG_CLK_DCM is not set
+CONFIG_CLK_MUL=2
+CONFIG_CLK_DIV=8
+CONFIG_OCLK_DIV=2
+# CONFIG_PCI_SYSCLK is not set
+CONFIG_LEON3=y
+CONFIG_PROC_NUM=1
+
+#
+# Processor            
+#
+
+#
+# Integer unit                                           
+#
+CONFIG_IU_NWINDOWS=8
+# CONFIG_IU_V8MULDIV is not set
+# CONFIG_IU_SVT is not set
+CONFIG_IU_LDELAY=1
+CONFIG_IU_WATCHPOINTS=0
+# CONFIG_PWD is not set
+CONFIG_IU_RSTADDR=00000
+
+#
+# Floating-point unit
+#
+# CONFIG_FPU_ENABLE is not set
+
+#
+# Cache system
+#
+CONFIG_ICACHE_ENABLE=y
+CONFIG_ICACHE_ASSO1=y
+# CONFIG_ICACHE_ASSO2 is not set
+# CONFIG_ICACHE_ASSO3 is not set
+# CONFIG_ICACHE_ASSO4 is not set
+# CONFIG_ICACHE_SZ1 is not set
+# CONFIG_ICACHE_SZ2 is not set
+CONFIG_ICACHE_SZ4=y
+# CONFIG_ICACHE_SZ8 is not set
+# CONFIG_ICACHE_SZ16 is not set
+# CONFIG_ICACHE_SZ32 is not set
+# CONFIG_ICACHE_SZ64 is not set
+# CONFIG_ICACHE_SZ128 is not set
+# CONFIG_ICACHE_SZ256 is not set
+# CONFIG_ICACHE_LZ16 is not set
+CONFIG_ICACHE_LZ32=y
+CONFIG_DCACHE_ENABLE=y
+CONFIG_DCACHE_ASSO1=y
+# CONFIG_DCACHE_ASSO2 is not set
+# CONFIG_DCACHE_ASSO3 is not set
+# CONFIG_DCACHE_ASSO4 is not set
+# CONFIG_DCACHE_SZ1 is not set
+# CONFIG_DCACHE_SZ2 is not set
+CONFIG_DCACHE_SZ4=y
+# CONFIG_DCACHE_SZ8 is not set
+# CONFIG_DCACHE_SZ16 is not set
+# CONFIG_DCACHE_SZ32 is not set
+# CONFIG_DCACHE_SZ64 is not set
+# CONFIG_DCACHE_SZ128 is not set
+# CONFIG_DCACHE_SZ256 is not set
+# CONFIG_DCACHE_LZ16 is not set
+CONFIG_DCACHE_LZ32=y
+# CONFIG_DCACHE_SNOOP is not set
+CONFIG_CACHE_FIXED=0
+
+#
+# MMU
+#
+CONFIG_MMU_ENABLE=y
+# CONFIG_MMU_COMBINED is not set
+CONFIG_MMU_SPLIT=y
+# CONFIG_MMU_REPARRAY is not set
+CONFIG_MMU_REPINCREMENT=y
+# CONFIG_MMU_I2 is not set
+# CONFIG_MMU_I4 is not set
+CONFIG_MMU_I8=y
+# CONFIG_MMU_I16 is not set
+# CONFIG_MMU_I32 is not set
+# CONFIG_MMU_D2 is not set
+# CONFIG_MMU_D4 is not set
+CONFIG_MMU_D8=y
+# CONFIG_MMU_D16 is not set
+# CONFIG_MMU_D32 is not set
+CONFIG_MMU_FASTWB=y
+CONFIG_MMU_PAGE_4K=y
+# CONFIG_MMU_PAGE_8K is not set
+# CONFIG_MMU_PAGE_16K is not set
+# CONFIG_MMU_PAGE_32K is not set
+# CONFIG_MMU_PAGE_PROG is not set
+
+#
+# Debug Support Unit        
+#
+# CONFIG_DSU_ENABLE is not set
+
+#
+# Fault-tolerance  
+#
+
+#
+# VHDL debug settings       
+#
+# CONFIG_IU_DISAS is not set
+# CONFIG_DEBUG_PC32 is not set
+
+#
+# AMBA configuration
+#
+CONFIG_AHB_DEFMST=0
+CONFIG_AHB_RROBIN=y
+# CONFIG_AHB_SPLIT is not set
+CONFIG_AHB_IOADDR=FFF
+CONFIG_APB_HADDR=800
+# CONFIG_AHB_MON is not set
+
+#
+# Debug Link           
+#
+CONFIG_DSU_UART=y
+# CONFIG_DSU_JTAG is not set
+
+#
+# Peripherals             
+#
+
+#
+# Memory controllers             
+#
+
+#
+# 8/32-bit PROM/SRAM controller 
+#
+CONFIG_SRCTRL=y
+# CONFIG_SRCTRL_8BIT is not set
+CONFIG_SRCTRL_PROMWS=3
+CONFIG_SRCTRL_RAMWS=0
+CONFIG_SRCTRL_IOWS=0
+# CONFIG_SRCTRL_RMW is not set
+CONFIG_SRCTRL_SRBANKS1=y
+# CONFIG_SRCTRL_SRBANKS2 is not set
+# CONFIG_SRCTRL_SRBANKS3 is not set
+# CONFIG_SRCTRL_SRBANKS4 is not set
+# CONFIG_SRCTRL_SRBANKS5 is not set
+# CONFIG_SRCTRL_BANKSZ0 is not set
+# CONFIG_SRCTRL_BANKSZ1 is not set
+# CONFIG_SRCTRL_BANKSZ2 is not set
+# CONFIG_SRCTRL_BANKSZ3 is not set
+# CONFIG_SRCTRL_BANKSZ4 is not set
+# CONFIG_SRCTRL_BANKSZ5 is not set
+# CONFIG_SRCTRL_BANKSZ6 is not set
+# CONFIG_SRCTRL_BANKSZ7 is not set
+# CONFIG_SRCTRL_BANKSZ8 is not set
+# CONFIG_SRCTRL_BANKSZ9 is not set
+# CONFIG_SRCTRL_BANKSZ10 is not set
+# CONFIG_SRCTRL_BANKSZ11 is not set
+# CONFIG_SRCTRL_BANKSZ12 is not set
+# CONFIG_SRCTRL_BANKSZ13 is not set
+CONFIG_SRCTRL_ROMASEL=19
+
+#
+# Leon2 memory controller        
+#
+CONFIG_MCTRL_LEON2=y
+# CONFIG_MCTRL_8BIT is not set
+# CONFIG_MCTRL_16BIT is not set
+# CONFIG_MCTRL_5CS is not set
+# CONFIG_MCTRL_SDRAM is not set
+
+#
+# PC133 SDRAM controller             
+#
+# CONFIG_SDCTRL is not set
+
+#
+# On-chip RAM/ROM                 
+#
+# CONFIG_AHBROM_ENABLE is not set
+# CONFIG_AHBRAM_ENABLE is not set
+
+#
+# Ethernet             
+#
+# CONFIG_GRETH_ENABLE is not set
+
+#
+# CAN                     
+#
+# CONFIG_CAN_ENABLE is not set
+
+#
+# PCI              
+#
+# CONFIG_PCI_SIMPLE_TARGET is not set
+# CONFIG_PCI_MASTER_TARGET is not set
+# CONFIG_PCI_ARBITER is not set
+# CONFIG_PCI_TRACE is not set
+
+#
+# Spacewire 
+#
+# CONFIG_SPW_ENABLE is not set
+
+#
+# UARTs, timers and irq control         
+#
+CONFIG_UART1_ENABLE=y
+# CONFIG_UA1_FIFO1 is not set
+# CONFIG_UA1_FIFO2 is not set
+CONFIG_UA1_FIFO4=y
+# CONFIG_UA1_FIFO8 is not set
+# CONFIG_UA1_FIFO16 is not set
+# CONFIG_UA1_FIFO32 is not set
+# CONFIG_UART2_ENABLE is not set
+CONFIG_IRQ3_ENABLE=y
+# CONFIG_IRQ3_SEC is not set
+CONFIG_GPT_ENABLE=y
+CONFIG_GPT_NTIM=2
+CONFIG_GPT_SW=8
+CONFIG_GPT_TW=32
+CONFIG_GPT_IRQ=8
+CONFIG_GPT_SEPIRQ=y
+CONFIG_GPT_WDOGEN=y
+CONFIG_GPT_WDOG=FFFF
+CONFIG_GRGPIO_ENABLE=y
+CONFIG_GRGPIO_WIDTH=8
+CONFIG_GRGPIO_IMASK=0000
+
+#
+# VHDL Debugging        
+#
+# CONFIG_DEBUG_UART is not set
diff --git a/designs/LFR-em-WFP_MS/LFR-em.vhd b/designs/LFR-em-WFP_MS/LFR-em.vhd
new file mode 100644
--- /dev/null
+++ b/designs/LFR-em-WFP_MS/LFR-em.vhd
@@ -0,0 +1,396 @@
+------------------------------------------------------------------------------
+--  This file is a part of the LPP VHDL IP LIBRARY
+--  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
+--
+--  This program is free software; you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation; either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program; if not, write to the Free Software
+--  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA 
+-------------------------------------------------------------------------------
+--                    Author : Jean-christophe Pellion
+--                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
+-------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_1164.ALL;
+LIBRARY grlib;
+USE grlib.amba.ALL;
+USE grlib.stdlib.ALL;
+LIBRARY techmap;
+USE techmap.gencomp.ALL;
+LIBRARY gaisler;
+USE gaisler.memctrl.ALL;
+USE gaisler.leon3.ALL;
+USE gaisler.uart.ALL;
+USE gaisler.misc.ALL;
+USE gaisler.spacewire.ALL;
+LIBRARY esa;
+USE esa.memoryctrl.ALL;
+LIBRARY lpp;
+USE lpp.lpp_memory.ALL;
+USE lpp.lpp_ad_conv.ALL;
+USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
+USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
+USE lpp.iir_filter.ALL;
+USE lpp.general_purpose.ALL;
+USE lpp.lpp_lfr_time_management.ALL;
+USE lpp.lpp_leon3_soc_pkg.ALL;
+
+ENTITY LFR_em IS
+  
+  PORT (
+    clk100MHz    : IN STD_ULOGIC;                       
+    clk49_152MHz : IN STD_ULOGIC;                       
+    reset        : IN STD_ULOGIC;
+                      
+    -- TAG --------------------------------------------------------------------
+    TAG3 : IN  STD_ULOGIC;            -- DSU rx data   
+    TAG1 : OUT STD_ULOGIC;            -- DSU tx data  
+    -- UART APB ---------------------------------------------------------------
+    TAG4 : IN  STD_ULOGIC;            -- UART1 rx data 
+    TAG2 : OUT STD_ULOGIC;            -- UART1 tx data   
+    -- RAM --------------------------------------------------------------------
+    address   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);    
+    data      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);    
+    nSRAM_BE0 : OUT   STD_LOGIC;                        
+    nSRAM_BE1 : OUT   STD_LOGIC;                        
+    nSRAM_BE2 : OUT   STD_LOGIC;                        
+    nSRAM_BE3 : OUT   STD_LOGIC;                        
+    nSRAM_WE  : OUT   STD_LOGIC;                        
+    nSRAM_CE  : OUT   STD_LOGIC;                        
+    nSRAM_OE  : OUT   STD_LOGIC;                        
+    -- SPW --------------------------------------------------------------------
+    spw1_din  : IN  STD_LOGIC;                                  
+    spw1_sin  : IN  STD_LOGIC;                                  
+    spw1_dout : OUT STD_LOGIC;                                  
+    spw1_sout : OUT STD_LOGIC;                           
+    spw2_din  : IN  STD_LOGIC;                             
+    spw2_sin  : IN  STD_LOGIC;                             
+    spw2_dout : OUT STD_LOGIC;                             
+    spw2_sout : OUT STD_LOGIC;                           
+    -- ADC --------------------------------------------------------------------
+    bias_fail_sw   : OUT STD_LOGIC;                     
+    ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    ADC_smpclk     : OUT STD_LOGIC;
+    ADC_data       : IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
+    ---------------------------------------------------------------------------
+    TAG8 : OUT STD_LOGIC;
+    led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)  
+    );
+
+END LFR_em;
+
+
+ARCHITECTURE beh OF LFR_em IS
+  SIGNAL clk_50_s    : STD_LOGIC := '0';
+  SIGNAL clk_25      : STD_LOGIC := '0';
+  SIGNAL clk_24      : STD_LOGIC := '0';
+  -----------------------------------------------------------------------------
+  SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
+  
+  -- CONSTANTS
+  CONSTANT CFG_PADTECH   : INTEGER := inferred;
+  CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
+  CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
+  CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
+
+  SIGNAL apbi_ext   : apb_slv_in_type;
+  SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
+  SIGNAL ahbi_s_ext : ahb_slv_in_type;
+  SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
+  SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
+  SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
+
+-- Spacewire signals
+  SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
+  SIGNAL spw_rxtxclk : STD_ULOGIC;
+  SIGNAL spw_rxclkn  : STD_ULOGIC;
+  SIGNAL spw_clk     : STD_LOGIC;
+  SIGNAL swni        : grspw_in_type;
+  SIGNAL swno        : grspw_out_type;
+
+--GPIO
+  SIGNAL gpioi : gpio_in_type;
+  SIGNAL gpioo : gpio_out_type;
+
+-- AD Converter ADS7886
+  SIGNAL sample      : Samples14v(7 DOWNTO 0);
+  SIGNAL sample_val  : STD_LOGIC;
+  SIGNAL ADC_nCS_sig : STD_LOGIC;
+  SIGNAL ADC_CLK_sig : STD_LOGIC;
+  SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
+  
+  -----------------------------------------------------------------------------
+  SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+  -----------------------------------------------------------------------------
+  SIGNAL rstn : STD_LOGIC;
+BEGIN  -- beh
+
+  -----------------------------------------------------------------------------
+  -- CLK
+  -----------------------------------------------------------------------------
+  rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
+
+  PROCESS(clk100MHz)
+  BEGIN
+    IF clk100MHz'EVENT AND clk100MHz = '1' THEN
+      clk_50_s <= NOT clk_50_s;
+    END IF;
+  END PROCESS;
+
+  PROCESS(clk_50_s)
+  BEGIN
+    IF clk_50_s'EVENT AND clk_50_s = '1' THEN
+      clk_25 <= NOT clk_25;
+    END IF;
+  END PROCESS;
+
+  PROCESS(clk49_152MHz)
+  BEGIN
+    IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
+      clk_24 <= NOT clk_24;
+    END IF;
+  END PROCESS;
+
+  -----------------------------------------------------------------------------
+
+  PROCESS (clk_25, rstn)
+  BEGIN  -- PROCESS
+    IF rstn = '0' THEN                 -- asynchronous reset (active low)
+      led(0) <= '0';
+      led(1) <= '0';
+      led(2) <= '0';
+    ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
+      led(0) <= '0';
+      led(1) <= '1';
+      led(2) <= '1';
+    END IF;
+  END PROCESS;
+
+  --
+  leon3_soc_1 : leon3_soc
+    GENERIC MAP (
+      fabtech         => apa3e,
+      memtech         => apa3e,
+      padtech         => inferred,
+      clktech         => inferred,
+      disas           => 0,
+      dbguart         => 0,
+      pclow           => 2,
+      clk_freq        => 25000,
+      NB_CPU          => 1,
+      ENABLE_FPU      => 1,
+      FPU_NETLIST     => 0,
+      ENABLE_DSU      => 1,
+      ENABLE_AHB_UART => 1,
+      ENABLE_APB_UART => 1,
+      ENABLE_IRQMP    => 1,
+      ENABLE_GPT      => 1,
+      NB_AHB_MASTER   => NB_AHB_MASTER,
+      NB_AHB_SLAVE    => NB_AHB_SLAVE,
+      NB_APB_SLAVE    => NB_APB_SLAVE)
+    PORT MAP (
+      clk       => clk_25,
+      reset     => rstn,
+      errorn    => OPEN,
+
+      ahbrxd    => TAG3,
+      ahbtxd    => TAG1,
+      urxd1     => TAG4,
+      utxd1     => TAG2,
+      
+      address   => address,
+      data      => data,
+      nSRAM_BE0 => nSRAM_BE0,
+      nSRAM_BE1 => nSRAM_BE1,
+      nSRAM_BE2 => nSRAM_BE2,
+      nSRAM_BE3 => nSRAM_BE3,
+      nSRAM_WE  => nSRAM_WE,
+      nSRAM_CE  => nSRAM_CE,
+      nSRAM_OE  => nSRAM_OE,
+
+      apbi_ext   => apbi_ext,
+      apbo_ext   => apbo_ext,
+      ahbi_s_ext => ahbi_s_ext,
+      ahbo_s_ext => ahbo_s_ext,
+      ahbi_m_ext => ahbi_m_ext,
+      ahbo_m_ext => ahbo_m_ext);
+
+
+-------------------------------------------------------------------------------
+-- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
+-------------------------------------------------------------------------------
+  apb_lfr_time_management_1 : apb_lfr_time_management
+    GENERIC MAP (
+      pindex => 6,
+      paddr  => 6,
+      pmask  => 16#fff#,
+      FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
+      NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
+    PORT MAP (
+      clk25MHz     => clk_25,
+      clk24_576MHz => clk_24,           -- 49.152MHz/2
+      resetn       => rstn,
+      grspw_tick   => swno.tickout,
+      apbi         => apbi_ext,
+      apbo         => apbo_ext(6),
+      coarse_time  => coarse_time,
+      fine_time    => fine_time);
+
+-----------------------------------------------------------------------
+---  SpaceWire --------------------------------------------------------
+-----------------------------------------------------------------------
+
+--  SPW_EN <= '1';
+
+  spw_clk     <= clk_50_s;
+  spw_rxtxclk <= spw_clk;
+  spw_rxclkn  <= NOT spw_rxtxclk;
+
+  -- PADS for SPW1
+  spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw1_din, dtmp(0));
+  spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw1_sin, stmp(0));
+  spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw1_dout, swno.d(0));
+  spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw1_sout, swno.s(0));
+  -- PADS FOR SPW2
+  spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
+    PORT MAP (spw2_sin, dtmp(1));
+  spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
+    PORT MAP (spw2_din, stmp(1));
+  spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw2_dout, swno.d(1));
+  spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
+    PORT MAP (spw2_sout, swno.s(1));
+
+  -- GRSPW PHY
+  --spw1_input: if CFG_SPW_GRSPW = 1 generate
+  spw_inputloop : FOR j IN 0 TO 1 GENERATE
+    spw_phy0 : grspw_phy
+      GENERIC MAP(
+        tech         => apa3e,
+        rxclkbuftype => 1,
+        scantest     => 0)
+      PORT MAP(
+        rxrst    => swno.rxrst,
+        di       => dtmp(j),
+        si       => stmp(j),
+        rxclko   => spw_rxclk(j),
+        do       => swni.d(j),
+        ndo      => swni.nd(j*5+4 DOWNTO j*5),
+        dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
+  END GENERATE spw_inputloop;
+
+  -- SPW core
+  sw0 : grspwm GENERIC MAP(
+    tech         => apa3e,
+    hindex       => 1,
+    pindex       => 5,
+    paddr        => 5,
+    pirq         => 11,
+    sysfreq      => 25000,              -- CPU_FREQ
+    rmap         => 1,
+    rmapcrc      => 1,
+    fifosize1    => 16,
+    fifosize2    => 16,
+    rxclkbuftype => 1,
+    rxunaligned  => 0,
+    rmapbufs     => 4,
+    ft           => 0,
+    netlist      => 0,
+    ports        => 2,
+    --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
+    memtech      => apa3e,
+    destkey      => 2,
+    spwcore      => 1
+    --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
+    --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
+    --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
+    )
+    PORT MAP(rstn, clk_25, spw_rxclk(0),
+             spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
+             ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
+             swni, swno);
+
+  swni.tickin      <= '0';
+  swni.rmapen      <= '1';
+  swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
+  swni.tickinraw   <= '0';
+  swni.timein      <= (OTHERS => '0');
+  swni.dcrstval    <= (OTHERS => '0');
+  swni.timerrstval <= (OTHERS => '0');
+
+-------------------------------------------------------------------------------
+-- LFR ------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+  lpp_lfr_1 : lpp_lfr_WFP_nMS
+    GENERIC MAP (
+      Mem_use                => use_RAM,
+      nb_data_by_buffer_size => 32,
+      nb_word_by_buffer_size => 30,
+      nb_snapshot_param_size => 32,
+      delta_vector_size      => 32,
+      delta_vector_size_f0_2 => 7,      -- log2(96)
+      pindex                 => 15,
+      paddr                  => 15,
+      pmask                  => 16#fff#,
+      pirq_ms                => 6,
+      pirq_wfp               => 14,
+      hindex                 => 2,
+      top_lfr_version        => X"000109")  -- aa.bb.cc version
+                                            -- AA : BOARD NUMBER
+                                            -- 0 => MINI_LFR
+                                            -- 1 => EM
+    PORT MAP (
+      clk             => clk_25,
+      rstn            => rstn,
+      sample_B        => sample(2 DOWNTO 0),
+      sample_E        => sample(7 DOWNTO 3),
+      sample_val      => sample_val,
+      apbi            => apbi_ext,
+      apbo            => apbo_ext(15),
+      ahbi            => ahbi_m_ext,
+      ahbo            => ahbo_m_ext(2),
+      coarse_time     => coarse_time,
+      fine_time       => fine_time,
+      data_shaping_BW => bias_fail_sw,
+      observation_reg => observation_reg);
+
+  -----------------------------------------------------------------------------
+  -- 
+  -----------------------------------------------------------------------------
+  top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
+    GENERIC MAP (
+      ChanelCount     => 8,
+      ncycle_cnv_high => 40,            -- TODO : 79
+      ncycle_cnv      => 250)           -- TODO : 500
+    PORT MAP (
+      cnv_clk    => clk_24,             -- TODO : 49.152
+      cnv_rstn   => rstn,               -- ok
+      cnv        => ADC_smpclk,         -- ok
+      clk        => clk_25,             -- ok
+      rstn       => rstn,               -- ok
+      ADC_data   => ADC_data,           -- ok
+      ADC_nOE    => ADC_OEB_bar_CH,     -- ok
+      sample     => sample,             -- ok
+      sample_val => sample_val);        -- ok
+
+  TAG8 <= ADC_smpclk;
+
+END beh;
diff --git a/designs/LFR-em-WFP_MS/Makefile b/designs/LFR-em-WFP_MS/Makefile
new file mode 100644
--- /dev/null
+++ b/designs/LFR-em-WFP_MS/Makefile
@@ -0,0 +1,51 @@
+#GRLIB=../..
+VHDLIB=../..
+SCRIPTSDIR=$(VHDLIB)/scripts/
+GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
+TOP=LFR_em
+BOARD=em-LeonLPP-A3PE3kL-v3-core1
+include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
+DEVICE=$(PART)-$(PACKAGE)$(SPEED)
+UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
+QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
+EFFORT=high
+XSTOPT=
+SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
+#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
+#VHDLSYNFILES=config.vhd leon3mp.vhd
+VHDLSYNFILES=LFR-em.vhd
+#VHDLSIMFILES=testbench.vhd
+#SIMTOP=testbench
+#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
+#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
+PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
+BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
+CLEAN=soft-clean
+
+TECHLIBS = proasic3e
+
+LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
+	tmtc openchip hynix ihp gleichmann micron usbhc
+
+DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
+	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
+	./amba_lcd_16x2_ctrlr \
+	./general_purpose/lpp_AMR \
+	./general_purpose/lpp_balise \
+	./general_purpose/lpp_delay \
+	./lpp_bootloader \
+	./lpp_cna \
+	./lpp_uart \
+	./lpp_usb \
+
+FILESKIP = i2cmst.vhd \
+	APB_MULTI_DIODE.vhd \
+	APB_MULTI_DIODE.vhd \
+	Top_MatrixSpec.vhd \
+	APB_FFT.vhd
+
+include $(GRLIB)/bin/Makefile
+include $(GRLIB)/software/leon3/Makefile
+
+##################  project specific targets ##########################
+