@@ -499,7 +499,7 BEGIN | |||
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499 | 499 | pirq_ms => 6, |
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500 | 500 | pirq_wfp => 14, |
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501 | 501 | hindex => 2, |
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502 |
top_lfr_version => X"0000000 |
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502 | top_lfr_version => X"00000009") | |
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503 | 503 | PORT MAP ( |
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504 | 504 | clk => clkm, |
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505 | 505 | rstn => rstn, |
@@ -140,6 +140,8 ARCHITECTURE beh OF MINI_LFR_top IS | |||
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140 | 140 | SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none); |
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141 | 141 | SIGNAL ahbi_m_ext : AHB_Mst_In_Type; |
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142 | 142 | SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none); |
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143 | -- | |
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144 | SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0); | |
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143 | 145 | |
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144 | 146 | BEGIN -- beh |
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145 | 147 | |
@@ -176,7 +178,10 BEGIN -- beh | |||
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176 | 178 | IO5 <= '0'; |
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177 | 179 | IO6 <= '0'; |
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178 | 180 | IO7 <= '0'; |
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179 |
IO8 <= ' |
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181 | IO8 <= '0'; | |
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182 | IO9 <= '0'; | |
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183 | IO10 <= '0'; | |
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184 | IO11 <= '0'; | |
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180 | 185 | ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge |
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181 | 186 | LED0 <= '0'; |
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182 | 187 | LED1 <= '1'; |
@@ -188,7 +193,10 BEGIN -- beh | |||
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188 | 193 | IO5 <= ADC_SDO(3) OR ADC_SDO(4); |
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189 | 194 | IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7); |
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190 | 195 | IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1; |
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191 |
IO8 <= |
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196 | IO8 <= IO_s(8); | |
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197 | IO9 <= IO_s(9); | |
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198 | IO10 <= IO_s(10); | |
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199 | IO11 <= IO_s(11); | |
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192 | 200 | END IF; |
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193 | 201 | END PROCESS; |
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194 | 202 | |
@@ -234,9 +242,10 BEGIN -- beh | |||
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234 | 242 | ahbmo => ahbo_m_ext(1), |
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235 | 243 | apbi => apbi_ext, |
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236 | 244 | apbo => apbo_ext(5), |
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237 | out_ren => IO11, | |
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238 | out_send => IO10, | |
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239 | out_done => IO9 | |
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245 | out_ren => IO_s(11), | |
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246 | out_send => IO_s(10), | |
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247 | out_done => IO_s(9), | |
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248 | out_dmaout_okay => IO_s(8) | |
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240 | 249 | ); |
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241 | 250 | |
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242 | 251 | ----------------------------------------------------------------------------- |
@@ -63,7 +63,8 ENTITY lpp_debug_dma_singleOrBurst IS | |||
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63 | 63 | -- observation SIGNAL |
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64 | 64 | out_ren : OUT STD_LOGIC; |
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65 | 65 | out_send : OUT STD_LOGIC; |
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66 |
out_done : OUT STD_LOGIC |
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66 | out_done : OUT STD_LOGIC; | |
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67 | out_dmaout_okay : OUT STD_LOGIC | |
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67 | 68 | ); |
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68 | 69 | END; |
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69 | 70 | |
@@ -117,7 +118,8 BEGIN | |||
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117 | 118 | done => done, -- out |
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118 | 119 | ren => ren, -- out |
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119 | 120 | address => address, |
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120 |
data => data |
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121 | data => data, | |
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122 | debug_dmaout_okay => out_dmaout_okay); | |
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121 | 123 | |
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122 | 124 | |
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123 | 125 | run <= reg.run; |
@@ -43,7 +43,9 PACKAGE lpp_debug_lfr_pkg IS | |||
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43 | 43 | apbo : OUT apb_slv_out_type; |
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44 | 44 | out_ren : OUT STD_LOGIC; |
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45 | 45 | out_send : OUT STD_LOGIC; |
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46 |
out_done : OUT STD_LOGIC |
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46 | out_done : OUT STD_LOGIC; | |
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47 | out_dmaout_okay : OUT STD_LOGIC | |
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48 | ); | |
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47 | 49 | END COMPONENT; |
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48 | 50 | |
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49 | 51 | END; |
@@ -213,7 +213,8 PACKAGE lpp_dma_pkg IS | |||
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213 | 213 | done : OUT STD_LOGIC; |
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214 | 214 | ren : OUT STD_LOGIC; |
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215 | 215 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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216 |
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) |
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216 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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217 | debug_dmaout_okay : OUT STD_LOGIC); | |
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217 | 218 | END COMPONENT; |
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218 | 219 | |
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219 | 220 | END; |
@@ -54,6 +54,7 ENTITY lpp_dma_send_16word IS | |||
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54 | 54 | -- |
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55 | 55 | send_ok : OUT STD_LOGIC; |
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56 | 56 | send_ko : OUT STD_LOGIC |
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57 | ||
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57 | 58 |
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58 | 59 | END lpp_dma_send_16word; |
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59 | 60 | |
@@ -167,8 +168,14 BEGIN -- beh | |||
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167 | 168 | |
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168 | 169 | DMAIn.Data <= data; |
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169 | 170 | |
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170 |
ren <= '0' WHEN DMAOut.OKAY = '1' |
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171 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE | |
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171 | 172 | '1'; |
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173 | ||
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174 | -- \/ JC - 11/12/2013 \/ | |
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175 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE | |
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176 | -- '1'; | |
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177 | -- /\ JC - 11/12/2013 /\ | |
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178 | ||
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172 | 179 | -- \/ JC - 10/12/2013 \/ |
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173 | 180 | --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE |
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174 | 181 | -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE |
@@ -62,7 +62,10 ENTITY lpp_dma_singleOrBurst IS | |||
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62 | 62 | done : OUT STD_LOGIC; |
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63 | 63 | ren : OUT STD_LOGIC; |
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64 | 64 | address : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0) | |
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65 | data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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66 | -- | |
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67 | debug_dmaout_okay : OUT STD_LOGIC | |
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68 | ||
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66 | 69 |
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67 | 70 | END; |
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68 | 71 | |
@@ -94,6 +97,9 ARCHITECTURE Behavioral OF lpp_dma_singl | |||
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94 | 97 | SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0); |
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95 | 98 | BEGIN |
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96 | 99 | |
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100 | debug_dmaout_okay <= DMAOut.OKAY; | |
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101 | ||
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102 | ||
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97 | 103 |
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98 | 104 | -- DMA to AHB interface |
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99 | 105 | DMA2AHB_1 : DMA2AHB |
@@ -132,7 +138,10 BEGIN | |||
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132 | 138 | |
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133 | 139 | --ren <= burst_ren WHEN valid_burst = '1' ELSE |
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134 | 140 | -- NOT single_send_ok; |
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135 | ren <= burst_ren AND single_ren; | |
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141 | --ren <= burst_ren AND single_ren; | |
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142 | ||
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143 | ren <= '0' WHEN DMAOut.OKAY = '1' ELSE | |
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144 | '1'; | |
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136 | 145 | |
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137 | 146 | ----------------------------------------------------------------------------- |
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138 | 147 | -- SEND 1 word by DMA |
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