@@ -428,7 +428,7 BEGIN -- beh | |||||
428 | pirq_ms => 6, |
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428 | pirq_ms => 6, | |
429 | pirq_wfp => 14, |
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429 | pirq_wfp => 14, | |
430 | hindex => 2, |
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430 | hindex => 2, | |
431 |
top_lfr_version => X"00011 |
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431 | top_lfr_version => X"000117") -- aa.bb.cc version | |
432 | PORT MAP ( |
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432 | PORT MAP ( | |
433 | clk => clk_25, |
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433 | clk => clk_25, | |
434 | rstn => reset, |
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434 | rstn => reset, |
@@ -120,7 +120,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
120 | -- |
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120 | -- | |
121 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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121 | SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
122 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); |
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122 | SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
123 |
SIGNAL sample_f |
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123 | SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); | |
124 | -- |
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124 | -- | |
125 | SIGNAL sample_f0_val : STD_LOGIC; |
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125 | SIGNAL sample_f0_val : STD_LOGIC; | |
126 | SIGNAL sample_f1_val : STD_LOGIC; |
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126 | SIGNAL sample_f1_val : STD_LOGIC; | |
@@ -134,7 +134,7 ARCHITECTURE beh OF lpp_lfr IS | |||||
134 | -- |
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134 | -- | |
135 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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135 | SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
136 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); |
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136 | SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
137 |
SIGNAL sample_f |
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137 | SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0); | |
138 |
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138 | |||
139 | -- SM |
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139 | -- SM | |
140 | SIGNAL ready_matrix_f0 : STD_LOGIC; |
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140 | SIGNAL ready_matrix_f0 : STD_LOGIC; | |
@@ -672,12 +672,12 BEGIN | |||||
672 | NOT(sample_f0_val) & NOT(sample_f0_val); |
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672 | NOT(sample_f0_val) & NOT(sample_f0_val); | |
673 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & |
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673 | sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & | |
674 | NOT(sample_f1_val) & NOT(sample_f1_val); |
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674 | NOT(sample_f1_val) & NOT(sample_f1_val); | |
675 |
sample_f |
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675 | sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & | |
676 |
NOT(sample_f |
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676 | NOT(sample_f2_val) & NOT(sample_f2_val); | |
677 |
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677 | |||
678 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) |
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678 | sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB) | |
679 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); |
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679 | sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16)); | |
680 |
sample_f |
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680 | sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16)); | |
681 |
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681 | |||
682 | ------------------------------------------------------------------------------- |
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682 | ------------------------------------------------------------------------------- | |
683 |
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683 | |||
@@ -745,4 +745,4 BEGIN | |||||
745 | debug_ms(11 DOWNTO 0) & -- 23 .. 12 |
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745 | debug_ms(11 DOWNTO 0) & -- 23 .. 12 | |
746 | debug_signal(11 DOWNTO 0); -- 11 .. 0 |
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746 | debug_signal(11 DOWNTO 0); -- 11 .. 0 | |
747 |
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747 | |||
748 |
END beh; |
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748 | END beh; No newline at end of file |
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