diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
--- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
+++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd
@@ -428,7 +428,7 @@ BEGIN  -- beh
       pirq_ms                => 6,
       pirq_wfp               => 14,
       hindex                 => 2,
-      top_lfr_version        => X"000116")  -- aa.bb.cc version
+      top_lfr_version        => X"000117")  -- aa.bb.cc version
     PORT MAP (
       clk             => clk_25,
       rstn            => reset,
diff --git a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
--- a/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
+++ b/lib/lpp/lpp_top_lfr/lpp_lfr.vhd
@@ -120,7 +120,7 @@ ARCHITECTURE beh OF lpp_lfr IS
   --
   SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
   SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
-  SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+  SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
   --
   SIGNAL sample_f0_val    : STD_LOGIC;
   SIGNAL sample_f1_val    : STD_LOGIC;
@@ -134,7 +134,7 @@ ARCHITECTURE beh OF lpp_lfr IS
   --
   SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
   SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-  SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+  SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
 
   -- SM
   SIGNAL ready_matrix_f0                      : STD_LOGIC;
@@ -672,12 +672,12 @@ BEGIN
                    NOT(sample_f0_val) & NOT(sample_f0_val);
   sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                    NOT(sample_f1_val) & NOT(sample_f1_val);
-  sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
-                   NOT(sample_f3_val) & NOT(sample_f3_val);
+  sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
+                   NOT(sample_f2_val) & NOT(sample_f2_val);
 
   sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
   sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
-  sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
+  sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
 
   -------------------------------------------------------------------------------
 
@@ -745,4 +745,4 @@ BEGIN
     debug_ms(11 DOWNTO 0) &     -- 23 .. 12
     debug_signal(11 DOWNTO 0);  -- 11 .. 0
   
-END beh;
+END beh;
\ No newline at end of file