HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r394:d544c8db0c81

Change on MS_F2 the data at 16Hz by the data at 256Hz

pellion -

r394:d544c8db0c81 (MINI-LFR) WFP_MS-0-1-23 JC

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r394:d544c8db0c81

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designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +1 -1

                    pirq_ms                => 6,
                    pirq_wfp               => 14,
                    hindex                 => 2,
-                   top_lfr_version        => X"000116")  -- aa.bb.cc version
+                   top_lfr_version        => X"000117")  -- aa.bb.cc version
                  PORT MAP (
                    clk             => clk_25,
                    rstn            => reset,

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +6 -6

                --
                SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
                SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
-               SIGNAL sample_f3_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
+               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
                --
                SIGNAL sample_f0_val    : STD_LOGIC;
                SIGNAL sample_f1_val    : STD_LOGIC;
                --
                SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
-               SIGNAL sample_f3_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
+               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                -- SM
                SIGNAL ready_matrix_f0                      : STD_LOGIC;
                                 NOT(sample_f0_val) & NOT(sample_f0_val);
                sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                 NOT(sample_f1_val) & NOT(sample_f1_val);
-               sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
-                                NOT(sample_f3_val) & NOT(sample_f3_val);
+               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
+                                NOT(sample_f2_val) & NOT(sample_f2_val);
                sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
                sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
-               sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
+               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
                -------------------------------------------------------------------------------
                  debug_ms(11 DOWNTO 0) &     -- 23 .. 12
                  debug_signal(11 DOWNTO 0);  -- 11 .. 0
-             END beh;
+             END beh;
  No newline at end of file

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