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Change on MS_F2 the data at 16Hz by the data at 256Hz
pellion -
r394:d544c8db0c81 (MINI-LFR) WFP_MS-0-1-23 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
176 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
177 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
178
178
179 BEGIN -- beh
179 BEGIN -- beh
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK
182 -- CLK
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184
184
185 PROCESS(clk_50)
185 PROCESS(clk_50)
186 BEGIN
186 BEGIN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
187 IF clk_50'EVENT AND clk_50 = '1' THEN
188 clk_50_s <= NOT clk_50_s;
188 clk_50_s <= NOT clk_50_s;
189 END IF;
189 END IF;
190 END PROCESS;
190 END PROCESS;
191
191
192 PROCESS(clk_50_s)
192 PROCESS(clk_50_s)
193 BEGIN
193 BEGIN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
194 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
195 clk_25 <= NOT clk_25;
195 clk_25 <= NOT clk_25;
196 END IF;
196 END IF;
197 END PROCESS;
197 END PROCESS;
198
198
199 PROCESS(clk_49)
199 PROCESS(clk_49)
200 BEGIN
200 BEGIN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
201 IF clk_49'EVENT AND clk_49 = '1' THEN
202 clk_24 <= NOT clk_24;
202 clk_24 <= NOT clk_24;
203 END IF;
203 END IF;
204 END PROCESS;
204 END PROCESS;
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207
207
208 PROCESS (clk_25, reset)
208 PROCESS (clk_25, reset)
209 BEGIN -- PROCESS
209 BEGIN -- PROCESS
210 IF reset = '0' THEN -- asynchronous reset (active low)
210 IF reset = '0' THEN -- asynchronous reset (active low)
211 LED0 <= '0';
211 LED0 <= '0';
212 LED1 <= '0';
212 LED1 <= '0';
213 LED2 <= '0';
213 LED2 <= '0';
214 --IO1 <= '0';
214 --IO1 <= '0';
215 --IO2 <= '1';
215 --IO2 <= '1';
216 --IO3 <= '0';
216 --IO3 <= '0';
217 --IO4 <= '0';
217 --IO4 <= '0';
218 --IO5 <= '0';
218 --IO5 <= '0';
219 --IO6 <= '0';
219 --IO6 <= '0';
220 --IO7 <= '0';
220 --IO7 <= '0';
221 --IO8 <= '0';
221 --IO8 <= '0';
222 --IO9 <= '0';
222 --IO9 <= '0';
223 --IO10 <= '0';
223 --IO10 <= '0';
224 --IO11 <= '0';
224 --IO11 <= '0';
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
225 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
226 LED0 <= '0';
226 LED0 <= '0';
227 LED1 <= '1';
227 LED1 <= '1';
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
228 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
229 --IO1 <= '1';
229 --IO1 <= '1';
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
230 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
231 --IO3 <= ADC_SDO(0);
231 --IO3 <= ADC_SDO(0);
232 --IO4 <= ADC_SDO(1);
232 --IO4 <= ADC_SDO(1);
233 --IO5 <= ADC_SDO(2);
233 --IO5 <= ADC_SDO(2);
234 --IO6 <= ADC_SDO(3);
234 --IO6 <= ADC_SDO(3);
235 --IO7 <= ADC_SDO(4);
235 --IO7 <= ADC_SDO(4);
236 --IO8 <= ADC_SDO(5);
236 --IO8 <= ADC_SDO(5);
237 --IO9 <= ADC_SDO(6);
237 --IO9 <= ADC_SDO(6);
238 --IO10 <= ADC_SDO(7);
238 --IO10 <= ADC_SDO(7);
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
239 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
240 END IF;
240 END IF;
241 END PROCESS;
241 END PROCESS;
242
242
243 PROCESS (clk_24, reset)
243 PROCESS (clk_24, reset)
244 BEGIN -- PROCESS
244 BEGIN -- PROCESS
245 IF reset = '0' THEN -- asynchronous reset (active low)
245 IF reset = '0' THEN -- asynchronous reset (active low)
246 I00_s <= '0';
246 I00_s <= '0';
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
247 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
248 I00_s <= NOT I00_s ;
248 I00_s <= NOT I00_s ;
249 END IF;
249 END IF;
250 END PROCESS;
250 END PROCESS;
251 -- IO0 <= I00_s;
251 -- IO0 <= I00_s;
252
252
253 --UARTs
253 --UARTs
254 nCTS1 <= '1';
254 nCTS1 <= '1';
255 nCTS2 <= '1';
255 nCTS2 <= '1';
256 nDCD2 <= '1';
256 nDCD2 <= '1';
257
257
258 --EXT CONNECTOR
258 --EXT CONNECTOR
259
259
260 --SPACE WIRE
260 --SPACE WIRE
261
261
262 leon3_soc_1 : leon3_soc
262 leon3_soc_1 : leon3_soc
263 GENERIC MAP (
263 GENERIC MAP (
264 fabtech => apa3e,
264 fabtech => apa3e,
265 memtech => apa3e,
265 memtech => apa3e,
266 padtech => inferred,
266 padtech => inferred,
267 clktech => inferred,
267 clktech => inferred,
268 disas => 0,
268 disas => 0,
269 dbguart => 0,
269 dbguart => 0,
270 pclow => 2,
270 pclow => 2,
271 clk_freq => 25000,
271 clk_freq => 25000,
272 NB_CPU => 1,
272 NB_CPU => 1,
273 ENABLE_FPU => 1,
273 ENABLE_FPU => 1,
274 FPU_NETLIST => 0,
274 FPU_NETLIST => 0,
275 ENABLE_DSU => 1,
275 ENABLE_DSU => 1,
276 ENABLE_AHB_UART => 1,
276 ENABLE_AHB_UART => 1,
277 ENABLE_APB_UART => 1,
277 ENABLE_APB_UART => 1,
278 ENABLE_IRQMP => 1,
278 ENABLE_IRQMP => 1,
279 ENABLE_GPT => 1,
279 ENABLE_GPT => 1,
280 NB_AHB_MASTER => NB_AHB_MASTER,
280 NB_AHB_MASTER => NB_AHB_MASTER,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
281 NB_AHB_SLAVE => NB_AHB_SLAVE,
282 NB_APB_SLAVE => NB_APB_SLAVE)
282 NB_APB_SLAVE => NB_APB_SLAVE)
283 PORT MAP (
283 PORT MAP (
284 clk => clk_25,
284 clk => clk_25,
285 reset => reset,
285 reset => reset,
286 errorn => errorn,
286 errorn => errorn,
287 ahbrxd => TXD1,
287 ahbrxd => TXD1,
288 ahbtxd => RXD1,
288 ahbtxd => RXD1,
289 urxd1 => TXD2,
289 urxd1 => TXD2,
290 utxd1 => RXD2,
290 utxd1 => RXD2,
291 address => SRAM_A,
291 address => SRAM_A,
292 data => SRAM_DQ,
292 data => SRAM_DQ,
293 nSRAM_BE0 => SRAM_nBE(0),
293 nSRAM_BE0 => SRAM_nBE(0),
294 nSRAM_BE1 => SRAM_nBE(1),
294 nSRAM_BE1 => SRAM_nBE(1),
295 nSRAM_BE2 => SRAM_nBE(2),
295 nSRAM_BE2 => SRAM_nBE(2),
296 nSRAM_BE3 => SRAM_nBE(3),
296 nSRAM_BE3 => SRAM_nBE(3),
297 nSRAM_WE => SRAM_nWE,
297 nSRAM_WE => SRAM_nWE,
298 nSRAM_CE => SRAM_CE,
298 nSRAM_CE => SRAM_CE,
299 nSRAM_OE => SRAM_nOE,
299 nSRAM_OE => SRAM_nOE,
300
300
301 apbi_ext => apbi_ext,
301 apbi_ext => apbi_ext,
302 apbo_ext => apbo_ext,
302 apbo_ext => apbo_ext,
303 ahbi_s_ext => ahbi_s_ext,
303 ahbi_s_ext => ahbi_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
304 ahbo_s_ext => ahbo_s_ext,
305 ahbi_m_ext => ahbi_m_ext,
305 ahbi_m_ext => ahbi_m_ext,
306 ahbo_m_ext => ahbo_m_ext);
306 ahbo_m_ext => ahbo_m_ext);
307
307
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
309 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
310 -------------------------------------------------------------------------------
310 -------------------------------------------------------------------------------
311 apb_lfr_time_management_1 : apb_lfr_time_management
311 apb_lfr_time_management_1 : apb_lfr_time_management
312 GENERIC MAP (
312 GENERIC MAP (
313 pindex => 6,
313 pindex => 6,
314 paddr => 6,
314 paddr => 6,
315 pmask => 16#fff#,
315 pmask => 16#fff#,
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
316 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
317 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
318 PORT MAP (
318 PORT MAP (
319 clk25MHz => clk_25,
319 clk25MHz => clk_25,
320 clk24_576MHz => clk_24, -- 49.152MHz/2
320 clk24_576MHz => clk_24, -- 49.152MHz/2
321 resetn => reset,
321 resetn => reset,
322 grspw_tick => swno.tickout,
322 grspw_tick => swno.tickout,
323 apbi => apbi_ext,
323 apbi => apbi_ext,
324 apbo => apbo_ext(6),
324 apbo => apbo_ext(6),
325 coarse_time => coarse_time,
325 coarse_time => coarse_time,
326 fine_time => fine_time);
326 fine_time => fine_time);
327
327
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
329 --- SpaceWire --------------------------------------------------------
330 -----------------------------------------------------------------------
330 -----------------------------------------------------------------------
331
331
332 SPW_EN <= '1';
332 SPW_EN <= '1';
333
333
334 spw_clk <= clk_50_s;
334 spw_clk <= clk_50_s;
335 spw_rxtxclk <= spw_clk;
335 spw_rxtxclk <= spw_clk;
336 spw_rxclkn <= NOT spw_rxtxclk;
336 spw_rxclkn <= NOT spw_rxtxclk;
337
337
338 -- PADS for SPW1
338 -- PADS for SPW1
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
340 PORT MAP (SPW_NOM_DIN, dtmp(0));
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
341 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_SIN, stmp(0));
342 PORT MAP (SPW_NOM_SIN, stmp(0));
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
344 PORT MAP (SPW_NOM_DOUT, swno.d(0));
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
345 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
346 PORT MAP (SPW_NOM_SOUT, swno.s(0));
347 -- PADS FOR SPW2
347 -- PADS FOR SPW2
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_SIN, dtmp(1));
349 PORT MAP (SPW_RED_SIN, dtmp(1));
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
350 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
351 PORT MAP (SPW_RED_DIN, stmp(1));
351 PORT MAP (SPW_RED_DIN, stmp(1));
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
353 PORT MAP (SPW_RED_DOUT, swno.d(1));
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
354 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
355 PORT MAP (SPW_RED_SOUT, swno.s(1));
356
356
357 -- GRSPW PHY
357 -- GRSPW PHY
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
358 --spw1_input: if CFG_SPW_GRSPW = 1 generate
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
359 spw_inputloop : FOR j IN 0 TO 1 GENERATE
360 spw_phy0 : grspw_phy
360 spw_phy0 : grspw_phy
361 GENERIC MAP(
361 GENERIC MAP(
362 tech => apa3e,
362 tech => apa3e,
363 rxclkbuftype => 1,
363 rxclkbuftype => 1,
364 scantest => 0)
364 scantest => 0)
365 PORT MAP(
365 PORT MAP(
366 rxrst => swno.rxrst,
366 rxrst => swno.rxrst,
367 di => dtmp(j),
367 di => dtmp(j),
368 si => stmp(j),
368 si => stmp(j),
369 rxclko => spw_rxclk(j),
369 rxclko => spw_rxclk(j),
370 do => swni.d(j),
370 do => swni.d(j),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
371 ndo => swni.nd(j*5+4 DOWNTO j*5),
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
372 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
373 END GENERATE spw_inputloop;
373 END GENERATE spw_inputloop;
374
374
375 -- SPW core
375 -- SPW core
376 sw0 : grspwm GENERIC MAP(
376 sw0 : grspwm GENERIC MAP(
377 tech => apa3e,
377 tech => apa3e,
378 hindex => 1,
378 hindex => 1,
379 pindex => 5,
379 pindex => 5,
380 paddr => 5,
380 paddr => 5,
381 pirq => 11,
381 pirq => 11,
382 sysfreq => 25000, -- CPU_FREQ
382 sysfreq => 25000, -- CPU_FREQ
383 rmap => 1,
383 rmap => 1,
384 rmapcrc => 1,
384 rmapcrc => 1,
385 fifosize1 => 16,
385 fifosize1 => 16,
386 fifosize2 => 16,
386 fifosize2 => 16,
387 rxclkbuftype => 1,
387 rxclkbuftype => 1,
388 rxunaligned => 0,
388 rxunaligned => 0,
389 rmapbufs => 4,
389 rmapbufs => 4,
390 ft => 0,
390 ft => 0,
391 netlist => 0,
391 netlist => 0,
392 ports => 2,
392 ports => 2,
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
393 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
394 memtech => apa3e,
394 memtech => apa3e,
395 destkey => 2,
395 destkey => 2,
396 spwcore => 1
396 spwcore => 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
397 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
398 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
399 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
400 )
400 )
401 PORT MAP(reset, clk_25, spw_rxclk(0),
401 PORT MAP(reset, clk_25, spw_rxclk(0),
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
402 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
403 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
404 swni, swno);
404 swni, swno);
405
405
406 swni.tickin <= '0';
406 swni.tickin <= '0';
407 swni.rmapen <= '1';
407 swni.rmapen <= '1';
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
408 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
409 swni.tickinraw <= '0';
409 swni.tickinraw <= '0';
410 swni.timein <= (OTHERS => '0');
410 swni.timein <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
411 swni.dcrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
412 swni.timerrstval <= (OTHERS => '0');
413
413
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
415 -- LFR ------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
416 -------------------------------------------------------------------------------
417 lpp_lfr_1 : lpp_lfr
417 lpp_lfr_1 : lpp_lfr
418 GENERIC MAP (
418 GENERIC MAP (
419 Mem_use => use_RAM,
419 Mem_use => use_RAM,
420 nb_data_by_buffer_size => 32,
420 nb_data_by_buffer_size => 32,
421 nb_word_by_buffer_size => 30,
421 nb_word_by_buffer_size => 30,
422 nb_snapshot_param_size => 32,
422 nb_snapshot_param_size => 32,
423 delta_vector_size => 32,
423 delta_vector_size => 32,
424 delta_vector_size_f0_2 => 7, -- log2(96)
424 delta_vector_size_f0_2 => 7, -- log2(96)
425 pindex => 15,
425 pindex => 15,
426 paddr => 15,
426 paddr => 15,
427 pmask => 16#fff#,
427 pmask => 16#fff#,
428 pirq_ms => 6,
428 pirq_ms => 6,
429 pirq_wfp => 14,
429 pirq_wfp => 14,
430 hindex => 2,
430 hindex => 2,
431 top_lfr_version => X"000116") -- aa.bb.cc version
431 top_lfr_version => X"000117") -- aa.bb.cc version
432 PORT MAP (
432 PORT MAP (
433 clk => clk_25,
433 clk => clk_25,
434 rstn => reset,
434 rstn => reset,
435 sample_B => sample_s(2 DOWNTO 0),
435 sample_B => sample_s(2 DOWNTO 0),
436 sample_E => sample_s(7 DOWNTO 3),
436 sample_E => sample_s(7 DOWNTO 3),
437 sample_val => sample_val,
437 sample_val => sample_val,
438 apbi => apbi_ext,
438 apbi => apbi_ext,
439 apbo => apbo_ext(15),
439 apbo => apbo_ext(15),
440 ahbi => ahbi_m_ext,
440 ahbi => ahbi_m_ext,
441 ahbo => ahbo_m_ext(2),
441 ahbo => ahbo_m_ext(2),
442 coarse_time => coarse_time,
442 coarse_time => coarse_time,
443 fine_time => fine_time,
443 fine_time => fine_time,
444 data_shaping_BW => bias_fail_sw_sig,
444 data_shaping_BW => bias_fail_sw_sig,
445 observation_vector_0=> observation_vector_0,
445 observation_vector_0=> observation_vector_0,
446 observation_vector_1 => observation_vector_1,
446 observation_vector_1 => observation_vector_1,
447 observation_reg => observation_reg);
447 observation_reg => observation_reg);
448
448
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
449 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
450 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
451 END GENERATE all_sample;
451 END GENERATE all_sample;
452
452
453
453
454
454
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
455 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
456 GENERIC MAP(
456 GENERIC MAP(
457 ChannelCount => 8,
457 ChannelCount => 8,
458 SampleNbBits => 14,
458 SampleNbBits => 14,
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
459 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
460 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
461 PORT MAP (
461 PORT MAP (
462 -- CONV
462 -- CONV
463 cnv_clk => clk_24,
463 cnv_clk => clk_24,
464 cnv_rstn => reset,
464 cnv_rstn => reset,
465 cnv => ADC_nCS_sig,
465 cnv => ADC_nCS_sig,
466 -- DATA
466 -- DATA
467 clk => clk_25,
467 clk => clk_25,
468 rstn => reset,
468 rstn => reset,
469 sck => ADC_CLK_sig,
469 sck => ADC_CLK_sig,
470 sdo => ADC_SDO_sig,
470 sdo => ADC_SDO_sig,
471 -- SAMPLE
471 -- SAMPLE
472 sample => sample,
472 sample => sample,
473 sample_val => sample_val);
473 sample_val => sample_val);
474
474
475 --IO10 <= ADC_SDO_sig(5);
475 --IO10 <= ADC_SDO_sig(5);
476 --IO9 <= ADC_SDO_sig(4);
476 --IO9 <= ADC_SDO_sig(4);
477 --IO8 <= ADC_SDO_sig(3);
477 --IO8 <= ADC_SDO_sig(3);
478
478
479 ADC_nCS <= ADC_nCS_sig;
479 ADC_nCS <= ADC_nCS_sig;
480 ADC_CLK <= ADC_CLK_sig;
480 ADC_CLK <= ADC_CLK_sig;
481 ADC_SDO_sig <= ADC_SDO;
481 ADC_SDO_sig <= ADC_SDO;
482
482
483 ----------------------------------------------------------------------
483 ----------------------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
484 --- GPIO -----------------------------------------------------------
485 ----------------------------------------------------------------------
485 ----------------------------------------------------------------------
486
486
487 grgpio0 : grgpio
487 grgpio0 : grgpio
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
488 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
489 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
490
490
491 --pio_pad_0 : iopad
491 --pio_pad_0 : iopad
492 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- GENERIC MAP (tech => CFG_PADTECH)
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
493 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
494 --pio_pad_1 : iopad
494 --pio_pad_1 : iopad
495 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- GENERIC MAP (tech => CFG_PADTECH)
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
496 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
497 --pio_pad_2 : iopad
497 --pio_pad_2 : iopad
498 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- GENERIC MAP (tech => CFG_PADTECH)
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
499 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
500 --pio_pad_3 : iopad
500 --pio_pad_3 : iopad
501 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- GENERIC MAP (tech => CFG_PADTECH)
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
502 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
503 --pio_pad_4 : iopad
503 --pio_pad_4 : iopad
504 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- GENERIC MAP (tech => CFG_PADTECH)
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
505 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
506 --pio_pad_5 : iopad
506 --pio_pad_5 : iopad
507 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- GENERIC MAP (tech => CFG_PADTECH)
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
508 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
509 --pio_pad_6 : iopad
509 --pio_pad_6 : iopad
510 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- GENERIC MAP (tech => CFG_PADTECH)
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
511 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
512 --pio_pad_7 : iopad
512 --pio_pad_7 : iopad
513 -- GENERIC MAP (tech => CFG_PADTECH)
513 -- GENERIC MAP (tech => CFG_PADTECH)
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
514 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
515
515
516 PROCESS (clk_25, reset)
516 PROCESS (clk_25, reset)
517 BEGIN -- PROCESS
517 BEGIN -- PROCESS
518 IF reset = '0' THEN -- asynchronous reset (active low)
518 IF reset = '0' THEN -- asynchronous reset (active low)
519 IO0 <= '0';
519 IO0 <= '0';
520 IO1 <= '0';
520 IO1 <= '0';
521 IO2 <= '0';
521 IO2 <= '0';
522 IO3 <= '0';
522 IO3 <= '0';
523 IO4 <= '0';
523 IO4 <= '0';
524 IO5 <= '0';
524 IO5 <= '0';
525 IO6 <= '0';
525 IO6 <= '0';
526 IO7 <= '0';
526 IO7 <= '0';
527 IO8 <= '0';
527 IO8 <= '0';
528 IO9 <= '0';
528 IO9 <= '0';
529 IO10 <= '0';
529 IO10 <= '0';
530 IO11 <= '0';
530 IO11 <= '0';
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
531 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
532 CASE gpioo.dout(2 DOWNTO 0) IS
532 CASE gpioo.dout(2 DOWNTO 0) IS
533 WHEN "011" =>
533 WHEN "011" =>
534 IO0 <= observation_reg(0 );
534 IO0 <= observation_reg(0 );
535 IO1 <= observation_reg(1 );
535 IO1 <= observation_reg(1 );
536 IO2 <= observation_reg(2 );
536 IO2 <= observation_reg(2 );
537 IO3 <= observation_reg(3 );
537 IO3 <= observation_reg(3 );
538 IO4 <= observation_reg(4 );
538 IO4 <= observation_reg(4 );
539 IO5 <= observation_reg(5 );
539 IO5 <= observation_reg(5 );
540 IO6 <= observation_reg(6 );
540 IO6 <= observation_reg(6 );
541 IO7 <= observation_reg(7 );
541 IO7 <= observation_reg(7 );
542 IO8 <= observation_reg(8 );
542 IO8 <= observation_reg(8 );
543 IO9 <= observation_reg(9 );
543 IO9 <= observation_reg(9 );
544 IO10 <= observation_reg(10);
544 IO10 <= observation_reg(10);
545 IO11 <= observation_reg(11);
545 IO11 <= observation_reg(11);
546 WHEN "001" =>
546 WHEN "001" =>
547 IO0 <= observation_reg(0 + 12);
547 IO0 <= observation_reg(0 + 12);
548 IO1 <= observation_reg(1 + 12);
548 IO1 <= observation_reg(1 + 12);
549 IO2 <= observation_reg(2 + 12);
549 IO2 <= observation_reg(2 + 12);
550 IO3 <= observation_reg(3 + 12);
550 IO3 <= observation_reg(3 + 12);
551 IO4 <= observation_reg(4 + 12);
551 IO4 <= observation_reg(4 + 12);
552 IO5 <= observation_reg(5 + 12);
552 IO5 <= observation_reg(5 + 12);
553 IO6 <= observation_reg(6 + 12);
553 IO6 <= observation_reg(6 + 12);
554 IO7 <= observation_reg(7 + 12);
554 IO7 <= observation_reg(7 + 12);
555 IO8 <= observation_reg(8 + 12);
555 IO8 <= observation_reg(8 + 12);
556 IO9 <= observation_reg(9 + 12);
556 IO9 <= observation_reg(9 + 12);
557 IO10 <= observation_reg(10 + 12);
557 IO10 <= observation_reg(10 + 12);
558 IO11 <= observation_reg(11 + 12);
558 IO11 <= observation_reg(11 + 12);
559 WHEN "010" =>
559 WHEN "010" =>
560 IO0 <= observation_reg(0 + 12 + 12);
560 IO0 <= observation_reg(0 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
561 IO1 <= observation_reg(1 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
562 IO2 <= observation_reg(2 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
563 IO3 <= observation_reg(3 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
564 IO4 <= observation_reg(4 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
565 IO5 <= observation_reg(5 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
566 IO6 <= observation_reg(6 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
567 IO7 <= observation_reg(7 + 12 + 12);
568 IO8 <= '0';
568 IO8 <= '0';
569 IO9 <= '0';
569 IO9 <= '0';
570 IO10 <= '0';
570 IO10 <= '0';
571 IO11 <= '0';
571 IO11 <= '0';
572 WHEN "000" =>
572 WHEN "000" =>
573 IO0 <= observation_vector_0(0 );
573 IO0 <= observation_vector_0(0 );
574 IO1 <= observation_vector_0(1 );
574 IO1 <= observation_vector_0(1 );
575 IO2 <= observation_vector_0(2 );
575 IO2 <= observation_vector_0(2 );
576 IO3 <= observation_vector_0(3 );
576 IO3 <= observation_vector_0(3 );
577 IO4 <= observation_vector_0(4 );
577 IO4 <= observation_vector_0(4 );
578 IO5 <= observation_vector_0(5 );
578 IO5 <= observation_vector_0(5 );
579 IO6 <= observation_vector_0(6 );
579 IO6 <= observation_vector_0(6 );
580 IO7 <= observation_vector_0(7 );
580 IO7 <= observation_vector_0(7 );
581 IO8 <= observation_vector_0(8 );
581 IO8 <= observation_vector_0(8 );
582 IO9 <= observation_vector_0(9 );
582 IO9 <= observation_vector_0(9 );
583 IO10 <= observation_vector_0(10);
583 IO10 <= observation_vector_0(10);
584 IO11 <= observation_vector_0(11);
584 IO11 <= observation_vector_0(11);
585 WHEN "100" =>
585 WHEN "100" =>
586 IO0 <= observation_vector_1(0 );
586 IO0 <= observation_vector_1(0 );
587 IO1 <= observation_vector_1(1 );
587 IO1 <= observation_vector_1(1 );
588 IO2 <= observation_vector_1(2 );
588 IO2 <= observation_vector_1(2 );
589 IO3 <= observation_vector_1(3 );
589 IO3 <= observation_vector_1(3 );
590 IO4 <= observation_vector_1(4 );
590 IO4 <= observation_vector_1(4 );
591 IO5 <= observation_vector_1(5 );
591 IO5 <= observation_vector_1(5 );
592 IO6 <= observation_vector_1(6 );
592 IO6 <= observation_vector_1(6 );
593 IO7 <= observation_vector_1(7 );
593 IO7 <= observation_vector_1(7 );
594 IO8 <= observation_vector_1(8 );
594 IO8 <= observation_vector_1(8 );
595 IO9 <= observation_vector_1(9 );
595 IO9 <= observation_vector_1(9 );
596 IO10 <= observation_vector_1(10);
596 IO10 <= observation_vector_1(10);
597 IO11 <= observation_vector_1(11);
597 IO11 <= observation_vector_1(11);
598 WHEN OTHERS => NULL;
598 WHEN OTHERS => NULL;
599 END CASE;
599 END CASE;
600
600
601 END IF;
601 END IF;
602 END PROCESS;
602 END PROCESS;
603
603
604 END beh;
604 END beh;
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@@ -1,748 +1,748
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
67
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
69
70 --debug
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
79
80 ---- debug FIFO_IN
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
89
90 ----debug FIFO OUT
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
99
100 ----debug DMA IN
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 );
109 );
110 END lpp_lfr;
110 END lpp_lfr;
111
111
112 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 --
115 --
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
120 --
120 --
121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 --
124 --
125 SIGNAL sample_f0_val : STD_LOGIC;
125 SIGNAL sample_f0_val : STD_LOGIC;
126 SIGNAL sample_f1_val : STD_LOGIC;
126 SIGNAL sample_f1_val : STD_LOGIC;
127 SIGNAL sample_f2_val : STD_LOGIC;
127 SIGNAL sample_f2_val : STD_LOGIC;
128 SIGNAL sample_f3_val : STD_LOGIC;
128 SIGNAL sample_f3_val : STD_LOGIC;
129 --
129 --
130 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
134 --
134 --
135 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
135 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
138
138
139 -- SM
139 -- SM
140 SIGNAL ready_matrix_f0 : STD_LOGIC;
140 SIGNAL ready_matrix_f0 : STD_LOGIC;
141 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
141 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL ready_matrix_f1 : STD_LOGIC;
142 SIGNAL ready_matrix_f1 : STD_LOGIC;
143 SIGNAL ready_matrix_f2 : STD_LOGIC;
143 SIGNAL ready_matrix_f2 : STD_LOGIC;
144 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
144 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
145 SIGNAL error_bad_component_error : STD_LOGIC;
145 SIGNAL error_bad_component_error : STD_LOGIC;
146 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
147 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
151 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
151 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
152 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
152 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
153 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
153 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
154 SIGNAL config_active_interruption_onError : STD_LOGIC;
154 SIGNAL config_active_interruption_onError : STD_LOGIC;
155 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159
159
160 -- WFP
160 -- WFP
161 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
167 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
167 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
168 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
170
170
171 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
171 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
172 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
172 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
174 SIGNAL enable_f0 : STD_LOGIC;
174 SIGNAL enable_f0 : STD_LOGIC;
175 SIGNAL enable_f1 : STD_LOGIC;
175 SIGNAL enable_f1 : STD_LOGIC;
176 SIGNAL enable_f2 : STD_LOGIC;
176 SIGNAL enable_f2 : STD_LOGIC;
177 SIGNAL enable_f3 : STD_LOGIC;
177 SIGNAL enable_f3 : STD_LOGIC;
178 SIGNAL burst_f0 : STD_LOGIC;
178 SIGNAL burst_f0 : STD_LOGIC;
179 SIGNAL burst_f1 : STD_LOGIC;
179 SIGNAL burst_f1 : STD_LOGIC;
180 SIGNAL burst_f2 : STD_LOGIC;
180 SIGNAL burst_f2 : STD_LOGIC;
181 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
185
185
186 SIGNAL run : STD_LOGIC;
186 SIGNAL run : STD_LOGIC;
187 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
187 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
188
188
189 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 SIGNAL data_f0_data_out_valid : STD_LOGIC;
191 SIGNAL data_f0_data_out_valid : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
193 SIGNAL data_f0_data_out_ren : STD_LOGIC;
193 SIGNAL data_f0_data_out_ren : STD_LOGIC;
194 --f1
194 --f1
195 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL data_f1_data_out_valid : STD_LOGIC;
197 SIGNAL data_f1_data_out_valid : STD_LOGIC;
198 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
198 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
199 SIGNAL data_f1_data_out_ren : STD_LOGIC;
199 SIGNAL data_f1_data_out_ren : STD_LOGIC;
200 --f2
200 --f2
201 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f2_data_out_valid : STD_LOGIC;
203 SIGNAL data_f2_data_out_valid : STD_LOGIC;
204 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
204 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
205 SIGNAL data_f2_data_out_ren : STD_LOGIC;
205 SIGNAL data_f2_data_out_ren : STD_LOGIC;
206 --f3
206 --f3
207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
211 SIGNAL data_f3_data_out_ren : STD_LOGIC;
211 SIGNAL data_f3_data_out_ren : STD_LOGIC;
212
212
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214 --
214 --
215 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
216 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
219 --f1
219 --f1
220 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
223 --f2
223 --f2
224 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
227 --f3
227 --f3
228 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
229 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
230 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
230 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
231
231
232 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
233 -- DMA RR
233 -- DMA RR
234 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
235 SIGNAL dma_sel_valid : STD_LOGIC;
235 SIGNAL dma_sel_valid : STD_LOGIC;
236 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
240
240
241 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
241 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
243
243
244 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
245 -- DMA_REG
245 -- DMA_REG
246 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
247 SIGNAL ongoing_reg : STD_LOGIC;
247 SIGNAL ongoing_reg : STD_LOGIC;
248 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
248 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
249 SIGNAL dma_send_reg : STD_LOGIC;
249 SIGNAL dma_send_reg : STD_LOGIC;
250 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
250 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
251 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
253
253
254
254
255 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
256 -- DMA
256 -- DMA
257 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
258 SIGNAL dma_send : STD_LOGIC;
258 SIGNAL dma_send : STD_LOGIC;
259 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
259 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
260 SIGNAL dma_done : STD_LOGIC;
260 SIGNAL dma_done : STD_LOGIC;
261 SIGNAL dma_ren : STD_LOGIC;
261 SIGNAL dma_ren : STD_LOGIC;
262 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265
265
266 -----------------------------------------------------------------------------
266 -----------------------------------------------------------------------------
267 -- MS
267 -- MS
268 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
269
269
270 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL data_ms_valid : STD_LOGIC;
272 SIGNAL data_ms_valid : STD_LOGIC;
273 SIGNAL data_ms_valid_burst : STD_LOGIC;
273 SIGNAL data_ms_valid_burst : STD_LOGIC;
274 SIGNAL data_ms_ren : STD_LOGIC;
274 SIGNAL data_ms_ren : STD_LOGIC;
275 SIGNAL data_ms_done : STD_LOGIC;
275 SIGNAL data_ms_done : STD_LOGIC;
276 SIGNAL dma_ms_ongoing : STD_LOGIC;
276 SIGNAL dma_ms_ongoing : STD_LOGIC;
277
277
278 SIGNAL run_ms : STD_LOGIC;
278 SIGNAL run_ms : STD_LOGIC;
279 SIGNAL ms_softandhard_rstn : STD_LOGIC;
279 SIGNAL ms_softandhard_rstn : STD_LOGIC;
280
280
281 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
281 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
285
285
286
286
287 SIGNAL error_buffer_full : STD_LOGIC;
287 SIGNAL error_buffer_full : STD_LOGIC;
288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
289
289
290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
292
292
293 BEGIN
293 BEGIN
294
294
295 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
295 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
296 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
296 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
297
297
298 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
298 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
299 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
299 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
300 --END GENERATE all_channel;
300 --END GENERATE all_channel;
301
301
302 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
303 lpp_lfr_filter_1 : lpp_lfr_filter
303 lpp_lfr_filter_1 : lpp_lfr_filter
304 GENERIC MAP (
304 GENERIC MAP (
305 Mem_use => Mem_use)
305 Mem_use => Mem_use)
306 PORT MAP (
306 PORT MAP (
307 sample => sample_s,
307 sample => sample_s,
308 sample_val => sample_val,
308 sample_val => sample_val,
309 clk => clk,
309 clk => clk,
310 rstn => rstn,
310 rstn => rstn,
311 data_shaping_SP0 => data_shaping_SP0,
311 data_shaping_SP0 => data_shaping_SP0,
312 data_shaping_SP1 => data_shaping_SP1,
312 data_shaping_SP1 => data_shaping_SP1,
313 data_shaping_R0 => data_shaping_R0,
313 data_shaping_R0 => data_shaping_R0,
314 data_shaping_R1 => data_shaping_R1,
314 data_shaping_R1 => data_shaping_R1,
315 sample_f0_val => sample_f0_val,
315 sample_f0_val => sample_f0_val,
316 sample_f1_val => sample_f1_val,
316 sample_f1_val => sample_f1_val,
317 sample_f2_val => sample_f2_val,
317 sample_f2_val => sample_f2_val,
318 sample_f3_val => sample_f3_val,
318 sample_f3_val => sample_f3_val,
319 sample_f0_wdata => sample_f0_data,
319 sample_f0_wdata => sample_f0_data,
320 sample_f1_wdata => sample_f1_data,
320 sample_f1_wdata => sample_f1_data,
321 sample_f2_wdata => sample_f2_data,
321 sample_f2_wdata => sample_f2_data,
322 sample_f3_wdata => sample_f3_data);
322 sample_f3_wdata => sample_f3_data);
323
323
324 -----------------------------------------------------------------------------
324 -----------------------------------------------------------------------------
325 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
325 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
326 GENERIC MAP (
326 GENERIC MAP (
327 nb_data_by_buffer_size => nb_data_by_buffer_size,
327 nb_data_by_buffer_size => nb_data_by_buffer_size,
328 nb_word_by_buffer_size => nb_word_by_buffer_size,
328 nb_word_by_buffer_size => nb_word_by_buffer_size,
329 nb_snapshot_param_size => nb_snapshot_param_size,
329 nb_snapshot_param_size => nb_snapshot_param_size,
330 delta_vector_size => delta_vector_size,
330 delta_vector_size => delta_vector_size,
331 delta_vector_size_f0_2 => delta_vector_size_f0_2,
331 delta_vector_size_f0_2 => delta_vector_size_f0_2,
332 pindex => pindex,
332 pindex => pindex,
333 paddr => paddr,
333 paddr => paddr,
334 pmask => pmask,
334 pmask => pmask,
335 pirq_ms => pirq_ms,
335 pirq_ms => pirq_ms,
336 pirq_wfp => pirq_wfp,
336 pirq_wfp => pirq_wfp,
337 top_lfr_version => top_lfr_version)
337 top_lfr_version => top_lfr_version)
338 PORT MAP (
338 PORT MAP (
339 HCLK => clk,
339 HCLK => clk,
340 HRESETn => rstn,
340 HRESETn => rstn,
341 apbi => apbi,
341 apbi => apbi,
342 apbo => apbo,
342 apbo => apbo,
343
343
344 run_ms => run_ms,
344 run_ms => run_ms,
345
345
346 ready_matrix_f0 => ready_matrix_f0,
346 ready_matrix_f0 => ready_matrix_f0,
347 -- ready_matrix_f0_1 => ready_matrix_f0_1,
347 -- ready_matrix_f0_1 => ready_matrix_f0_1,
348 ready_matrix_f1 => ready_matrix_f1,
348 ready_matrix_f1 => ready_matrix_f1,
349 ready_matrix_f2 => ready_matrix_f2,
349 ready_matrix_f2 => ready_matrix_f2,
350 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
350 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
351 error_bad_component_error => error_bad_component_error,
351 error_bad_component_error => error_bad_component_error,
352 error_buffer_full => error_buffer_full, -- TODO
352 error_buffer_full => error_buffer_full, -- TODO
353 error_input_fifo_write => error_input_fifo_write, -- TODO
353 error_input_fifo_write => error_input_fifo_write, -- TODO
354 -- debug_reg => debug_reg,
354 -- debug_reg => debug_reg,
355 status_ready_matrix_f0 => status_ready_matrix_f0,
355 status_ready_matrix_f0 => status_ready_matrix_f0,
356 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
356 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
357 status_ready_matrix_f1 => status_ready_matrix_f1,
357 status_ready_matrix_f1 => status_ready_matrix_f1,
358 status_ready_matrix_f2 => status_ready_matrix_f2,
358 status_ready_matrix_f2 => status_ready_matrix_f2,
359 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
359 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
360 -- status_error_bad_component_error => status_error_bad_component_error,
360 -- status_error_bad_component_error => status_error_bad_component_error,
361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
362 config_active_interruption_onError => config_active_interruption_onError,
362 config_active_interruption_onError => config_active_interruption_onError,
363
363
364 matrix_time_f0 => matrix_time_f0,
364 matrix_time_f0 => matrix_time_f0,
365 -- matrix_time_f0_1 => matrix_time_f0_1,
365 -- matrix_time_f0_1 => matrix_time_f0_1,
366 matrix_time_f1 => matrix_time_f1,
366 matrix_time_f1 => matrix_time_f1,
367 matrix_time_f2 => matrix_time_f2,
367 matrix_time_f2 => matrix_time_f2,
368
368
369 addr_matrix_f0 => addr_matrix_f0,
369 addr_matrix_f0 => addr_matrix_f0,
370 -- addr_matrix_f0_1 => addr_matrix_f0_1,
370 -- addr_matrix_f0_1 => addr_matrix_f0_1,
371 addr_matrix_f1 => addr_matrix_f1,
371 addr_matrix_f1 => addr_matrix_f1,
372 addr_matrix_f2 => addr_matrix_f2,
372 addr_matrix_f2 => addr_matrix_f2,
373 -------------------------------------------------------------------------
373 -------------------------------------------------------------------------
374 status_full => status_full,
374 status_full => status_full,
375 status_full_ack => status_full_ack,
375 status_full_ack => status_full_ack,
376 status_full_err => status_full_err,
376 status_full_err => status_full_err,
377 status_new_err => status_new_err,
377 status_new_err => status_new_err,
378 data_shaping_BW => data_shaping_BW,
378 data_shaping_BW => data_shaping_BW,
379 data_shaping_SP0 => data_shaping_SP0,
379 data_shaping_SP0 => data_shaping_SP0,
380 data_shaping_SP1 => data_shaping_SP1,
380 data_shaping_SP1 => data_shaping_SP1,
381 data_shaping_R0 => data_shaping_R0,
381 data_shaping_R0 => data_shaping_R0,
382 data_shaping_R1 => data_shaping_R1,
382 data_shaping_R1 => data_shaping_R1,
383 delta_snapshot => delta_snapshot,
383 delta_snapshot => delta_snapshot,
384 delta_f0 => delta_f0,
384 delta_f0 => delta_f0,
385 delta_f0_2 => delta_f0_2,
385 delta_f0_2 => delta_f0_2,
386 delta_f1 => delta_f1,
386 delta_f1 => delta_f1,
387 delta_f2 => delta_f2,
387 delta_f2 => delta_f2,
388 nb_data_by_buffer => nb_data_by_buffer,
388 nb_data_by_buffer => nb_data_by_buffer,
389 nb_word_by_buffer => nb_word_by_buffer,
389 nb_word_by_buffer => nb_word_by_buffer,
390 nb_snapshot_param => nb_snapshot_param,
390 nb_snapshot_param => nb_snapshot_param,
391 enable_f0 => enable_f0,
391 enable_f0 => enable_f0,
392 enable_f1 => enable_f1,
392 enable_f1 => enable_f1,
393 enable_f2 => enable_f2,
393 enable_f2 => enable_f2,
394 enable_f3 => enable_f3,
394 enable_f3 => enable_f3,
395 burst_f0 => burst_f0,
395 burst_f0 => burst_f0,
396 burst_f1 => burst_f1,
396 burst_f1 => burst_f1,
397 burst_f2 => burst_f2,
397 burst_f2 => burst_f2,
398 run => run,
398 run => run,
399 addr_data_f0 => addr_data_f0,
399 addr_data_f0 => addr_data_f0,
400 addr_data_f1 => addr_data_f1,
400 addr_data_f1 => addr_data_f1,
401 addr_data_f2 => addr_data_f2,
401 addr_data_f2 => addr_data_f2,
402 addr_data_f3 => addr_data_f3,
402 addr_data_f3 => addr_data_f3,
403 start_date => start_date,
403 start_date => start_date,
404 debug_signal => debug_signal);
404 debug_signal => debug_signal);
405
405
406 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
408 lpp_waveform_1 : lpp_waveform
408 lpp_waveform_1 : lpp_waveform
409 GENERIC MAP (
409 GENERIC MAP (
410 tech => inferred,
410 tech => inferred,
411 data_size => 6*16,
411 data_size => 6*16,
412 nb_data_by_buffer_size => nb_data_by_buffer_size,
412 nb_data_by_buffer_size => nb_data_by_buffer_size,
413 nb_word_by_buffer_size => nb_word_by_buffer_size,
413 nb_word_by_buffer_size => nb_word_by_buffer_size,
414 nb_snapshot_param_size => nb_snapshot_param_size,
414 nb_snapshot_param_size => nb_snapshot_param_size,
415 delta_vector_size => delta_vector_size,
415 delta_vector_size => delta_vector_size,
416 delta_vector_size_f0_2 => delta_vector_size_f0_2
416 delta_vector_size_f0_2 => delta_vector_size_f0_2
417 )
417 )
418 PORT MAP (
418 PORT MAP (
419 clk => clk,
419 clk => clk,
420 rstn => rstn,
420 rstn => rstn,
421
421
422 reg_run => run,
422 reg_run => run,
423 reg_start_date => start_date,
423 reg_start_date => start_date,
424 reg_delta_snapshot => delta_snapshot,
424 reg_delta_snapshot => delta_snapshot,
425 reg_delta_f0 => delta_f0,
425 reg_delta_f0 => delta_f0,
426 reg_delta_f0_2 => delta_f0_2,
426 reg_delta_f0_2 => delta_f0_2,
427 reg_delta_f1 => delta_f1,
427 reg_delta_f1 => delta_f1,
428 reg_delta_f2 => delta_f2,
428 reg_delta_f2 => delta_f2,
429
429
430 enable_f0 => enable_f0,
430 enable_f0 => enable_f0,
431 enable_f1 => enable_f1,
431 enable_f1 => enable_f1,
432 enable_f2 => enable_f2,
432 enable_f2 => enable_f2,
433 enable_f3 => enable_f3,
433 enable_f3 => enable_f3,
434 burst_f0 => burst_f0,
434 burst_f0 => burst_f0,
435 burst_f1 => burst_f1,
435 burst_f1 => burst_f1,
436 burst_f2 => burst_f2,
436 burst_f2 => burst_f2,
437
437
438 nb_data_by_buffer => nb_data_by_buffer,
438 nb_data_by_buffer => nb_data_by_buffer,
439 nb_word_by_buffer => nb_word_by_buffer,
439 nb_word_by_buffer => nb_word_by_buffer,
440 nb_snapshot_param => nb_snapshot_param,
440 nb_snapshot_param => nb_snapshot_param,
441 status_full => status_full,
441 status_full => status_full,
442 status_full_ack => status_full_ack,
442 status_full_ack => status_full_ack,
443 status_full_err => status_full_err,
443 status_full_err => status_full_err,
444 status_new_err => status_new_err,
444 status_new_err => status_new_err,
445
445
446 coarse_time => coarse_time,
446 coarse_time => coarse_time,
447 fine_time => fine_time,
447 fine_time => fine_time,
448
448
449 --f0
449 --f0
450 addr_data_f0 => addr_data_f0,
450 addr_data_f0 => addr_data_f0,
451 data_f0_in_valid => sample_f0_val,
451 data_f0_in_valid => sample_f0_val,
452 data_f0_in => sample_f0_data,
452 data_f0_in => sample_f0_data,
453 --f1
453 --f1
454 addr_data_f1 => addr_data_f1,
454 addr_data_f1 => addr_data_f1,
455 data_f1_in_valid => sample_f1_val,
455 data_f1_in_valid => sample_f1_val,
456 data_f1_in => sample_f1_data,
456 data_f1_in => sample_f1_data,
457 --f2
457 --f2
458 addr_data_f2 => addr_data_f2,
458 addr_data_f2 => addr_data_f2,
459 data_f2_in_valid => sample_f2_val,
459 data_f2_in_valid => sample_f2_val,
460 data_f2_in => sample_f2_data,
460 data_f2_in => sample_f2_data,
461 --f3
461 --f3
462 addr_data_f3 => addr_data_f3,
462 addr_data_f3 => addr_data_f3,
463 data_f3_in_valid => sample_f3_val,
463 data_f3_in_valid => sample_f3_val,
464 data_f3_in => sample_f3_data,
464 data_f3_in => sample_f3_data,
465 -- OUTPUT -- DMA interface
465 -- OUTPUT -- DMA interface
466 --f0
466 --f0
467 data_f0_addr_out => data_f0_addr_out_s,
467 data_f0_addr_out => data_f0_addr_out_s,
468 data_f0_data_out => data_f0_data_out,
468 data_f0_data_out => data_f0_data_out,
469 data_f0_data_out_valid => data_f0_data_out_valid_s,
469 data_f0_data_out_valid => data_f0_data_out_valid_s,
470 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
470 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
471 data_f0_data_out_ren => data_f0_data_out_ren,
471 data_f0_data_out_ren => data_f0_data_out_ren,
472 --f1
472 --f1
473 data_f1_addr_out => data_f1_addr_out_s,
473 data_f1_addr_out => data_f1_addr_out_s,
474 data_f1_data_out => data_f1_data_out,
474 data_f1_data_out => data_f1_data_out,
475 data_f1_data_out_valid => data_f1_data_out_valid_s,
475 data_f1_data_out_valid => data_f1_data_out_valid_s,
476 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
476 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
477 data_f1_data_out_ren => data_f1_data_out_ren,
477 data_f1_data_out_ren => data_f1_data_out_ren,
478 --f2
478 --f2
479 data_f2_addr_out => data_f2_addr_out_s,
479 data_f2_addr_out => data_f2_addr_out_s,
480 data_f2_data_out => data_f2_data_out,
480 data_f2_data_out => data_f2_data_out,
481 data_f2_data_out_valid => data_f2_data_out_valid_s,
481 data_f2_data_out_valid => data_f2_data_out_valid_s,
482 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
482 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
483 data_f2_data_out_ren => data_f2_data_out_ren,
483 data_f2_data_out_ren => data_f2_data_out_ren,
484 --f3
484 --f3
485 data_f3_addr_out => data_f3_addr_out_s,
485 data_f3_addr_out => data_f3_addr_out_s,
486 data_f3_data_out => data_f3_data_out,
486 data_f3_data_out => data_f3_data_out,
487 data_f3_data_out_valid => data_f3_data_out_valid_s,
487 data_f3_data_out_valid => data_f3_data_out_valid_s,
488 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
488 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
489 data_f3_data_out_ren => data_f3_data_out_ren ,
489 data_f3_data_out_ren => data_f3_data_out_ren ,
490
490
491 -------------------------------------------------------------------------
491 -------------------------------------------------------------------------
492 observation_reg => OPEN
492 observation_reg => OPEN
493
493
494 );
494 );
495
495
496
496
497 -----------------------------------------------------------------------------
497 -----------------------------------------------------------------------------
498 -- TEMP
498 -- TEMP
499 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
500
500
501 PROCESS (clk, rstn)
501 PROCESS (clk, rstn)
502 BEGIN -- PROCESS
502 BEGIN -- PROCESS
503 IF rstn = '0' THEN -- asynchronous reset (active low)
503 IF rstn = '0' THEN -- asynchronous reset (active low)
504 data_f0_data_out_valid <= '0';
504 data_f0_data_out_valid <= '0';
505 data_f0_data_out_valid_burst <= '0';
505 data_f0_data_out_valid_burst <= '0';
506 data_f1_data_out_valid <= '0';
506 data_f1_data_out_valid <= '0';
507 data_f1_data_out_valid_burst <= '0';
507 data_f1_data_out_valid_burst <= '0';
508 data_f2_data_out_valid <= '0';
508 data_f2_data_out_valid <= '0';
509 data_f2_data_out_valid_burst <= '0';
509 data_f2_data_out_valid_burst <= '0';
510 data_f3_data_out_valid <= '0';
510 data_f3_data_out_valid <= '0';
511 data_f3_data_out_valid_burst <= '0';
511 data_f3_data_out_valid_burst <= '0';
512 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
512 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
513 data_f0_data_out_valid <= data_f0_data_out_valid_s;
513 data_f0_data_out_valid <= data_f0_data_out_valid_s;
514 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
514 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
515 data_f1_data_out_valid <= data_f1_data_out_valid_s;
515 data_f1_data_out_valid <= data_f1_data_out_valid_s;
516 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
516 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
517 data_f2_data_out_valid <= data_f2_data_out_valid_s;
517 data_f2_data_out_valid <= data_f2_data_out_valid_s;
518 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
518 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
519 data_f3_data_out_valid <= data_f3_data_out_valid_s;
519 data_f3_data_out_valid <= data_f3_data_out_valid_s;
520 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
520 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
521 END IF;
521 END IF;
522 END PROCESS;
522 END PROCESS;
523
523
524 data_f0_addr_out <= data_f0_addr_out_s;
524 data_f0_addr_out <= data_f0_addr_out_s;
525 data_f1_addr_out <= data_f1_addr_out_s;
525 data_f1_addr_out <= data_f1_addr_out_s;
526 data_f2_addr_out <= data_f2_addr_out_s;
526 data_f2_addr_out <= data_f2_addr_out_s;
527 data_f3_addr_out <= data_f3_addr_out_s;
527 data_f3_addr_out <= data_f3_addr_out_s;
528
528
529 -----------------------------------------------------------------------------
529 -----------------------------------------------------------------------------
530 -- RoundRobin Selection For DMA
530 -- RoundRobin Selection For DMA
531 -----------------------------------------------------------------------------
531 -----------------------------------------------------------------------------
532
532
533 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
533 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
534 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
534 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
535 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
535 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
536 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
536 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
537
537
538 RR_Arbiter_4_1 : RR_Arbiter_4
538 RR_Arbiter_4_1 : RR_Arbiter_4
539 PORT MAP (
539 PORT MAP (
540 clk => clk,
540 clk => clk,
541 rstn => rstn,
541 rstn => rstn,
542 in_valid => dma_rr_valid,
542 in_valid => dma_rr_valid,
543 out_grant => dma_rr_grant_s);
543 out_grant => dma_rr_grant_s);
544
544
545 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
545 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
546 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
546 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
547 dma_rr_valid_ms(2) <= '0';
547 dma_rr_valid_ms(2) <= '0';
548 dma_rr_valid_ms(3) <= '0';
548 dma_rr_valid_ms(3) <= '0';
549
549
550 RR_Arbiter_4_2 : RR_Arbiter_4
550 RR_Arbiter_4_2 : RR_Arbiter_4
551 PORT MAP (
551 PORT MAP (
552 clk => clk,
552 clk => clk,
553 rstn => rstn,
553 rstn => rstn,
554 in_valid => dma_rr_valid_ms,
554 in_valid => dma_rr_valid_ms,
555 out_grant => dma_rr_grant_ms);
555 out_grant => dma_rr_grant_ms);
556
556
557 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
557 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
558
558
559
559
560 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
561 -- in : dma_rr_grant
561 -- in : dma_rr_grant
562 -- send
562 -- send
563 -- out : dma_sel
563 -- out : dma_sel
564 -- dma_valid_burst
564 -- dma_valid_burst
565 -- dma_sel_valid
565 -- dma_sel_valid
566 -----------------------------------------------------------------------------
566 -----------------------------------------------------------------------------
567 PROCESS (clk, rstn)
567 PROCESS (clk, rstn)
568 BEGIN -- PROCESS
568 BEGIN -- PROCESS
569 IF rstn = '0' THEN -- asynchronous reset (active low)
569 IF rstn = '0' THEN -- asynchronous reset (active low)
570 dma_sel <= (OTHERS => '0');
570 dma_sel <= (OTHERS => '0');
571 dma_send <= '0';
571 dma_send <= '0';
572 dma_valid_burst <= '0';
572 dma_valid_burst <= '0';
573 data_ms_done <= '0';
573 data_ms_done <= '0';
574 dma_ms_ongoing <= '0';
574 dma_ms_ongoing <= '0';
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
576 IF run = '1' THEN
576 IF run = '1' THEN
577 data_ms_done <= '0';
577 data_ms_done <= '0';
578 IF dma_sel = "00000" OR dma_done = '1' THEN
578 IF dma_sel = "00000" OR dma_done = '1' THEN
579 dma_sel <= dma_rr_grant;
579 dma_sel <= dma_rr_grant;
580 IF dma_rr_grant(0) = '1' THEN
580 IF dma_rr_grant(0) = '1' THEN
581 dma_ms_ongoing <= '0';
581 dma_ms_ongoing <= '0';
582 dma_send <= '1';
582 dma_send <= '1';
583 dma_valid_burst <= data_f0_data_out_valid_burst;
583 dma_valid_burst <= data_f0_data_out_valid_burst;
584 dma_sel_valid <= data_f0_data_out_valid;
584 dma_sel_valid <= data_f0_data_out_valid;
585 ELSIF dma_rr_grant(1) = '1' THEN
585 ELSIF dma_rr_grant(1) = '1' THEN
586 dma_ms_ongoing <= '0';
586 dma_ms_ongoing <= '0';
587 dma_send <= '1';
587 dma_send <= '1';
588 dma_valid_burst <= data_f1_data_out_valid_burst;
588 dma_valid_burst <= data_f1_data_out_valid_burst;
589 dma_sel_valid <= data_f1_data_out_valid;
589 dma_sel_valid <= data_f1_data_out_valid;
590 ELSIF dma_rr_grant(2) = '1' THEN
590 ELSIF dma_rr_grant(2) = '1' THEN
591 dma_ms_ongoing <= '0';
591 dma_ms_ongoing <= '0';
592 dma_send <= '1';
592 dma_send <= '1';
593 dma_valid_burst <= data_f2_data_out_valid_burst;
593 dma_valid_burst <= data_f2_data_out_valid_burst;
594 dma_sel_valid <= data_f2_data_out_valid;
594 dma_sel_valid <= data_f2_data_out_valid;
595 ELSIF dma_rr_grant(3) = '1' THEN
595 ELSIF dma_rr_grant(3) = '1' THEN
596 dma_ms_ongoing <= '0';
596 dma_ms_ongoing <= '0';
597 dma_send <= '1';
597 dma_send <= '1';
598 dma_valid_burst <= data_f3_data_out_valid_burst;
598 dma_valid_burst <= data_f3_data_out_valid_burst;
599 dma_sel_valid <= data_f3_data_out_valid;
599 dma_sel_valid <= data_f3_data_out_valid;
600 ELSIF dma_rr_grant(4) = '1' THEN
600 ELSIF dma_rr_grant(4) = '1' THEN
601 dma_ms_ongoing <= '1';
601 dma_ms_ongoing <= '1';
602 dma_send <= '1';
602 dma_send <= '1';
603 dma_valid_burst <= data_ms_valid_burst;
603 dma_valid_burst <= data_ms_valid_burst;
604 dma_sel_valid <= data_ms_valid;
604 dma_sel_valid <= data_ms_valid;
605 --ELSE
605 --ELSE
606 --dma_ms_ongoing <= '0';
606 --dma_ms_ongoing <= '0';
607 END IF;
607 END IF;
608
608
609 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
609 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
610 data_ms_done <= '1';
610 data_ms_done <= '1';
611 END IF;
611 END IF;
612 ELSE
612 ELSE
613 dma_sel <= dma_sel;
613 dma_sel <= dma_sel;
614 dma_send <= '0';
614 dma_send <= '0';
615 END IF;
615 END IF;
616 ELSE
616 ELSE
617 data_ms_done <= '0';
617 data_ms_done <= '0';
618 dma_sel <= (OTHERS => '0');
618 dma_sel <= (OTHERS => '0');
619 dma_send <= '0';
619 dma_send <= '0';
620 dma_valid_burst <= '0';
620 dma_valid_burst <= '0';
621 END IF;
621 END IF;
622 END IF;
622 END IF;
623 END PROCESS;
623 END PROCESS;
624
624
625
625
626 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
626 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
627 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
627 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
628 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
628 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
629 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
629 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
630 data_ms_addr;
630 data_ms_addr;
631
631
632 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
632 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
633 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
633 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
634 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
634 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
635 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
635 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
636 data_ms_data;
636 data_ms_data;
637
637
638 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
638 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
639 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
639 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
640 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
640 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
641 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
641 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
642 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
642 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
643
643
644 dma_data_2 <= dma_data;
644 dma_data_2 <= dma_data;
645
645
646
646
647 -----------------------------------------------------------------------------
647 -----------------------------------------------------------------------------
648 -- DMA
648 -- DMA
649 -----------------------------------------------------------------------------
649 -----------------------------------------------------------------------------
650 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
650 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
651 GENERIC MAP (
651 GENERIC MAP (
652 tech => inferred,
652 tech => inferred,
653 hindex => hindex)
653 hindex => hindex)
654 PORT MAP (
654 PORT MAP (
655 HCLK => clk,
655 HCLK => clk,
656 HRESETn => rstn,
656 HRESETn => rstn,
657 run => run,
657 run => run,
658 AHB_Master_In => ahbi,
658 AHB_Master_In => ahbi,
659 AHB_Master_Out => ahbo,
659 AHB_Master_Out => ahbo,
660
660
661 send => dma_send,
661 send => dma_send,
662 valid_burst => dma_valid_burst,
662 valid_burst => dma_valid_burst,
663 done => dma_done,
663 done => dma_done,
664 ren => dma_ren,
664 ren => dma_ren,
665 address => dma_address,
665 address => dma_address,
666 data => dma_data_2);
666 data => dma_data_2);
667
667
668 -----------------------------------------------------------------------------
668 -----------------------------------------------------------------------------
669 -- Matrix Spectral
669 -- Matrix Spectral
670 -----------------------------------------------------------------------------
670 -----------------------------------------------------------------------------
671 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
671 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
672 NOT(sample_f0_val) & NOT(sample_f0_val);
672 NOT(sample_f0_val) & NOT(sample_f0_val);
673 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
673 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
674 NOT(sample_f1_val) & NOT(sample_f1_val);
674 NOT(sample_f1_val) & NOT(sample_f1_val);
675 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
675 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
676 NOT(sample_f3_val) & NOT(sample_f3_val);
676 NOT(sample_f2_val) & NOT(sample_f2_val);
677
677
678 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
678 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
679 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
679 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
680 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
680 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
681
681
682 -------------------------------------------------------------------------------
682 -------------------------------------------------------------------------------
683
683
684 ms_softandhard_rstn <= rstn AND run_ms AND run;
684 ms_softandhard_rstn <= rstn AND run_ms AND run;
685
685
686 -----------------------------------------------------------------------------
686 -----------------------------------------------------------------------------
687 lpp_lfr_ms_1 : lpp_lfr_ms
687 lpp_lfr_ms_1 : lpp_lfr_ms
688 GENERIC MAP (
688 GENERIC MAP (
689 Mem_use => Mem_use)
689 Mem_use => Mem_use)
690 PORT MAP (
690 PORT MAP (
691 clk => clk,
691 clk => clk,
692 rstn => ms_softandhard_rstn, --rstn,
692 rstn => ms_softandhard_rstn, --rstn,
693
693
694 coarse_time => coarse_time,
694 coarse_time => coarse_time,
695 fine_time => fine_time,
695 fine_time => fine_time,
696
696
697 sample_f0_wen => sample_f0_wen,
697 sample_f0_wen => sample_f0_wen,
698 sample_f0_wdata => sample_f0_wdata,
698 sample_f0_wdata => sample_f0_wdata,
699 sample_f1_wen => sample_f1_wen,
699 sample_f1_wen => sample_f1_wen,
700 sample_f1_wdata => sample_f1_wdata,
700 sample_f1_wdata => sample_f1_wdata,
701 sample_f2_wen => sample_f2_wen, -- TODO
701 sample_f2_wen => sample_f2_wen, -- TODO
702 sample_f2_wdata => sample_f2_wdata,-- TODO
702 sample_f2_wdata => sample_f2_wdata,-- TODO
703
703
704 dma_addr => data_ms_addr, --
704 dma_addr => data_ms_addr, --
705 dma_data => data_ms_data, --
705 dma_data => data_ms_data, --
706 dma_valid => data_ms_valid, --
706 dma_valid => data_ms_valid, --
707 dma_valid_burst => data_ms_valid_burst, --
707 dma_valid_burst => data_ms_valid_burst, --
708 dma_ren => data_ms_ren, --
708 dma_ren => data_ms_ren, --
709 dma_done => data_ms_done, --
709 dma_done => data_ms_done, --
710
710
711 ready_matrix_f0 => ready_matrix_f0,
711 ready_matrix_f0 => ready_matrix_f0,
712 ready_matrix_f1 => ready_matrix_f1,
712 ready_matrix_f1 => ready_matrix_f1,
713 ready_matrix_f2 => ready_matrix_f2,
713 ready_matrix_f2 => ready_matrix_f2,
714 error_bad_component_error => error_bad_component_error,
714 error_bad_component_error => error_bad_component_error,
715 error_buffer_full => error_buffer_full,
715 error_buffer_full => error_buffer_full,
716 error_input_fifo_write => error_input_fifo_write,
716 error_input_fifo_write => error_input_fifo_write,
717
717
718 debug_reg => debug_ms,--observation_reg,
718 debug_reg => debug_ms,--observation_reg,
719 observation_vector_0 => observation_vector_0,
719 observation_vector_0 => observation_vector_0,
720 observation_vector_1 => observation_vector_1,
720 observation_vector_1 => observation_vector_1,
721
721
722 status_ready_matrix_f0 => status_ready_matrix_f0,
722 status_ready_matrix_f0 => status_ready_matrix_f0,
723 status_ready_matrix_f1 => status_ready_matrix_f1,
723 status_ready_matrix_f1 => status_ready_matrix_f1,
724 status_ready_matrix_f2 => status_ready_matrix_f2,
724 status_ready_matrix_f2 => status_ready_matrix_f2,
725 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
725 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
726 config_active_interruption_onError => config_active_interruption_onError,
726 config_active_interruption_onError => config_active_interruption_onError,
727 addr_matrix_f0 => addr_matrix_f0,
727 addr_matrix_f0 => addr_matrix_f0,
728 addr_matrix_f1 => addr_matrix_f1,
728 addr_matrix_f1 => addr_matrix_f1,
729 addr_matrix_f2 => addr_matrix_f2,
729 addr_matrix_f2 => addr_matrix_f2,
730
730
731 matrix_time_f0 => matrix_time_f0,
731 matrix_time_f0 => matrix_time_f0,
732 matrix_time_f1 => matrix_time_f1,
732 matrix_time_f1 => matrix_time_f1,
733 matrix_time_f2 => matrix_time_f2);
733 matrix_time_f2 => matrix_time_f2);
734
734
735 -----------------------------------------------------------------------------
735 -----------------------------------------------------------------------------
736
736
737
737
738 observation_reg(31 DOWNTO 0) <=
738 observation_reg(31 DOWNTO 0) <=
739 dma_sel(4) & -- 31
739 dma_sel(4) & -- 31
740 dma_ms_ongoing & -- 30
740 dma_ms_ongoing & -- 30
741 data_ms_done & -- 29
741 data_ms_done & -- 29
742 dma_done & -- 28
742 dma_done & -- 28
743 ms_softandhard_rstn & --27
743 ms_softandhard_rstn & --27
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
747
747
748 END beh;
748 END beh; No newline at end of file
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