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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
36
37 ENTITY lpp_top_apbreg IS
38 GENERIC (
39 pindex : INTEGER := 4;
40 paddr : INTEGER := 4;
41 pmask : INTEGER := 16#fff#;
42 pirq : INTEGER := 0);
43 PORT (
44 -- AMBA AHB system signals
45 HCLK : IN STD_ULOGIC;
46 HRESETn : IN STD_ULOGIC;
47
48 -- AMBA APB Slave Interface
49 apbi : IN apb_slv_in_type;
50 apbo : OUT apb_slv_out_type;
51
52 -- IN
53 ready_matrix_f0_0 : IN STD_LOGIC;
54 ready_matrix_f0_1 : IN STD_LOGIC;
55 ready_matrix_f1 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60
61 -- OUT
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
64 status_ready_matrix_f1 : OUT STD_LOGIC;
65 status_ready_matrix_f2 : OUT STD_LOGIC;
66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
67 status_error_bad_component_error : OUT STD_LOGIC;
68
69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
70 config_active_interruption_onError : OUT STD_LOGIC;
71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
75 );
76
77 END lpp_top_apbreg;
78
79 ARCHITECTURE beh OF lpp_top_apbreg IS
80
81 CONSTANT REVISION : INTEGER := 1;
82
83 CONSTANT pconfig : apb_config_type := (
84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
85 1 => apb_iobar(paddr, pmask));
86
87 TYPE lpp_dma_regs IS RECORD
88 config_active_interruption_onNewMatrix : STD_LOGIC;
89 config_active_interruption_onError : STD_LOGIC;
90 status_ready_matrix_f0_0 : STD_LOGIC;
91 status_ready_matrix_f0_1 : STD_LOGIC;
92 status_ready_matrix_f1 : STD_LOGIC;
93 status_ready_matrix_f2 : STD_LOGIC;
94 status_error_anticipating_empty_fifo : STD_LOGIC;
95 status_error_bad_component_error : STD_LOGIC;
96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 END RECORD;
101
102 SIGNAL reg : lpp_dma_regs;
103
104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
105
106 BEGIN -- beh
107
108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
113 status_error_bad_component_error <= reg.status_error_bad_component_error;
114
115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
116 config_active_interruption_onError <= reg.config_active_interruption_onError;
117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
119 addr_matrix_f1 <= reg.addr_matrix_f1;
120 addr_matrix_f2 <= reg.addr_matrix_f2;
121
122 lpp_top_apbreg : PROCESS (HCLK, HRESETn)
123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
124 BEGIN -- PROCESS lpp_dma_top
125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
126 reg.config_active_interruption_onNewMatrix <= '0';
127 reg.config_active_interruption_onError <= '0';
128 reg.status_ready_matrix_f0_0 <= '0';
129 reg.status_ready_matrix_f0_1 <= '0';
130 reg.status_ready_matrix_f1 <= '0';
131 reg.status_ready_matrix_f2 <= '0';
132 reg.status_error_anticipating_empty_fifo <= '0';
133 reg.status_error_bad_component_error <= '0';
134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
145
146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
148
149 paddr := "000000";
150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
151 prdata <= (OTHERS => '0');
152 IF apbi.psel(pindex) = '1' THEN
153 -- APB DMA READ --
154 CASE paddr(7 DOWNTO 2) IS
155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
156 prdata(1) <= reg.config_active_interruption_onError;
157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
158 prdata(1) <= reg.status_ready_matrix_f0_1;
159 prdata(2) <= reg.status_ready_matrix_f1;
160 prdata(3) <= reg.status_ready_matrix_f2;
161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
162 prdata(5) <= reg.status_error_bad_component_error;
163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
168 WHEN OTHERS => NULL;
169 END CASE;
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
171 -- APB DMA WRITE --
172 CASE paddr(7 DOWNTO 2) IS
173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
185 WHEN OTHERS => NULL;
186 END CASE;
187 END IF;
188 END IF;
189 END IF;
190 END PROCESS lpp_top_apbreg;
191
192 apbo.pirq <= (OTHERS => '0');
193 apbo.pindex <= pindex;
194 apbo.pconfig <= pconfig;
195 apbo.prdata <= prdata;
196
197
198 END beh;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY grlib;
4 USE grlib.amba.ALL;
5 USE grlib.stdlib.ALL;
6 USE grlib.devices.ALL;
7 USE GRLIB.DMA2AHB_Package.ALL;
8 LIBRARY lpp;
9 USE lpp.lpp_ad_conv.ALL;
10 USE lpp.iir_filter.ALL;
11 USE lpp.FILTERcfg.ALL;
12 USE lpp.lpp_memory.ALL;
13 USE lpp.lpp_top_lfr_pkg.ALL;
14 USE lpp.lpp_dma_pkg.ALL;
15 LIBRARY techmap;
16 USE techmap.gencomp.ALL;
17
18 ENTITY lpp_top_lfr IS
19 GENERIC(
20 tech : INTEGER := 0;
21 hindex_SpectralMatrix : INTEGER := 2;
22 pindex : INTEGER := 4;
23 paddr : INTEGER := 4;
24 pmask : INTEGER := 16#fff#;
25 pirq : INTEGER := 0
26 );
27 PORT (
28 -- ADS7886
29 cnv_run : IN STD_LOGIC;
30 cnv : OUT STD_LOGIC;
31 sck : OUT STD_LOGIC;
32 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
33 --
34 cnv_clk : IN STD_LOGIC; -- 49 MHz
35 cnv_rstn : IN STD_LOGIC;
36 --
37 clk : IN STD_LOGIC; -- 25 MHz
38 rstn : IN STD_LOGIC;
39 --
40 apbi : IN apb_slv_in_type;
41 apbo : OUT apb_slv_out_type;
42
43 -- AMBA AHB Master Interface
44 AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type;
45 AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type
46 );
47 END lpp_top_lfr;
48
49 ARCHITECTURE tb OF lpp_top_lfr IS
50
51 -----------------------------------------------------------------------------
52 -- f0
53 SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
54 SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
55 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
56 --
57 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
59 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 --
62 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
63 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
64 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
65 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
66 -----------------------------------------------------------------------------
67 -- f1
68 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
69 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
70 --
71 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
72 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
73 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
75 -----------------------------------------------------------------------------
76 -- f2
77 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
79 -----------------------------------------------------------------------------
80 -- f3
81 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
83 --
84 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
86 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 -----------------------------------------------------------------------------
89
90 -----------------------------------------------------------------------------
91 -- SPECTRAL MATRIX
92 -----------------------------------------------------------------------------
93 SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 SIGNAL fifo_empty : STD_LOGIC;
95 SIGNAL fifo_ren : STD_LOGIC;
96 SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL header_val : STD_LOGIC;
98 SIGNAL header_ack : STD_LOGIC;
99
100 -----------------------------------------------------------------------------
101 -- APB REG
102 -----------------------------------------------------------------------------
103 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
104 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL ready_matrix_f1 : STD_LOGIC;
106 SIGNAL ready_matrix_f2 : STD_LOGIC;
107 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
108 SIGNAL error_bad_component_error : STD_LOGIC;
109 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
111 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
114 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
115 SIGNAL status_error_bad_component_error : STD_LOGIC;
116 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
117 SIGNAL config_active_interruption_onError : STD_LOGIC;
118 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122
123 BEGIN
124
125 -----------------------------------------------------------------------------
126 -- CNA + FILTER
127 -----------------------------------------------------------------------------
128 lpp_top_acq_1 : lpp_top_acq
129 GENERIC MAP (
130 tech => tech)
131 PORT MAP (
132 cnv_run => cnv_run,
133 cnv => cnv,
134 sck => sck,
135 sdo => sdo,
136 cnv_clk => cnv_clk,
137 cnv_rstn => cnv_rstn,
138 clk => clk,
139 rstn => rstn,
140
141 sample_f0_0_wen => sample_f0_0_wen,
142 sample_f0_1_wen => sample_f0_1_wen,
143 sample_f0_wdata => sample_f0_wdata,
144 sample_f1_wen => sample_f1_wen,
145 sample_f1_wdata => sample_f1_wdata,
146 sample_f2_wen => sample_f2_wen,
147 sample_f2_wdata => sample_f2_wdata,
148 sample_f3_wen => sample_f3_wen,
149 sample_f3_wdata => sample_f3_wdata);
150
151 -----------------------------------------------------------------------------
152 -- FIFO
153 -----------------------------------------------------------------------------
154
155 lppFIFO_f0_0 : lppFIFOxN
156 GENERIC MAP (
157 tech => tech,
158 Data_sz => 18,
159 FifoCnt => 5,
160 Enable_ReUse => '0')
161 PORT MAP (
162 rst => rstn,
163 wclk => clk,
164 rclk => clk,
165 ReUse => (OTHERS => '0'),
166
167 wen => sample_f0_0_wen,
168 ren => sample_f0_0_ren,
169 wdata => sample_f0_wdata,
170 rdata => sample_f0_0_rdata,
171 full => sample_f0_0_full,
172 empty => sample_f0_0_empty);
173
174 lppFIFO_f0_1 : lppFIFOxN
175 GENERIC MAP (
176 tech => tech,
177 Data_sz => 18,
178 FifoCnt => 5,
179 Enable_ReUse => '0')
180 PORT MAP (
181 rst => rstn,
182 wclk => clk,
183 rclk => clk,
184 ReUse => (OTHERS => '0'),
185
186 wen => sample_f0_1_wen,
187 ren => sample_f0_1_ren,
188 wdata => sample_f0_wdata,
189 rdata => sample_f0_1_rdata,
190 full => sample_f0_1_full,
191 empty => sample_f0_1_empty);
192
193 lppFIFO_f1 : lppFIFOxN
194 GENERIC MAP (
195 tech => tech,
196 Data_sz => 18,
197 FifoCnt => 5,
198 Enable_ReUse => '0')
199 PORT MAP (
200 rst => rstn,
201 wclk => clk,
202 rclk => clk,
203 ReUse => (OTHERS => '0'),
204
205 wen => sample_f1_wen,
206 ren => sample_f1_ren,
207 wdata => sample_f1_wdata,
208 rdata => sample_f1_rdata,
209 full => sample_f1_full,
210 empty => sample_f1_empty);
211
212 lppFIFO_f3 : lppFIFOxN
213 GENERIC MAP (
214 tech => tech,
215 Data_sz => 18,
216 FifoCnt => 5,
217 Enable_ReUse => '0')
218 PORT MAP (
219 rst => rstn,
220 wclk => clk,
221 rclk => clk,
222 ReUse => (OTHERS => '0'),
223
224 wen => sample_f3_wen,
225 ren => sample_f3_ren,
226 wdata => sample_f3_wdata,
227 rdata => sample_f3_rdata,
228 full => sample_f3_full,
229 empty => sample_f3_empty);
230
231 -----------------------------------------------------------------------------
232 -- SPECTRAL MATRIX
233 -----------------------------------------------------------------------------
234
235 -----------------------------------------------------------------------------
236 -- DMA SPECTRAL MATRIX
237 -----------------------------------------------------------------------------
238 lpp_dma_ip_1 : lpp_dma_ip
239 GENERIC MAP (
240 tech => tech,
241 hindex => hindex_SpectralMatrix)
242 PORT MAP (
243 HCLK => clk,
244 HRESETn => rstn,
245 AHB_Master_In => AHB_DMA_SpectralMatrix_In,
246 AHB_Master_Out => AHB_DMA_SpectralMatrix_Out,
247
248 -- Connect to Spectral Matrix --
249 fifo_data => fifo_data,
250 fifo_empty => fifo_empty,
251 fifo_ren => fifo_ren,
252 header => header,
253 header_val => header_val,
254 header_ack => header_ack,
255
256 -- APB REG
257
258 ready_matrix_f0_0 => ready_matrix_f0_0,
259 ready_matrix_f0_1 => ready_matrix_f0_1,
260 ready_matrix_f1 => ready_matrix_f1,
261 ready_matrix_f2 => ready_matrix_f2,
262 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
263 error_bad_component_error => error_bad_component_error,
264 debug_reg => debug_reg,
265 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
266 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
268 status_ready_matrix_f2 => status_ready_matrix_f2,
269 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
270 status_error_bad_component_error => status_error_bad_component_error,
271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
272 config_active_interruption_onError => config_active_interruption_onError,
273 addr_matrix_f0_0 => addr_matrix_f0_0,
274 addr_matrix_f0_1 => addr_matrix_f0_1,
275 addr_matrix_f1 => addr_matrix_f1,
276 addr_matrix_f2 => addr_matrix_f2);
277
278 lpp_top_apbreg_1 : lpp_top_apbreg
279 GENERIC MAP (
280 pindex => pindex,
281 paddr => paddr,
282 pmask => pmask,
283 pirq => pirq)
284 PORT MAP (
285 HCLK => clk,
286 HRESETn => rstn,
287 apbi => apbi,
288 apbo => apbo,
289
290 ready_matrix_f0_0 => ready_matrix_f0_0,
291 ready_matrix_f0_1 => ready_matrix_f0_1,
292 ready_matrix_f1 => ready_matrix_f1,
293 ready_matrix_f2 => ready_matrix_f2,
294 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
295 error_bad_component_error => error_bad_component_error,
296 debug_reg => debug_reg,
297 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
298 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
299 status_ready_matrix_f1 => status_ready_matrix_f1,
300 status_ready_matrix_f2 => status_ready_matrix_f2,
301 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
302 status_error_bad_component_error => status_error_bad_component_error,
303 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
304 config_active_interruption_onError => config_active_interruption_onError,
305 addr_matrix_f0_0 => addr_matrix_f0_0,
306 addr_matrix_f0_1 => addr_matrix_f0_1,
307 addr_matrix_f1 => addr_matrix_f1,
308 addr_matrix_f2 => addr_matrix_f2);
309
310
311 --TODO : add the irq alert for DMA matrix transfert ending
312 --TODO : add 5 bit register into APB to control the DATA SHIPING
313 --TODO : add Spectral Matrix (FFT + SP)
314 --TODO : add DMA for WaveForms Picker
315 --TODO : add APB Reg to control WaveForms Picker
316 --TODO : add WaveForms Picker
317
318 END tb;
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@@ -4,7 +4,6 BOARDSDIR=boards/
4 DESIGNSDIR=designs/
4 DESIGNSDIR=designs/
5
5
6
6
7
8 .PHONY:doc
7 .PHONY:doc
9
8
10
9
@@ -54,6 +53,7 Patch-GRLIB: init doc
54
53
55 link:
54 link:
56 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
55 sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
56 sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
57
57
58 dist: init
58 dist: init
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
59 tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*
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@@ -30,9 +30,10 vcom -quiet -93 -work lpp ../../lib/lpp/
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
32
32
33
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
34
34
35 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36
37
37 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
@@ -41,8 +42,8 vcom -quiet -93 -work lpp ../../lib/lpp/
41 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43
44
44 vsim work.TB_Data_Acquisition
45 #vsim work.TB_Data_Acquisition
45
46
46 log -r *
47 #log -r *
47 do wave_data_acquisition.do
48 #do wave_data_acquisition.do
48 run 5 ms No newline at end of file
49 #run 5 ms No newline at end of file
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@@ -104,14 +104,10 BEGIN
104 -- LPP DMA IP
104 -- LPP DMA IP
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106
106
107 lpp_dma_ip_1: ENTITY work.lpp_dma_ip
107 lpp_dma_ip_1: lpp_dma_ip
108 GENERIC MAP (
108 GENERIC MAP (
109 tech => tech,
109 tech => tech,
110 hindex => hindex,
110 hindex => hindex)
111 pindex => pindex,
112 paddr => paddr,
113 pmask => pmask,
114 pirq => pirq)
115 PORT MAP (
111 PORT MAP (
116 HCLK => HCLK,
112 HCLK => HCLK,
117 HRESETn => HRESETn,
113 HRESETn => HRESETn,
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@@ -45,11 +45,8 USE techmap.gencomp.ALL;
45 ENTITY lpp_dma_ip IS
45 ENTITY lpp_dma_ip IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2;
48 hindex : INTEGER := 2
49 pindex : INTEGER := 4;
49 );
50 paddr : INTEGER := 4;
51 pmask : INTEGER := 16#fff#;
52 pirq : INTEGER := 0);
53 PORT (
50 PORT (
54 -- AMBA AHB system signals
51 -- AMBA AHB system signals
55 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
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@@ -164,11 +164,7 PACKAGE lpp_dma_pkg IS
164 COMPONENT lpp_dma_ip
164 COMPONENT lpp_dma_ip
165 GENERIC (
165 GENERIC (
166 tech : INTEGER;
166 tech : INTEGER;
167 hindex : INTEGER;
167 hindex : INTEGER);
168 pindex : INTEGER;
169 paddr : INTEGER;
170 pmask : INTEGER;
171 pirq : INTEGER);
172 PORT (
168 PORT (
173 HCLK : IN STD_ULOGIC;
169 HCLK : IN STD_ULOGIC;
174 HRESETn : IN STD_ULOGIC;
170 HRESETn : IN STD_ULOGIC;
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@@ -20,10 +20,10 ENTITY lpp_top_acq IS
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC;
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC;
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -72,16 +72,14 ARCHITECTURE tb OF lpp_top_acq IS
72 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
73 CONSTANT Cels_count : INTEGER := 5;
74
74
75 -- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
76 SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 -- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
77 --
80 SIGNAL sample_filter_JC_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 --
80 --
83 SIGNAL sample_filter_JC_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
84 SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 -----------------------------------------------------------------------------
83 -----------------------------------------------------------------------------
86 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
87 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out_val : STD_LOGIC;
@@ -145,27 +143,7 BEGIN
145 sample_filter_in(i, 17) <= sample(i)(15);
143 sample_filter_in(i, 17) <= sample(i)(15);
146 END GENERATE;
144 END GENERATE;
147
145
148 -- coefs <= CoefsInitValCst;
146 coefs_v2 <= CoefsInitValCst_v2;
149 coefs_JC <= CoefsInitValCst_JC;
150
151 --FILTER : IIR_CEL_CTRLR
152 -- GENERIC MAP (
153 -- tech => 0,
154 -- Sample_SZ => 18,
155 -- ChanelsCount => ChanelCount,
156 -- Coef_SZ => Coef_SZ,
157 -- CoefCntPerCel => CoefCntPerCel,
158 -- Cels_count => Cels_count,
159 -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis
160 -- PORT MAP (
161 -- reset => rstn,
162 -- clk => clk,
163 -- sample_clk => sample_val_delay,
164 -- sample_in => sample_filter_in,
165 -- sample_out => sample_filter_out,
166 -- virg_pos => 7,
167 -- GOtest => OPEN,
168 -- coefs => coefs);
169
147
170 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
148 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
171 GENERIC MAP (
149 GENERIC MAP (
@@ -181,26 +159,26 BEGIN
181 rstn => rstn,
159 rstn => rstn,
182 clk => clk,
160 clk => clk,
183 virg_pos => 7,
161 virg_pos => 7,
184 coefs => coefs_JC,
162 coefs => coefs_v2,
185 sample_in_val => sample_val_delay,
163 sample_in_val => sample_val_delay,
186 sample_in => sample_filter_in,
164 sample_in => sample_filter_in,
187 sample_out_val => sample_filter_JC_out_val,
165 sample_out_val => sample_filter_v2_out_val,
188 sample_out => sample_filter_JC_out);
166 sample_out => sample_filter_v2_out);
189
167
190 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
191 PROCESS (clk, rstn)
169 PROCESS (clk, rstn)
192 BEGIN -- PROCESS
170 BEGIN -- PROCESS
193 IF rstn = '0' THEN -- asynchronous reset (active low)
171 IF rstn = '0' THEN -- asynchronous reset (active low)
194 sample_filter_JC_out_r_val <= '0';
172 sample_filter_v2_out_r_val <= '0';
195 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
173 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
196 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
174 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
197 sample_filter_JC_out_r(I, J) <= '0';
175 sample_filter_v2_out_r(I, J) <= '0';
198 END LOOP rst_all_bits;
176 END LOOP rst_all_bits;
199 END LOOP rst_all_chanel;
177 END LOOP rst_all_chanel;
200 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
178 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
201 sample_filter_JC_out_r_val <= sample_filter_JC_out_val;
179 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
202 IF sample_filter_JC_out_val = '1' THEN
180 IF sample_filter_v2_out_val = '1' THEN
203 sample_filter_JC_out_r <= sample_filter_JC_out;
181 sample_filter_v2_out_r <= sample_filter_v2_out;
204 END IF;
182 END IF;
205 END IF;
183 END IF;
206 END PROCESS;
184 END PROCESS;
@@ -216,8 +194,8 BEGIN
216 PORT MAP (
194 PORT MAP (
217 clk => clk,
195 clk => clk,
218 rstn => rstn,
196 rstn => rstn,
219 sample_in_val => sample_filter_JC_out_val ,
197 sample_in_val => sample_filter_v2_out_val ,
220 sample_in => sample_filter_JC_out,
198 sample_in => sample_filter_v2_out,
221 sample_out_val => sample_f0_val,
199 sample_out_val => sample_f0_val,
222 sample_out => sample_f0);
200 sample_out => sample_f0);
223
201
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@@ -33,4 +33,36 PACKAGE lpp_top_lfr_pkg IS
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
33 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0));
34 END COMPONENT;
34 END COMPONENT;
35
35
36 COMPONENT lpp_top_apbreg
37 GENERIC (
38 pindex : INTEGER;
39 paddr : INTEGER;
40 pmask : INTEGER;
41 pirq : INTEGER);
42 PORT (
43 HCLK : IN STD_ULOGIC;
44 HRESETn : IN STD_ULOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 ready_matrix_f0_0 : IN STD_LOGIC;
48 ready_matrix_f0_1 : IN STD_LOGIC;
49 ready_matrix_f1 : IN STD_LOGIC;
50 ready_matrix_f2 : IN STD_LOGIC;
51 error_anticipating_empty_fifo : IN STD_LOGIC;
52 error_bad_component_error : IN STD_LOGIC;
53 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 status_ready_matrix_f0_0 : OUT STD_LOGIC;
55 status_ready_matrix_f0_1 : OUT STD_LOGIC;
56 status_ready_matrix_f1 : OUT STD_LOGIC;
57 status_ready_matrix_f2 : OUT STD_LOGIC;
58 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
59 status_error_bad_component_error : OUT STD_LOGIC;
60 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
61 config_active_interruption_onError : OUT STD_LOGIC;
62 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
66 END COMPONENT;
67
36 END lpp_top_lfr_pkg;
68 END lpp_top_lfr_pkg;
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@@ -1,2 +1,3
1 lpp_top_lfr_pkg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_top_acq.vhd
2 lpp_top_acq.vhd
3 lpp_top_lfr.vhd
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