# HG changeset patch # User pellion # Date 2013-04-16 07:53:51 # Node ID d4d9fbeeb9e380e38a5c1546971c003a53ec70b5 # Parent 37aad32f0ae909ca27d614b8e225f9b8d7a2bb0c temp diff --git a/Makefile b/Makefile --- a/Makefile +++ b/Makefile @@ -1,80 +1,80 @@ -SCRIPTSDIR=scripts/ -LIBDIR=lib/ -BOARDSDIR=boards/ -DESIGNSDIR=designs/ - - - -.PHONY:doc - - -all: help - -help: - @echo - @echo " batch targets:" - @echo - @echo " make link : link lpp library to GRLIB at : $(GRLIB)" - @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)" - @echo " make dist : create a tar file for using into an other computer" - @echo " make Patched-dist : create a tar file for with a patched grlib for using" - @echo " into an other computer" - @echo " make allGPL : add a GPL HEADER in all vhdl Files" - @echo " make init : add a GPL HEADER in all vhdl Files, init all files" - @echo " make doc : make documentation for VHDL IPs" - @echo " make pdf : make pdf documentation for VHDL IPs" - @echo " make C-libs : make C drivers for APB devices" - @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes" - @echo - - - -allGPL: - @echo "Scanning VHDL files ..." - sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib - @echo "Scanning C files ..." - sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers - @echo "Scanning H files ..." - sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers - -init: C-libs - sh $(SCRIPTSDIR)/vhdlsynPatcher.sh - sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp - -C-libs:APB_devs - make -C LPP_drivers - - -APB_devs: - sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh - - -Patch-GRLIB: init doc - sh $(SCRIPTSDIR)/patch.sh $(GRLIB) - -link: - sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) - -dist: init - tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* - - -Patched-dist: Patch-GRLIB - tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* - - -doc: - mkdir -p doc/html - cp doc/ressources/*.jpg doc/html/ - cp doc/ressources/doxygen.css doc/html/ - make -C lib/lpp doc - make -C LPP_drivers doc - - -pdf: doc - sh $(SCRIPTSDIR)/doc.sh - - - - - +SCRIPTSDIR=scripts/ +LIBDIR=lib/ +BOARDSDIR=boards/ +DESIGNSDIR=designs/ + + +.PHONY:doc + + +all: help + +help: + @echo + @echo " batch targets:" + @echo + @echo " make link : link lpp library to GRLIB at : $(GRLIB)" + @echo " make Patch-GRLIB : install library into GRLIB at : $(GRLIB)" + @echo " make dist : create a tar file for using into an other computer" + @echo " make Patched-dist : create a tar file for with a patched grlib for using" + @echo " into an other computer" + @echo " make allGPL : add a GPL HEADER in all vhdl Files" + @echo " make init : add a GPL HEADER in all vhdl Files, init all files" + @echo " make doc : make documentation for VHDL IPs" + @echo " make pdf : make pdf documentation for VHDL IPs" + @echo " make C-libs : make C drivers for APB devices" + @echo " binary files availiable on VHD_Lib/LPP_DRIVERS/lib ./includes" + @echo + + + +allGPL: + @echo "Scanning VHDL files ..." + sh $(SCRIPTSDIR)/GPL_Patcher.sh -R vhd lib + @echo "Scanning C files ..." + sh $(SCRIPTSDIR)/GPL_Patcher.sh -R c LPP_drivers + @echo "Scanning H files ..." + sh $(SCRIPTSDIR)/GPL_Patcher.sh -R h LPP_drivers + +init: C-libs + sh $(SCRIPTSDIR)/vhdlsynPatcher.sh + sh $(SCRIPTSDIR)/makeDirs.sh lib/lpp + +C-libs:APB_devs + make -C LPP_drivers + + +APB_devs: + sh $(SCRIPTSDIR)/APB_DEV_UPDATER.sh + + +Patch-GRLIB: init doc + sh $(SCRIPTSDIR)/patch.sh $(GRLIB) + +link: + sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB) + sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB) + +dist: init + tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/* + + +Patched-dist: Patch-GRLIB + tar -cvzf ./../lpp-patched-GRLIB.tgz $(GRLIB)/* + + +doc: + mkdir -p doc/html + cp doc/ressources/*.jpg doc/html/ + cp doc/ressources/doxygen.css doc/html/ + make -C lib/lpp doc + make -C LPP_drivers doc + + +pdf: doc + sh $(SCRIPTSDIR)/doc.sh + + + + + diff --git a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do --- a/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do +++ b/designs/Projet-LeonLFR-A3P3K-Sheldon_sim-all/run_sim_data_acquisition.do @@ -30,9 +30,10 @@ vcom -quiet -93 -work lpp ../../lib/lpp/ vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd - +vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd -vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd @@ -41,8 +42,8 @@ vcom -quiet -93 -work lpp ../../lib/lpp/ vcom -quiet -93 -work work Top_Data_Acquisition.vhd vcom -quiet -93 -work work TB_Data_Acquisition.vhd -vsim work.TB_Data_Acquisition +#vsim work.TB_Data_Acquisition -log -r * -do wave_data_acquisition.do -run 5 ms \ No newline at end of file +#log -r * +#do wave_data_acquisition.do +#run 5 ms \ No newline at end of file diff --git a/lib/lpp/lpp_dma/lpp_dma.vhd b/lib/lpp/lpp_dma/lpp_dma.vhd --- a/lib/lpp/lpp_dma/lpp_dma.vhd +++ b/lib/lpp/lpp_dma/lpp_dma.vhd @@ -104,14 +104,10 @@ BEGIN -- LPP DMA IP ----------------------------------------------------------------------------- - lpp_dma_ip_1: ENTITY work.lpp_dma_ip + lpp_dma_ip_1: lpp_dma_ip GENERIC MAP ( tech => tech, - hindex => hindex, - pindex => pindex, - paddr => paddr, - pmask => pmask, - pirq => pirq) + hindex => hindex) PORT MAP ( HCLK => HCLK, HRESETn => HRESETn, diff --git a/lib/lpp/lpp_dma/lpp_dma_ip.vhd b/lib/lpp/lpp_dma/lpp_dma_ip.vhd --- a/lib/lpp/lpp_dma/lpp_dma_ip.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_ip.vhd @@ -45,11 +45,8 @@ USE techmap.gencomp.ALL; ENTITY lpp_dma_ip IS GENERIC ( tech : INTEGER := inferred; - hindex : INTEGER := 2; - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#; - pirq : INTEGER := 0); + hindex : INTEGER := 2 + ); PORT ( -- AMBA AHB system signals HCLK : IN STD_ULOGIC; diff --git a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd --- a/lib/lpp/lpp_dma/lpp_dma_pkg.vhd +++ b/lib/lpp/lpp_dma/lpp_dma_pkg.vhd @@ -164,11 +164,7 @@ PACKAGE lpp_dma_pkg IS COMPONENT lpp_dma_ip GENERIC ( tech : INTEGER; - hindex : INTEGER; - pindex : INTEGER; - paddr : INTEGER; - pmask : INTEGER; - pirq : INTEGER); + hindex : INTEGER); PORT ( HCLK : IN STD_ULOGIC; HRESETn : IN STD_ULOGIC; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd @@ -20,10 +20,10 @@ ENTITY lpp_top_acq IS sck : OUT STD_LOGIC; sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- - cnv_clk : IN STD_LOGIC; + cnv_clk : IN STD_LOGIC; -- 49 MHz cnv_rstn : IN STD_LOGIC; -- - clk : IN STD_LOGIC; + clk : IN STD_LOGIC; -- 25 MHz rstn : IN STD_LOGIC; -- sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); @@ -72,16 +72,14 @@ ARCHITECTURE tb OF lpp_top_acq IS CONSTANT CoefPerCel : INTEGER := 5; CONSTANT Cels_count : INTEGER := 5; --- SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0); - SIGNAL coefs_JC : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); + SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0); SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); --- SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); -- - SIGNAL sample_filter_JC_out_val : STD_LOGIC; - SIGNAL sample_filter_JC_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_v2_out_val : STD_LOGIC; + SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); -- - SIGNAL sample_filter_JC_out_r_val : STD_LOGIC; - SIGNAL sample_filter_JC_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); + SIGNAL sample_filter_v2_out_r_val : STD_LOGIC; + SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0); ----------------------------------------------------------------------------- SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL sample_downsampling_out_val : STD_LOGIC; @@ -144,28 +142,8 @@ BEGIN sample_filter_in(i, 16) <= sample(i)(15); sample_filter_in(i, 17) <= sample(i)(15); END GENERATE; - --- coefs <= CoefsInitValCst; - coefs_JC <= CoefsInitValCst_JC; - - --FILTER : IIR_CEL_CTRLR - -- GENERIC MAP ( - -- tech => 0, - -- Sample_SZ => 18, - -- ChanelsCount => ChanelCount, - -- Coef_SZ => Coef_SZ, - -- CoefCntPerCel => CoefCntPerCel, - -- Cels_count => Cels_count, - -- Mem_use => use_CEL) -- use_CEL for SIMU, use_RAM for synthesis - -- PORT MAP ( - -- reset => rstn, - -- clk => clk, - -- sample_clk => sample_val_delay, - -- sample_in => sample_filter_in, - -- sample_out => sample_filter_out, - -- virg_pos => 7, - -- GOtest => OPEN, - -- coefs => coefs); + + coefs_v2 <= CoefsInitValCst_v2; IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2 GENERIC MAP ( @@ -181,26 +159,26 @@ BEGIN rstn => rstn, clk => clk, virg_pos => 7, - coefs => coefs_JC, + coefs => coefs_v2, sample_in_val => sample_val_delay, sample_in => sample_filter_in, - sample_out_val => sample_filter_JC_out_val, - sample_out => sample_filter_JC_out); + sample_out_val => sample_filter_v2_out_val, + sample_out => sample_filter_v2_out); ----------------------------------------------------------------------------- PROCESS (clk, rstn) BEGIN -- PROCESS IF rstn = '0' THEN -- asynchronous reset (active low) - sample_filter_JC_out_r_val <= '0'; + sample_filter_v2_out_r_val <= '0'; rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP - sample_filter_JC_out_r(I, J) <= '0'; + sample_filter_v2_out_r(I, J) <= '0'; END LOOP rst_all_bits; END LOOP rst_all_chanel; ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - sample_filter_JC_out_r_val <= sample_filter_JC_out_val; - IF sample_filter_JC_out_val = '1' THEN - sample_filter_JC_out_r <= sample_filter_JC_out; + sample_filter_v2_out_r_val <= sample_filter_v2_out_val; + IF sample_filter_v2_out_val = '1' THEN + sample_filter_v2_out_r <= sample_filter_v2_out; END IF; END IF; END PROCESS; @@ -216,8 +194,8 @@ BEGIN PORT MAP ( clk => clk, rstn => rstn, - sample_in_val => sample_filter_JC_out_val , - sample_in => sample_filter_JC_out, + sample_in_val => sample_filter_v2_out_val , + sample_in => sample_filter_v2_out, sample_out_val => sample_f0_val, sample_out => sample_f0); diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -0,0 +1,198 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +---------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_top_apbreg IS + GENERIC ( + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq : INTEGER := 0); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + -- IN + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + + -- OUT + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END lpp_top_apbreg; + +ARCHITECTURE beh OF lpp_top_apbreg IS + + CONSTANT REVISION : INTEGER := 1; + + CONSTANT pconfig : apb_config_type := ( + 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq), + 1 => apb_iobar(paddr, pmask)); + + TYPE lpp_dma_regs IS RECORD + config_active_interruption_onNewMatrix : STD_LOGIC; + config_active_interruption_onError : STD_LOGIC; + status_ready_matrix_f0_0 : STD_LOGIC; + status_ready_matrix_f0_1 : STD_LOGIC; + status_ready_matrix_f1 : STD_LOGIC; + status_ready_matrix_f2 : STD_LOGIC; + status_error_anticipating_empty_fifo : STD_LOGIC; + status_error_bad_component_error : STD_LOGIC; + addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + END RECORD; + + SIGNAL reg : lpp_dma_regs; + + SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN -- beh + + status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0; + status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1; + status_ready_matrix_f1 <= reg.status_ready_matrix_f1; + status_ready_matrix_f2 <= reg.status_ready_matrix_f2; + status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo; + status_error_bad_component_error <= reg.status_error_bad_component_error; + + config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix; + config_active_interruption_onError <= reg.config_active_interruption_onError; + addr_matrix_f0_0 <= reg.addr_matrix_f0_0; + addr_matrix_f0_1 <= reg.addr_matrix_f0_1; + addr_matrix_f1 <= reg.addr_matrix_f1; + addr_matrix_f2 <= reg.addr_matrix_f2; + + lpp_top_apbreg : PROCESS (HCLK, HRESETn) + VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); + BEGIN -- PROCESS lpp_dma_top + IF HRESETn = '0' THEN -- asynchronous reset (active low) + reg.config_active_interruption_onNewMatrix <= '0'; + reg.config_active_interruption_onError <= '0'; + reg.status_ready_matrix_f0_0 <= '0'; + reg.status_ready_matrix_f0_1 <= '0'; + reg.status_ready_matrix_f1 <= '0'; + reg.status_ready_matrix_f2 <= '0'; + reg.status_error_anticipating_empty_fifo <= '0'; + reg.status_error_bad_component_error <= '0'; + reg.addr_matrix_f0_0 <= (OTHERS => '0'); + reg.addr_matrix_f0_1 <= (OTHERS => '0'); + reg.addr_matrix_f1 <= (OTHERS => '0'); + reg.addr_matrix_f2 <= (OTHERS => '0'); + prdata <= (OTHERS => '0'); + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + + reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0; + reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1; + reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1; + reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2; + + reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo; + reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error; + + paddr := "000000"; + paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2); + prdata <= (OTHERS => '0'); + IF apbi.psel(pindex) = '1' THEN + -- APB DMA READ -- + CASE paddr(7 DOWNTO 2) IS + WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix; + prdata(1) <= reg.config_active_interruption_onError; + WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0; + prdata(1) <= reg.status_ready_matrix_f0_1; + prdata(2) <= reg.status_ready_matrix_f1; + prdata(3) <= reg.status_ready_matrix_f2; + prdata(4) <= reg.status_error_anticipating_empty_fifo; + prdata(5) <= reg.status_error_bad_component_error; + WHEN "000010" => prdata <= reg.addr_matrix_f0_0; + WHEN "000011" => prdata <= reg.addr_matrix_f0_1; + WHEN "000100" => prdata <= reg.addr_matrix_f1; + WHEN "000101" => prdata <= reg.addr_matrix_f2; + WHEN "000110" => prdata <= debug_reg; + WHEN OTHERS => NULL; + END CASE; + IF (apbi.pwrite AND apbi.penable) = '1' THEN + -- APB DMA WRITE -- + CASE paddr(7 DOWNTO 2) IS + WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0); + reg.config_active_interruption_onError <= apbi.pwdata(1); + WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0); + reg.status_ready_matrix_f0_1 <= apbi.pwdata(1); + reg.status_ready_matrix_f1 <= apbi.pwdata(2); + reg.status_ready_matrix_f2 <= apbi.pwdata(3); + reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4); + reg.status_error_bad_component_error <= apbi.pwdata(5); + WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata; + WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata; + WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata; + WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata; + WHEN OTHERS => NULL; + END CASE; + END IF; + END IF; + END IF; + END PROCESS lpp_top_apbreg; + + apbo.pirq <= (OTHERS => '0'); + apbo.pindex <= pindex; + apbo.pconfig <= pconfig; + apbo.prdata <= prdata; + + +END beh; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd @@ -0,0 +1,318 @@ +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY lpp_top_lfr IS + GENERIC( + tech : INTEGER := 0; + hindex_SpectralMatrix : INTEGER := 2; + pindex : INTEGER := 4; + paddr : INTEGER := 4; + pmask : INTEGER := 16#fff#; + pirq : INTEGER := 0 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; -- 49 MHz + cnv_rstn : IN STD_LOGIC; + -- + clk : IN STD_LOGIC; -- 25 MHz + rstn : IN STD_LOGIC; + -- + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + -- AMBA AHB Master Interface + AHB_DMA_SpectralMatrix_In : IN AHB_Mst_In_Type; + AHB_DMA_SpectralMatrix_Out : OUT AHB_Mst_Out_Type + ); +END lpp_top_lfr; + +ARCHITECTURE tb OF lpp_top_lfr IS + + ----------------------------------------------------------------------------- + -- f0 + SIGNAL sample_f0_0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + -- + SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + -- + SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + -- f1 + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + -- + SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + -- f2 + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + ----------------------------------------------------------------------------- + -- f3 + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + -- + SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0); + SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0); + SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- SPECTRAL MATRIX + ----------------------------------------------------------------------------- + SIGNAL fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fifo_empty : STD_LOGIC; + SIGNAL fifo_ren : STD_LOGIC; + SIGNAL header : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL header_val : STD_LOGIC; + SIGNAL header_ack : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- APB REG + ----------------------------------------------------------------------------- + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + +BEGIN + + ----------------------------------------------------------------------------- + -- CNA + FILTER + ----------------------------------------------------------------------------- + lpp_top_acq_1 : lpp_top_acq + GENERIC MAP ( + tech => tech) + PORT MAP ( + cnv_run => cnv_run, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + clk => clk, + rstn => rstn, + + sample_f0_0_wen => sample_f0_0_wen, + sample_f0_1_wen => sample_f0_1_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata); + + ----------------------------------------------------------------------------- + -- FIFO + ----------------------------------------------------------------------------- + + lppFIFO_f0_0 : lppFIFOxN + GENERIC MAP ( + tech => tech, + Data_sz => 18, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f0_0_wen, + ren => sample_f0_0_ren, + wdata => sample_f0_wdata, + rdata => sample_f0_0_rdata, + full => sample_f0_0_full, + empty => sample_f0_0_empty); + + lppFIFO_f0_1 : lppFIFOxN + GENERIC MAP ( + tech => tech, + Data_sz => 18, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f0_1_wen, + ren => sample_f0_1_ren, + wdata => sample_f0_wdata, + rdata => sample_f0_1_rdata, + full => sample_f0_1_full, + empty => sample_f0_1_empty); + + lppFIFO_f1 : lppFIFOxN + GENERIC MAP ( + tech => tech, + Data_sz => 18, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f1_wen, + ren => sample_f1_ren, + wdata => sample_f1_wdata, + rdata => sample_f1_rdata, + full => sample_f1_full, + empty => sample_f1_empty); + + lppFIFO_f3 : lppFIFOxN + GENERIC MAP ( + tech => tech, + Data_sz => 18, + FifoCnt => 5, + Enable_ReUse => '0') + PORT MAP ( + rst => rstn, + wclk => clk, + rclk => clk, + ReUse => (OTHERS => '0'), + + wen => sample_f3_wen, + ren => sample_f3_ren, + wdata => sample_f3_wdata, + rdata => sample_f3_rdata, + full => sample_f3_full, + empty => sample_f3_empty); + + ----------------------------------------------------------------------------- + -- SPECTRAL MATRIX + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- DMA SPECTRAL MATRIX + ----------------------------------------------------------------------------- + lpp_dma_ip_1 : lpp_dma_ip + GENERIC MAP ( + tech => tech, + hindex => hindex_SpectralMatrix) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + AHB_Master_In => AHB_DMA_SpectralMatrix_In, + AHB_Master_Out => AHB_DMA_SpectralMatrix_Out, + + -- Connect to Spectral Matrix -- + fifo_data => fifo_data, + fifo_empty => fifo_empty, + fifo_ren => fifo_ren, + header => header, + header_val => header_val, + header_ack => header_ack, + + -- APB REG + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + + lpp_top_apbreg_1 : lpp_top_apbreg + GENERIC MAP ( + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq => pirq) + PORT MAP ( + HCLK => clk, + HRESETn => rstn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2); + + + --TODO : add the irq alert for DMA matrix transfert ending + --TODO : add 5 bit register into APB to control the DATA SHIPING + --TODO : add Spectral Matrix (FFT + SP) + --TODO : add DMA for WaveForms Picker + --TODO : add APB Reg to control WaveForms Picker + --TODO : add WaveForms Picker + +END tb; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd @@ -33,4 +33,36 @@ PACKAGE lpp_top_lfr_pkg IS sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0)); END COMPONENT; + COMPONENT lpp_top_apbreg + GENERIC ( + pindex : INTEGER; + paddr : INTEGER; + pmask : INTEGER; + pirq : INTEGER); + PORT ( + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + ready_matrix_f0_0 : IN STD_LOGIC; + ready_matrix_f0_1 : IN STD_LOGIC; + ready_matrix_f1 : IN STD_LOGIC; + ready_matrix_f2 : IN STD_LOGIC; + error_anticipating_empty_fifo : IN STD_LOGIC; + error_bad_component_error : IN STD_LOGIC; + debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + status_ready_matrix_f0_0 : OUT STD_LOGIC; + status_ready_matrix_f0_1 : OUT STD_LOGIC; + status_ready_matrix_f1 : OUT STD_LOGIC; + status_ready_matrix_f2 : OUT STD_LOGIC; + status_error_anticipating_empty_fifo : OUT STD_LOGIC; + status_error_bad_component_error : OUT STD_LOGIC; + config_active_interruption_onNewMatrix : OUT STD_LOGIC; + config_active_interruption_onError : OUT STD_LOGIC; + addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); + END COMPONENT; + END lpp_top_lfr_pkg; diff --git a/lib/lpp/lpp_top_lfr/vhdlsyn.txt b/lib/lpp/lpp_top_lfr/vhdlsyn.txt --- a/lib/lpp/lpp_top_lfr/vhdlsyn.txt +++ b/lib/lpp/lpp_top_lfr/vhdlsyn.txt @@ -1,2 +1,3 @@ lpp_top_lfr_pkg.vhd lpp_top_acq.vhd +lpp_top_lfr.vhd