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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity ReadFifo_GEN is
27 port(
28 clk,raz : in std_logic; --! Horloge et Reset du composant
29 SYNC : in std_logic;
30 Readn : out std_logic
31 );
32 end entity;
33
34
35 architecture ar_ReadFifo_GEN of ReadFifo_GEN is
36
37 type etat is (eX,e0);
38 signal ect : etat;
39
40 signal SYNC_reg : std_logic;
41
42 begin
43 process(clk,raz)
44 begin
45 if(raz='0')then
46 ect <= eX;
47 Readn <= '1';
48
49 elsif(clk'event and clk='1')then
50 SYNC_reg <= SYNC;
51
52 case ect is
53 when eX =>
54 if (SYNC_reg='0' and SYNC='1') then
55 Readn <= '0';
56 ect <= e0;
57 end if;
58
59 when e0 =>
60 Readn <= '1';
61 ect <= eX;
62
63 end case;
64 end if;
65 end process;
66
67 end architecture; No newline at end of file
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@@ -1,43 +1,43
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 22 #include "lpp_apb_functions.h"
23 #include "apb_fifo_Driver.h"
24 #include <stdio.h>
25
26
27 FIFO_Device* openFIFO(int count)
28 {
29 FIFO_Device* fifo0;
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
31 return fifo0;
32 }
33
23 #include "apb_fifo_Driver.h"
24 #include <stdio.h>
25
26
27 FIFO_Device* openFIFO(int count)
28 {
29 FIFO_Device* fifo0;
30 fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count);
31 return fifo0;
32 }
33
34 34
35 35 int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count)
36 36 {
37 37 int i=0;
38 38 //int poub;
39 39 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
40 while(i<count)
40 while(i<=count)
41 41 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS
42 42 {
43 43 //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);
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@@ -38,13 +38,16 entity APB_DAC is
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 abits : integer := 8);
41 abits : integer := 8;
42 cpt_serial : integer := 6);
42 43 port (
43 44 clk : in std_logic; --! Horloge du composant
44 45 rst : in std_logic; --! Reset general du composant
45 46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 DataIN : in std_logic_vector(15 downto 0);
47 49 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
50 Readn : out std_logic;
48 51 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
49 52 SCLK : out std_logic; --! Horloge systeme du convertisseur
50 53 DATA : out std_logic --! Donn�e num�rique s�rialis�
@@ -63,11 +66,11 constant pconfig : apb_config_type := (
63 66 1 => apb_iobar(paddr, pmask));
64 67
65 68 signal enable : std_logic;
66 signal flag_sd : std_logic;
69 --signal flag_sd : std_logic;
67 70
68 71 type DAC_ctrlr_Reg is record
69 DAC_Cfg : std_logic_vector(1 downto 0);
70 DAC_Data : std_logic_vector(15 downto 0);
72 DAC_Enable : std_logic_vector(0 downto 0);
73 -- DAC_Data : std_logic_vector(15 downto 0);
71 74 end record;
72 75
73 76 signal Rec : DAC_ctrlr_Reg;
@@ -75,17 +78,19 signal Rdata : std_logic_vector(31 d
75 78
76 79 begin
77 80
78 enable <= Rec.DAC_Cfg(0);
79 Rec.DAC_Cfg(1) <= flag_sd;
81 enable <= Rec.DAC_Enable(0);
82 --Rec.DAC_Cfg(1) <= flag_sd;
80 83
81 84 CONV0 : DacDriver
82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
85 generic map(cpt_serial)
86 port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data);
83 87
84 88
85 89 process(rst,clk)
86 90 begin
87 91 if(rst='0')then
88 Rec.DAC_Data <= (others => '0');
92 --Rec.DAC_Data <= (others => '0');
93 Rec.DAC_Enable(0) <= '0';
89 94
90 95 elsif(clk'event and clk='1')then
91 96
@@ -94,9 +99,9 Rec.DAC_Cfg(1) <= flag_sd;
94 99 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
95 100 case apbi.paddr(abits-1 downto 2) is
96 101 when "000000" =>
97 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
98 when "000001" =>
99 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
102 Rec.DAC_Enable(0) <= apbi.pwdata(0);
103 -- when "000001" =>
104 -- Rec.DAC_Data <= apbi.pwdata(15 downto 0);
100 105 when others =>
101 106 null;
102 107 end case;
@@ -106,11 +111,11 Rec.DAC_Cfg(1) <= flag_sd;
106 111 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
107 112 case apbi.paddr(abits-1 downto 2) is
108 113 when "000000" =>
109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
110 Rdata(1 downto 0) <= Rec.DAC_Cfg;
111 when "000001" =>
112 Rdata(31 downto 16) <= X"FD18";
113 Rdata(15 downto 0) <= Rec.DAC_Data;
114 Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00";
115 Rdata(0 downto 0) <= Rec.DAC_Enable;
116 -- when "000001" =>
117 -- Rdata(31 downto 16) <= X"FD18";
118 -- Rdata(15 downto 0) <= Rec.DAC_Data;
114 119 when others =>
115 120 Rdata <= (others => '0');
116 121 end case;
@@ -121,5 +126,5 Rec.DAC_Cfg(1) <= flag_sd;
121 126 end process;
122 127
123 128 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
125 end architecture;
129 Cal_EN <= Rec.DAC_Enable(0);
130 end architecture; No newline at end of file
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@@ -22,20 +22,20
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 use work.Convertisseur_config.all;
26 25 use lpp.lpp_cna.all;
27 26
28 27 --! Programme du Convertisseur Num�rique/Analogique
29 28
30 29 entity DacDriver is
30 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
31 31 port(
32 32 clk : in std_logic; --! Horloge du composant
33 33 rst : in std_logic; --! Reset general du composant
34 34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
35 Data_reg : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
38 Readn : out std_logic;
39 39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 40 );
41 41 end entity;
@@ -46,23 +46,26 end entity;
46 46 architecture ar_DacDriver of DacDriver is
47 47
48 48 signal s_SCLK : std_logic;
49 signal OKAI_send : std_logic;
49 signal s_SYNC : std_logic;
50 50
51 51 begin
52 52
53 53 SystemCLK : Systeme_Clock
54 generic map (nb_serial)
54 generic map (cpt_serial)
55 55 port map (clk,rst,s_SCLK);
56 56
57 57
58 58 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
59 port map (s_SCLK,rst,enable,s_SYNC);
60 60
61 61
62 62 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
63 port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data);
64 64
65 RenGEN : ReadFifo_GEN
66 port map (clk,rst,s_SYNC,Readn);
65 67
66 68 SCLK <= s_SCLK;
69 SYNC <= s_SYNC;
67 70
68 71 end architecture; No newline at end of file
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@@ -29,7 +29,7 entity Gene_SYNC is
29 29 port(
30 30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
32 -- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
33 33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
34 34 );
35 35 end Gene_SYNC;
@@ -46,21 +46,22 begin
46 46 if(raz='0')then
47 47 SYNC <= '0';
48 48 count <= 14;
49 OKAI_send <= '0';
49 -- OKAI_send <= '0';
50 50
51 51 elsif(SCLK' event and SCLK='1')then
52 52 if(enable='1')then
53 53
54 54 if(count=15)then
55 55 SYNC <= '1';
56 count <= count+1;
57 elsif(count=16)then
56 -- count <= count+1;
57 -- elsif(count=16)then
58 58 count <= 0;
59 SYNC <= '0';
60 OKAI_send <= '1';
59 -- SYNC <= '0';
60 -- OKAI_send <= '1';
61 61 else
62 62 count <= count+1;
63 OKAI_send <= '0';
63 SYNC <= '0';
64 -- OKAI_send <= '0';
64 65 end if;
65 66
66 67 end if;
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@@ -31,7 +31,7 entity Serialize is
31 31 sclk : in std_logic; --! Horloge Systeme
32 32 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e
33 33 send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente
34 sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
34 -- sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e
35 35 Data : out std_logic --! Donn�e num�rique s�rialis�
36 36 );
37 37 end Serialize;
@@ -39,7 +39,7 end Serialize;
39 39
40 40 architecture ar_Serialize of Serialize is
41 41
42 type etat is (attente,serialize);
42 type etat is (attente,serialize,reg);
43 43 signal ect : etat;
44 44
45 45 signal vector_int : std_logic_vector(16 downto 0);
@@ -47,6 +47,7 signal vectin_reg : std_logic_vector(1
47 47 signal load : std_logic;
48 48 signal N : integer range 0 to 16;
49 49 signal CPT_ended : std_logic:='0';
50 signal i : std_logic;
50 51
51 52 begin
52 53 process(clk,raz)
@@ -55,7 +56,8 begin
55 56 ect <= attente;
56 57 vectin_reg <= (others=> '0');
57 58 load <= '0';
58 sended <= '1';
59 i <= '1';
60 -- sended <= '1';
59 61
60 62 elsif(clk'event and clk='1')then
61 63 vectin_reg <= vectin;
@@ -63,18 +65,25 begin
63 65 case ect is
64 66 when attente =>
65 67 if (send='1') then
66 sended <= '0';
67 load <= '1';
68 ect <= serialize;
69 else
70 ect <= attente;
68 -- sended <= '0';
69 if(i='1')then
70 i <= '0';
71 ect <= reg;
72 else
73 load <= '1';
74 ect <= serialize;
75 end if;
71 76 end if;
72 77
78 when reg =>
79 load <= '1';
80 ect <= serialize;
81
73 82 when serialize =>
74 83 load <= '0';
75 84 if(CPT_ended='1')then
76 85 ect <= attente;
77 sended <= '1';
86 -- sended <= '1';
78 87 end if;
79 88
80 89 end case;
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@@ -37,13 +37,16 component APB_DAC is
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 abits : integer := 8);
40 abits : integer := 8;
41 cpt_serial : integer := 6);
41 42 port (
42 43 clk : in std_logic;
43 44 rst : in std_logic;
44 45 apbi : in apb_slv_in_type;
45 46 apbo : out apb_slv_out_type;
47 DataIN : in std_logic_vector(15 downto 0);
46 48 Cal_EN : out std_logic;
49 Readn : out std_logic;
47 50 SYNC : out std_logic;
48 51 SCLK : out std_logic;
49 52 DATA : out std_logic
@@ -52,14 +55,15 end component;
52 55
53 56
54 57 component DacDriver is
58 generic(cpt_serial : integer := 6);
55 59 port(
56 60 clk : in std_logic;
57 61 rst : in std_logic;
58 62 enable : in std_logic;
59 Data_C : in std_logic_vector(15 downto 0);
63 Data_reg : in std_logic_vector(15 downto 0);
60 64 SYNC : out std_logic;
61 65 SCLK : out std_logic;
62 flag_sd : out std_logic;
66 Readn : out std_logic;
63 67 Data : out std_logic
64 68 );
65 69 end component;
@@ -74,12 +78,12 end component;
74 78
75 79
76 80 component Gene_SYNC is
77 port(
78 clk,raz : in std_logic;
79 send : in std_logic;
80 Sysclk : in std_logic;
81 OKAI_send : out std_logic;
82 SYNC : out std_logic);
81 port(
82 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
83 enable : in std_logic; --! Autorise ou non l'utilisation du composant
84 -- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
85 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
86 );
83 87 end component;
84 88
85 89
@@ -89,8 +93,16 port(
89 93 sclk : in std_logic;
90 94 vectin : in std_logic_vector(15 downto 0);
91 95 send : in std_logic;
92 sended : out std_logic;
96 -- sended : out std_logic;
93 97 Data : out std_logic);
94 98 end component;
95 99
100 component ReadFifo_GEN is
101 port(
102 clk,raz : in std_logic;
103 SYNC : in std_logic;
104 Readn : out std_logic
105 );
106 end component;
107
96 108 end;
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