# HG changeset patch # User martin # Date 2013-11-25 12:02:33 # Node ID d170a7fb48c0e1e91d0fe393bdd68bafb85ce149 # Parent a30b78481b8afb7dbf1804321b9f8896a518cff6 SVG non working version diff --git a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c --- a/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c +++ b/LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c @@ -1,43 +1,43 @@ -/*------------------------------------------------------------------------------ --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------*/ +/*------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +-----------------------------------------------------------------------------*/ #include "lpp_apb_functions.h" -#include "apb_fifo_Driver.h" -#include - - -FIFO_Device* openFIFO(int count) -{ - FIFO_Device* fifo0; - fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); - return fifo0; -} - +#include "apb_fifo_Driver.h" +#include + + +FIFO_Device* openFIFO(int count) +{ + FIFO_Device* fifo0; + fifo0 = (FIFO_Device*) apbgetdevice(LPP_FIFO_PID,VENDOR_LPP,count); + return fifo0; +} + int FillFifo(FIFO_Device* dev,int ID,int Tbl[],int count) { int i=0; //int poub; //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]); - while(iFIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE full a 0 ALORS { //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]); diff --git a/lib/lpp/lpp_cna/APB_DAC.vhd b/lib/lpp/lpp_cna/APB_DAC.vhd --- a/lib/lpp/lpp_cna/APB_DAC.vhd +++ b/lib/lpp/lpp_cna/APB_DAC.vhd @@ -38,13 +38,16 @@ entity APB_DAC is paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; - abits : integer := 8); + abits : integer := 8; + cpt_serial : integer := 6); port ( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus + DataIN : in std_logic_vector(15 downto 0); Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL + Readn : out std_logic; SYNC : out std_logic; --! Signal de synchronisation du convertisseur SCLK : out std_logic; --! Horloge systeme du convertisseur DATA : out std_logic --! Donn�e num�rique s�rialis� @@ -63,11 +66,11 @@ constant pconfig : apb_config_type := ( 1 => apb_iobar(paddr, pmask)); signal enable : std_logic; -signal flag_sd : std_logic; +--signal flag_sd : std_logic; type DAC_ctrlr_Reg is record - DAC_Cfg : std_logic_vector(1 downto 0); - DAC_Data : std_logic_vector(15 downto 0); + DAC_Enable : std_logic_vector(0 downto 0); +-- DAC_Data : std_logic_vector(15 downto 0); end record; signal Rec : DAC_ctrlr_Reg; @@ -75,17 +78,19 @@ signal Rdata : std_logic_vector(31 d begin -enable <= Rec.DAC_Cfg(0); -Rec.DAC_Cfg(1) <= flag_sd; +enable <= Rec.DAC_Enable(0); +--Rec.DAC_Cfg(1) <= flag_sd; CONV0 : DacDriver - port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); + generic map(cpt_serial) + port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data); process(rst,clk) begin if(rst='0')then - Rec.DAC_Data <= (others => '0'); + --Rec.DAC_Data <= (others => '0'); + Rec.DAC_Enable(0) <= '0'; elsif(clk'event and clk='1')then @@ -94,9 +99,9 @@ Rec.DAC_Cfg(1) <= flag_sd; if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rec.DAC_Cfg(0) <= apbi.pwdata(0); - when "000001" => - Rec.DAC_Data <= apbi.pwdata(15 downto 0); + Rec.DAC_Enable(0) <= apbi.pwdata(0); +-- when "000001" => +-- Rec.DAC_Data <= apbi.pwdata(15 downto 0); when others => null; end case; @@ -106,11 +111,11 @@ Rec.DAC_Cfg(1) <= flag_sd; if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then case apbi.paddr(abits-1 downto 2) is when "000000" => - Rdata(31 downto 2) <= X"ABCDEF5" & "00"; - Rdata(1 downto 0) <= Rec.DAC_Cfg; - when "000001" => - Rdata(31 downto 16) <= X"FD18"; - Rdata(15 downto 0) <= Rec.DAC_Data; + Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00"; + Rdata(0 downto 0) <= Rec.DAC_Enable; + -- when "000001" => + -- Rdata(31 downto 16) <= X"FD18"; + -- Rdata(15 downto 0) <= Rec.DAC_Data; when others => Rdata <= (others => '0'); end case; @@ -121,5 +126,5 @@ Rec.DAC_Cfg(1) <= flag_sd; end process; apbo.prdata <= Rdata when apbi.penable = '1'; -Cal_EN <= enable; -end architecture; +Cal_EN <= Rec.DAC_Enable(0); +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Convertisseur_config.vhd b/lib/lpp/lpp_cna/Convertisseur_config.vhd deleted file mode 100644 --- a/lib/lpp/lpp_cna/Convertisseur_config.vhd +++ /dev/null @@ -1,34 +0,0 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------- --- Author : Martin Morlot --- Mail : martin.morlot@lpp.polytechnique.fr ------------------------------------------------------------------------------- -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.numeric_std.all; - -Package Convertisseur_config is - ---===========================================================| ---============= Fr�quence de s�rialisation ==================| ---===========================================================| -constant Freq_serial : integer := 5_000_000; -constant nb_serial : integer := 30_000_000 / Freq_serial; - -end; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/DacDriver.vhd b/lib/lpp/lpp_cna/DacDriver.vhd --- a/lib/lpp/lpp_cna/DacDriver.vhd +++ b/lib/lpp/lpp_cna/DacDriver.vhd @@ -22,20 +22,20 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Convertisseur_config.all; use lpp.lpp_cna.all; --! Programme du Convertisseur Num�rique/Analogique entity DacDriver is + generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz port( clk : in std_logic; --! Horloge du composant rst : in std_logic; --! Reset general du composant enable : in std_logic; --! Autorise ou non l'utilisation du composant - Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits + Data_reg : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits SYNC : out std_logic; --! Signal de synchronisation du convertisseur SCLK : out std_logic; --! Horloge systeme du convertisseur - flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e + Readn : out std_logic; Data : out std_logic --! Donn�e num�rique s�rialis� ); end entity; @@ -46,23 +46,26 @@ end entity; architecture ar_DacDriver of DacDriver is signal s_SCLK : std_logic; -signal OKAI_send : std_logic; +signal s_SYNC : std_logic; begin SystemCLK : Systeme_Clock - generic map (nb_serial) + generic map (cpt_serial) port map (clk,rst,s_SCLK); Signal_sync : Gene_SYNC - port map (s_SCLK,rst,enable,OKAI_send,SYNC); + port map (s_SCLK,rst,enable,s_SYNC); Serial : serialize - port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data); + port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data); +RenGEN : ReadFifo_GEN + port map (clk,rst,s_SYNC,Readn); SCLK <= s_SCLK; +SYNC <= s_SYNC; end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Gene_SYNC.vhd b/lib/lpp/lpp_cna/Gene_SYNC.vhd --- a/lib/lpp/lpp_cna/Gene_SYNC.vhd +++ b/lib/lpp/lpp_cna/Gene_SYNC.vhd @@ -29,7 +29,7 @@ entity Gene_SYNC is port( SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant enable : in std_logic; --! Autorise ou non l'utilisation du composant - OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e +-- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r� ); end Gene_SYNC; @@ -46,21 +46,22 @@ begin if(raz='0')then SYNC <= '0'; count <= 14; - OKAI_send <= '0'; +-- OKAI_send <= '0'; elsif(SCLK' event and SCLK='1')then if(enable='1')then if(count=15)then SYNC <= '1'; - count <= count+1; - elsif(count=16)then +-- count <= count+1; +-- elsif(count=16)then count <= 0; - SYNC <= '0'; - OKAI_send <= '1'; +-- SYNC <= '0'; +-- OKAI_send <= '1'; else count <= count+1; - OKAI_send <= '0'; + SYNC <= '0'; +-- OKAI_send <= '0'; end if; end if; diff --git a/lib/lpp/lpp_cna/ReadFifo_GEN.vhd b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd new file mode 100644 --- /dev/null +++ b/lib/lpp/lpp_cna/ReadFifo_GEN.vhd @@ -0,0 +1,67 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------ +-- Author : Martin Morlot +-- Mail : martin.morlot@lpp.polytechnique.fr +------------------------------------------------------------------------------ +library IEEE; +use IEEE.numeric_std.all; +use IEEE.std_logic_1164.all; + +entity ReadFifo_GEN is + port( + clk,raz : in std_logic; --! Horloge et Reset du composant + SYNC : in std_logic; + Readn : out std_logic + ); +end entity; + + +architecture ar_ReadFifo_GEN of ReadFifo_GEN is + +type etat is (eX,e0); +signal ect : etat; + +signal SYNC_reg : std_logic; + +begin + process(clk,raz) + begin + if(raz='0')then + ect <= eX; + Readn <= '1'; + + elsif(clk'event and clk='1')then + SYNC_reg <= SYNC; + + case ect is + when eX => + if (SYNC_reg='0' and SYNC='1') then + Readn <= '0'; + ect <= e0; + end if; + + when e0 => + Readn <= '1'; + ect <= eX; + + end case; + end if; + end process; + +end architecture; \ No newline at end of file diff --git a/lib/lpp/lpp_cna/Serialize.vhd b/lib/lpp/lpp_cna/Serialize.vhd --- a/lib/lpp/lpp_cna/Serialize.vhd +++ b/lib/lpp/lpp_cna/Serialize.vhd @@ -31,7 +31,7 @@ entity Serialize is sclk : in std_logic; --! Horloge Systeme vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entr�e send : in std_logic; --! Flag, Une nouvelle donn�e est pr�sente - sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e +-- sended : out std_logic; --! Flag, La donn�e a �t� s�rialis�e Data : out std_logic --! Donn�e num�rique s�rialis� ); end Serialize; @@ -39,7 +39,7 @@ end Serialize; architecture ar_Serialize of Serialize is -type etat is (attente,serialize); +type etat is (attente,serialize,reg); signal ect : etat; signal vector_int : std_logic_vector(16 downto 0); @@ -47,6 +47,7 @@ signal vectin_reg : std_logic_vector(1 signal load : std_logic; signal N : integer range 0 to 16; signal CPT_ended : std_logic:='0'; +signal i : std_logic; begin process(clk,raz) @@ -55,7 +56,8 @@ begin ect <= attente; vectin_reg <= (others=> '0'); load <= '0'; - sended <= '1'; + i <= '1'; +-- sended <= '1'; elsif(clk'event and clk='1')then vectin_reg <= vectin; @@ -63,18 +65,25 @@ begin case ect is when attente => if (send='1') then - sended <= '0'; - load <= '1'; - ect <= serialize; - else - ect <= attente; +-- sended <= '0'; + if(i='1')then + i <= '0'; + ect <= reg; + else + load <= '1'; + ect <= serialize; + end if; end if; + when reg => + load <= '1'; + ect <= serialize; + when serialize => load <= '0'; if(CPT_ended='1')then ect <= attente; - sended <= '1'; +-- sended <= '1'; end if; end case; diff --git a/lib/lpp/lpp_cna/lpp_cna.vhd b/lib/lpp/lpp_cna/lpp_cna.vhd --- a/lib/lpp/lpp_cna/lpp_cna.vhd +++ b/lib/lpp/lpp_cna/lpp_cna.vhd @@ -37,13 +37,16 @@ component APB_DAC is paddr : integer := 0; pmask : integer := 16#fff#; pirq : integer := 0; - abits : integer := 8); + abits : integer := 8; + cpt_serial : integer := 6); port ( clk : in std_logic; rst : in std_logic; apbi : in apb_slv_in_type; apbo : out apb_slv_out_type; + DataIN : in std_logic_vector(15 downto 0); Cal_EN : out std_logic; + Readn : out std_logic; SYNC : out std_logic; SCLK : out std_logic; DATA : out std_logic @@ -52,14 +55,15 @@ end component; component DacDriver is + generic(cpt_serial : integer := 6); port( clk : in std_logic; rst : in std_logic; enable : in std_logic; - Data_C : in std_logic_vector(15 downto 0); + Data_reg : in std_logic_vector(15 downto 0); SYNC : out std_logic; SCLK : out std_logic; - flag_sd : out std_logic; + Readn : out std_logic; Data : out std_logic ); end component; @@ -74,12 +78,12 @@ end component; component Gene_SYNC is - port( - clk,raz : in std_logic; - send : in std_logic; - Sysclk : in std_logic; - OKAI_send : out std_logic; - SYNC : out std_logic); + port( + SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant + enable : in std_logic; --! Autorise ou non l'utilisation du composant +-- OKAI_send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e + SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r� + ); end component; @@ -89,8 +93,16 @@ port( sclk : in std_logic; vectin : in std_logic_vector(15 downto 0); send : in std_logic; - sended : out std_logic; +-- sended : out std_logic; Data : out std_logic); end component; +component ReadFifo_GEN is + port( + clk,raz : in std_logic; + SYNC : in std_logic; + Readn : out std_logic + ); +end component; + end;