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Update APB_TIME_MANAGEMENT :...
pellion -
r336:d05a1ff29f0e (MINI-LFR) WFP_MS-0-1-9 JC
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@@ -425,7 +425,7 BEGIN -- beh
425 425 pirq_ms => 6,
426 426 pirq_wfp => 14,
427 427 hindex => 2,
428 top_lfr_version => X"000107") -- aa.bb.cc version
428 top_lfr_version => X"000109") -- aa.bb.cc version
429 429 PORT MAP (
430 430 clk => clk_25,
431 431 rstn => reset,
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@@ -149,6 +149,66 BEGIN -- beh
149 149 grspw_tick <= '1';------------------------------------------------------3
150 150 WAIT UNTIL clk25MHz = '1';
151 151 grspw_tick <= '0';
152
153
154 WAIT FOR 250 ms;
155 WAIT UNTIL clk25MHz = '1';
156 TB_string <= "CT new ";
157 -- WRITE NEW COARSE_TIME
158 apbi.psel(0) <= '1';
159 apbi.pwrite <= '1';
160 apbi.penable <= '1';
161 apbi.paddr <= X"00000004";
162 apbi.pwdata <= X"80005678";
163 WAIT UNTIL clk25MHz = '1';
164 apbi.psel(0) <= '0';
165 apbi.pwrite <= '0';
166 apbi.penable <= '0';
167 apbi.paddr <= (OTHERS => '0');
168 apbi.pwdata <= (OTHERS => '0');
169 WAIT UNTIL clk25MHz = '1';
170
171 WAIT FOR 10 ms;
172 WAIT UNTIL clk25MHz = '1';
173 TB_string <= "TICK 5 ";
174 grspw_tick <= '1';------------------------------------------------------3
175 WAIT UNTIL clk25MHz = '1';
176 grspw_tick <= '0';
177
178
179 WAIT FOR 20 ms;
180 WAIT UNTIL clk25MHz = '1';
181 TB_string <= "CT new ";
182 -- WRITE NEW COARSE_TIME
183 apbi.psel(0) <= '1';
184 apbi.pwrite <= '1';
185 apbi.penable <= '1';
186 apbi.paddr <= X"00000004";
187 apbi.pwdata <= X"00005678";
188 WAIT UNTIL clk25MHz = '1';
189 apbi.psel(0) <= '0';
190 apbi.pwrite <= '0';
191 apbi.penable <= '0';
192 apbi.paddr <= (OTHERS => '0');
193 apbi.pwdata <= (OTHERS => '0');
194 WAIT UNTIL clk25MHz = '1';
195
196 WAIT FOR 25 ms;
197 WAIT UNTIL clk25MHz = '1';
198 TB_string <= "Soft RST";
199 -- WRITE SOFT RESET
200 apbi.psel(0) <= '1';
201 apbi.pwrite <= '1';
202 apbi.penable <= '1';
203 apbi.paddr <= X"00000000";
204 apbi.pwdata <= X"00000002";
205 WAIT UNTIL clk25MHz = '1';
206 apbi.psel(0) <= '0';
207 apbi.pwrite <= '0';
208 apbi.penable <= '0';
209 apbi.paddr <= (OTHERS => '0');
210 apbi.pwdata <= (OTHERS => '0');
211 WAIT UNTIL clk25MHz = '1';
152 212
153 213 WAIT FOR 250 ms;
154 214 TB_string <= "READ 1 ";
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@@ -65,7 +65,8 ARCHITECTURE Behavioral OF apb_lfr_time_
65 65
66 66 TYPE apb_lfr_time_management_Reg IS RECORD
67 67 ctrl : STD_LOGIC;
68 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
68 soft_reset : STD_LOGIC;
69 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
69 70 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 71 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 72 END RECORD;
@@ -77,7 +78,7 ARCHITECTURE Behavioral OF apb_lfr_time_
77 78 SIGNAL soft_tick : STD_LOGIC;
78 79
79 80 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
81 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
81 82
82 83 --SIGNAL coarse_time_new : STD_LOGIC;
83 84 SIGNAL coarse_time_new_49 : STD_LOGIC;
@@ -95,6 +96,15 ARCHITECTURE Behavioral OF apb_lfr_time_
95 96
96 97 SIGNAL time_new_49 : STD_LOGIC;
97 98 SIGNAL time_new : STD_LOGIC;
99
100 -----------------------------------------------------------------------------
101 SIGNAL force_reset : STD_LOGIC;
102 SIGNAL previous_force_reset : STD_LOGIC;
103 SIGNAL soft_reset : STD_LOGIC;
104 SIGNAL soft_reset_sync : STD_LOGIC;
105 -----------------------------------------------------------------------------
106
107 SIGNAL rstn_LFR_TM : STD_LOGIC;
98 108
99 109 BEGIN
100 110
@@ -103,7 +113,8 BEGIN
103 113
104 114 IF resetn = '0' THEN
105 115 Rdata <= (OTHERS => '0');
106 r.coarse_time_load <= x"80000000";
116 r.coarse_time_load <= (OTHERS => '0');
117 r.soft_reset <= '0';
107 118 r.ctrl <= '0';
108 119 force_tick <= '0';
109 120 previous_force_tick <= '0';
@@ -121,20 +132,34 BEGIN
121 132 ELSE
122 133 soft_tick <= '0';
123 134 END IF;
135
136 force_reset <= r.soft_reset;
137 previous_force_reset <= force_reset;
138 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
139 soft_reset <= '1';
140 ELSE
141 soft_reset <= '0';
142 END IF;
124 143
125 144 --APB Write OP
126 145 IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN
127 146 CASE apbi.paddr(7 DOWNTO 2) IS
128 147 WHEN "000000" =>
129 r.ctrl <= apbi.pwdata(0);
148 r.ctrl <= apbi.pwdata(0);
149 r.soft_reset <= apbi.pwdata(1);
130 150 WHEN "000001" =>
131 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
151 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
132 152 coarsetime_reg_updated <= '1';
133 153 WHEN OTHERS =>
134 154 NULL;
135 155 END CASE;
136 ELSIF r.ctrl = '1' THEN
137 r.ctrl <= '0';
156 ELSE
157 IF r.ctrl = '1' THEN
158 r.ctrl <= '0';
159 END if;
160 IF r.soft_reset = '1' THEN
161 r.soft_reset <= '0';
162 END if;
138 163 END IF;
139 164
140 165 --APB READ OP
@@ -142,9 +167,10 BEGIN
142 167 CASE apbi.paddr(7 DOWNTO 2) IS
143 168 WHEN "000000" =>
144 169 Rdata(0) <= r.ctrl;
170 Rdata(1) <= r.soft_reset;
145 171 Rdata(31 DOWNTO 1) <= (others => '0');
146 172 WHEN "000001" =>
147 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
173 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
148 174 WHEN "000010" =>
149 175 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
150 176 WHEN "000011" =>
@@ -197,7 +223,16 BEGIN
197 223 rstn => resetn,
198 224 sin => coarsetime_reg_updated,
199 225 sout => new_coarsetime);
200 ----------------------------------------------------------------------------
226
227 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
228 GENERIC MAP (
229 NB_FF_OF_SYNC => 2)
230 PORT MAP (
231 clk_in => clk25MHz,
232 clk_out => clk24_576MHz,
233 rstn => resetn,
234 sin => soft_reset,
235 sout => soft_reset_sync);
201 236
202 237 -----------------------------------------------------------------------------
203 238 --SYNC_FF_1 : SYNC_FF
@@ -253,6 +288,12 BEGIN
253 288 END IF;
254 289 END PROCESS;
255 290
291
292 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
293 '0' WHEN soft_reset_sync = '1' ELSE
294 '1';
295
296
256 297 -----------------------------------------------------------------------------
257 298 -- LFR_TIME_MANAGMENT
258 299 -----------------------------------------------------------------------------
@@ -262,11 +303,11 BEGIN
262 303 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
263 304 PORT MAP (
264 305 clk => clk24_576MHz,
265 rstn => resetn,
306 rstn => rstn_LFR_TM,
266 307
267 308 tick => new_timecode,
268 309 new_coarsetime => new_coarsetime,
269 coarsetime_reg => coarsetime_reg(31 DOWNTO 0),
310 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
270 311
271 312 fine_time => fine_time_49,
272 313 fine_time_new => fine_time_new_49,
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@@ -15,7 +15,8 ENTITY coarse_time_counter IS
15 15
16 16 tick : IN STD_LOGIC;
17 17 set_TCU : IN STD_LOGIC;
18 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
18 new_TCU : IN STD_LOGIC;
19 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19 20 CT_add1 : IN STD_LOGIC;
20 21 fsm_desync : IN STD_LOGIC;
21 22 FT_max : IN STD_LOGIC;
@@ -41,6 +42,9 ARCHITECTURE beh OF coarse_time_counter
41 42 --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60
42 43 BEGIN -- beh
43 44
45 -----------------------------------------------------------------------------
46 -- COARSE_TIME( 30 DOWNTO 0)
47 -----------------------------------------------------------------------------
44 48 counter_1 : general_counter
45 49 GENERIC MAP (
46 50 CYCLIC => '1',
@@ -58,10 +62,15 BEGIN -- beh
58 62
59 63 add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0';
60 64
65 -----------------------------------------------------------------------------
66 -- COARSE_TIME(31)
67 -----------------------------------------------------------------------------
61 68
62 set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
63 set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
64 (OTHERS => '0');
69 --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU);
70 --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE
71 -- (OTHERS => '0');
72 set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU));
73 set_synchronized_value <= (OTHERS => '0');
65 74
66 75 counter_2 : general_counter
67 76 GENERIC MAP (
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@@ -34,7 +34,7 ENTITY lfr_time_management IS
34 34 tick : IN STD_LOGIC; -- transition signal information
35 35
36 36 new_coarsetime : IN STD_LOGIC; -- transition signal information
37 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
37 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
38 38
39 39 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
40 40 fine_time_new : OUT STD_LOGIC;
@@ -107,6 +107,7 BEGIN
107 107 rstn => rstn,
108 108 tick => tick,
109 109 set_TCU => set_TCU, -- todo
110 new_TCU => new_coarsetime_reg,
110 111 set_TCU_value => coarsetime_reg, -- todo
111 112 CT_add1 => CT_add1, -- todo
112 113 fsm_desync => fsm_desync, -- todo
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@@ -57,7 +57,7 PACKAGE lpp_lfr_time_management IS
57 57 rstn : IN STD_LOGIC;
58 58 tick : IN STD_LOGIC;
59 59 new_coarsetime : IN STD_LOGIC;
60 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
60 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 61 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
62 62 fine_time_new : OUT STD_LOGIC;
63 63 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -72,7 +72,8 PACKAGE lpp_lfr_time_management IS
72 72 rstn : IN STD_LOGIC;
73 73 tick : IN STD_LOGIC;
74 74 set_TCU : IN STD_LOGIC;
75 set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 new_TCU : IN STD_LOGIC;
76 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
76 77 CT_add1 : IN STD_LOGIC;
77 78 fsm_desync : IN STD_LOGIC;
78 79 FT_max : IN STD_LOGIC;
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