diff --git a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd --- a/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +++ b/designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd @@ -425,7 +425,7 @@ BEGIN -- beh pirq_ms => 6, pirq_wfp => 14, hindex => 2, - top_lfr_version => X"000107") -- aa.bb.cc version + top_lfr_version => X"000109") -- aa.bb.cc version PORT MAP ( clk => clk_25, rstn => reset, diff --git a/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd b/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd --- a/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd +++ b/designs/Validation_LFR_TIME_MANAGEMENT/TB.vhd @@ -149,6 +149,66 @@ BEGIN -- beh grspw_tick <= '1';------------------------------------------------------3 WAIT UNTIL clk25MHz = '1'; grspw_tick <= '0'; + + + WAIT FOR 250 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "CT new "; + -- WRITE NEW COARSE_TIME + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000004"; + apbi.pwdata <= X"80005678"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 10 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "TICK 5 "; + grspw_tick <= '1';------------------------------------------------------3 + WAIT UNTIL clk25MHz = '1'; + grspw_tick <= '0'; + + + WAIT FOR 20 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "CT new "; + -- WRITE NEW COARSE_TIME + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000004"; + apbi.pwdata <= X"00005678"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; + + WAIT FOR 25 ms; + WAIT UNTIL clk25MHz = '1'; + TB_string <= "Soft RST"; + -- WRITE SOFT RESET + apbi.psel(0) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= X"00000000"; + apbi.pwdata <= X"00000002"; + WAIT UNTIL clk25MHz = '1'; + apbi.psel(0) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; WAIT FOR 250 ms; TB_string <= "READ 1 "; diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -65,7 +65,8 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ TYPE apb_lfr_time_management_Reg IS RECORD ctrl : STD_LOGIC; - coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0); + soft_reset : STD_LOGIC; + coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0); coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); END RECORD; @@ -77,7 +78,7 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ SIGNAL soft_tick : STD_LOGIC; SIGNAL coarsetime_reg_updated : STD_LOGIC; - SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0); --SIGNAL coarse_time_new : STD_LOGIC; SIGNAL coarse_time_new_49 : STD_LOGIC; @@ -95,6 +96,15 @@ ARCHITECTURE Behavioral OF apb_lfr_time_ SIGNAL time_new_49 : STD_LOGIC; SIGNAL time_new : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL force_reset : STD_LOGIC; + SIGNAL previous_force_reset : STD_LOGIC; + SIGNAL soft_reset : STD_LOGIC; + SIGNAL soft_reset_sync : STD_LOGIC; + ----------------------------------------------------------------------------- + + SIGNAL rstn_LFR_TM : STD_LOGIC; BEGIN @@ -103,7 +113,8 @@ BEGIN IF resetn = '0' THEN Rdata <= (OTHERS => '0'); - r.coarse_time_load <= x"80000000"; + r.coarse_time_load <= (OTHERS => '0'); + r.soft_reset <= '0'; r.ctrl <= '0'; force_tick <= '0'; previous_force_tick <= '0'; @@ -121,20 +132,34 @@ BEGIN ELSE soft_tick <= '0'; END IF; + + force_reset <= r.soft_reset; + previous_force_reset <= force_reset; + IF (previous_force_reset = '0') AND (force_reset = '1') THEN + soft_reset <= '1'; + ELSE + soft_reset <= '0'; + END IF; --APB Write OP IF (apbi.psel(pindex) AND apbi.penable AND apbi.pwrite) = '1' THEN CASE apbi.paddr(7 DOWNTO 2) IS WHEN "000000" => - r.ctrl <= apbi.pwdata(0); + r.ctrl <= apbi.pwdata(0); + r.soft_reset <= apbi.pwdata(1); WHEN "000001" => - r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0); + r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0); coarsetime_reg_updated <= '1'; WHEN OTHERS => NULL; END CASE; - ELSIF r.ctrl = '1' THEN - r.ctrl <= '0'; + ELSE + IF r.ctrl = '1' THEN + r.ctrl <= '0'; + END if; + IF r.soft_reset = '1' THEN + r.soft_reset <= '0'; + END if; END IF; --APB READ OP @@ -142,9 +167,10 @@ BEGIN CASE apbi.paddr(7 DOWNTO 2) IS WHEN "000000" => Rdata(0) <= r.ctrl; + Rdata(1) <= r.soft_reset; Rdata(31 DOWNTO 1) <= (others => '0'); WHEN "000001" => - Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0); + Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0); WHEN "000010" => Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0); WHEN "000011" => @@ -197,7 +223,16 @@ BEGIN rstn => resetn, sin => coarsetime_reg_updated, sout => new_coarsetime); - ---------------------------------------------------------------------------- + + SYNC_VALID_BIT_3 : SYNC_VALID_BIT + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk_in => clk25MHz, + clk_out => clk24_576MHz, + rstn => resetn, + sin => soft_reset, + sout => soft_reset_sync); ----------------------------------------------------------------------------- --SYNC_FF_1 : SYNC_FF @@ -253,6 +288,12 @@ BEGIN END IF; END PROCESS; + + rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE + '0' WHEN soft_reset_sync = '1' ELSE + '1'; + + ----------------------------------------------------------------------------- -- LFR_TIME_MANAGMENT ----------------------------------------------------------------------------- @@ -262,11 +303,11 @@ BEGIN NB_SECOND_DESYNC => NB_SECOND_DESYNC) PORT MAP ( clk => clk24_576MHz, - rstn => resetn, + rstn => rstn_LFR_TM, tick => new_timecode, new_coarsetime => new_coarsetime, - coarsetime_reg => coarsetime_reg(31 DOWNTO 0), + coarsetime_reg => coarsetime_reg(30 DOWNTO 0), fine_time => fine_time_49, fine_time_new => fine_time_new_49, diff --git a/lib/lpp/lfr_time_management/coarse_time_counter.vhd b/lib/lpp/lfr_time_management/coarse_time_counter.vhd --- a/lib/lpp/lfr_time_management/coarse_time_counter.vhd +++ b/lib/lpp/lfr_time_management/coarse_time_counter.vhd @@ -15,7 +15,8 @@ ENTITY coarse_time_counter IS tick : IN STD_LOGIC; set_TCU : IN STD_LOGIC; - set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + new_TCU : IN STD_LOGIC; + set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); CT_add1 : IN STD_LOGIC; fsm_desync : IN STD_LOGIC; FT_max : IN STD_LOGIC; @@ -41,6 +42,9 @@ ARCHITECTURE beh OF coarse_time_counter --CONSTANT NB_SECOND_DESYNC : INTEGER := 4; -- TODO : 60 BEGIN -- beh + ----------------------------------------------------------------------------- + -- COARSE_TIME( 30 DOWNTO 0) + ----------------------------------------------------------------------------- counter_1 : general_counter GENERIC MAP ( CYCLIC => '1', @@ -58,10 +62,15 @@ BEGIN -- beh add1_bit31 <= '1' WHEN fsm_desync = '1' AND FT_max = '1' ELSE '0'; + ----------------------------------------------------------------------------- + -- COARSE_TIME(31) + ----------------------------------------------------------------------------- - set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU); - set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE - (OTHERS => '0'); + --set_synchronized <= (tick AND (NOT coarse_time_31)) OR (coarse_time_31 AND set_TCU); + --set_synchronized_value <= STD_LOGIC_VECTOR(to_unsigned(NB_SECOND_DESYNC, 6)) WHEN (set_TCU AND set_TCU_value(31)) = '1' ELSE + -- (OTHERS => '0'); + set_synchronized <= tick AND ((NOT coarse_time_31) OR (coarse_time_31 AND new_TCU)); + set_synchronized_value <= (OTHERS => '0'); counter_2 : general_counter GENERIC MAP ( diff --git a/lib/lpp/lfr_time_management/lfr_time_management.vhd b/lib/lpp/lfr_time_management/lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lfr_time_management.vhd @@ -34,7 +34,7 @@ ENTITY lfr_time_management IS tick : IN STD_LOGIC; -- transition signal information new_coarsetime : IN STD_LOGIC; -- transition signal information - coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); fine_time_new : OUT STD_LOGIC; @@ -107,6 +107,7 @@ BEGIN rstn => rstn, tick => tick, set_TCU => set_TCU, -- todo + new_TCU => new_coarsetime_reg, set_TCU_value => coarsetime_reg, -- todo CT_add1 => CT_add1, -- todo fsm_desync => fsm_desync, -- todo diff --git a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/lpp_lfr_time_management.vhd @@ -57,7 +57,7 @@ PACKAGE lpp_lfr_time_management IS rstn : IN STD_LOGIC; tick : IN STD_LOGIC; new_coarsetime : IN STD_LOGIC; - coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0); fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); fine_time_new : OUT STD_LOGIC; coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); @@ -72,7 +72,8 @@ PACKAGE lpp_lfr_time_management IS rstn : IN STD_LOGIC; tick : IN STD_LOGIC; set_TCU : IN STD_LOGIC; - set_TCU_value : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + new_TCU : IN STD_LOGIC; + set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0); CT_add1 : IN STD_LOGIC; fsm_desync : IN STD_LOGIC; FT_max : IN STD_LOGIC;