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1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 ./general_purpose
2 ./general_purpose
6 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./dsp/iir_filter
7 ./dsp/lpp_downsampling
8 ./dsp/lpp_fft
9 ./lfr_time_management
9 ./lfr_time_management
10 ./lpp_ad_Conv
10 ./lpp_ad_Conv
11 ./lpp_amba
11 ./lpp_amba
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@@ -1,120 +1,120
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY lpp;
25 LIBRARY lpp;
26 USE lpp.iir_filter.ALL;
26 USE lpp.iir_filter.ALL;
27 USE lpp.FILTERcfg.ALL;
27 USE lpp.FILTERcfg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29 LIBRARY techmap;
29 LIBRARY techmap;
30 USE techmap.gencomp.ALL;
30 USE techmap.gencomp.ALL;
31
31
32 ENTITY RAM_CTRLR_v2 IS
32 ENTITY RAM_CTRLR_v2 IS
33 GENERIC(
33 GENERIC(
34 tech : INTEGER := 0;
34 tech : INTEGER := 0;
35 Input_SZ_1 : INTEGER := 16;
35 Input_SZ_1 : INTEGER := 16;
36 Mem_use : INTEGER := use_RAM
36 Mem_use : INTEGER := use_RAM
37 );
37 );
38 PORT(
38 PORT(
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
40 clk : IN STD_LOGIC;
41 -- R/W Ctrl
41 -- R/W Ctrl
42 ram_write : IN STD_LOGIC;
42 ram_write : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
43 ram_read : IN STD_LOGIC;
44 -- ADDR Ctrl
44 -- ADDR Ctrl
45 raddr_rst : IN STD_LOGIC;
45 raddr_rst : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
46 raddr_add1 : IN STD_LOGIC;
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
47 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
48 -- Data
48 -- Data
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
49 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
50 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)
51 );
51 );
52 END RAM_CTRLR_v2;
52 END RAM_CTRLR_v2;
53
53
54
54
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
55 ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS
56
56
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
57 SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
58 SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
59 SIGNAL WEN, REN : STD_LOGIC;
59 SIGNAL WEN, REN : STD_LOGIC;
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
60 SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
61 SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
62 SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0);
63
63
64 BEGIN
64 BEGIN
65
65
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
66 sample_out <= RD(Input_SZ_1-1 DOWNTO 0);
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
67 WD(Input_SZ_1-1 DOWNTO 0) <= sample_in;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 -- RAM
69 -- RAM
70 -----------------------------------------------------------------------------
70 -----------------------------------------------------------------------------
71
71
72 memCEL : IF Mem_use = use_CEL GENERATE
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
74 REN <= NOT ram_read;
75 RAMblk : RAM_CEL_N
75 RAMblk : RAM_CEL_N
76 GENERIC MAP(Input_SZ_1)
76 GENERIC MAP(Input_SZ_1)
77 PORT MAP(
77 PORT MAP(
78 WD => WD,
78 WD => WD,
79 RD => RD,
79 RD => RD,
80 WEN => WEN,
80 WEN => WEN,
81 REN => REN,
81 REN => REN,
82 WADDR => WADDR,
82 WADDR => WADDR,
83 RADDR => RADDR,
83 RADDR => RADDR,
84 RWCLK => clk,
84 RWCLK => clk,
85 RESET => rstn
85 RESET => rstn
86 ) ;
86 ) ;
87 END GENERATE;
87 END GENERATE;
88
88
89 memRAM : IF Mem_use = use_RAM GENERATE
89 memRAM : IF Mem_use = use_RAM GENERATE
90 SRAM : syncram_2p
90 SRAM : syncram_2p
91 GENERIC MAP(tech, 8, Input_SZ_1)
91 GENERIC MAP(tech, 8, Input_SZ_1)
92 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
92 PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD);
93 END GENERATE;
93 END GENERATE;
94
94
95 -----------------------------------------------------------------------------
95 -----------------------------------------------------------------------------
96 -- RADDR
96 -- RADDR
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 PROCESS (clk, rstn)
98 PROCESS (clk, rstn)
99 BEGIN -- PROCESS
99 BEGIN -- PROCESS
100 IF rstn = '0' THEN -- asynchronous reset (active low)
100 IF rstn = '0' THEN -- asynchronous reset (active low)
101 counter <= (OTHERS => '0');
101 counter <= (OTHERS => '0');
102 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
102 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
103 IF raddr_rst = '1' THEN
103 IF raddr_rst = '1' THEN
104 counter <= (OTHERS => '0');
104 counter <= (OTHERS => '0');
105 ELSIF raddr_add1 = '1' THEN
105 ELSIF raddr_add1 = '1' THEN
106 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
106 counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1);
107 END IF;
107 END IF;
108 END IF;
108 END IF;
109 END PROCESS;
109 END PROCESS;
110 RADDR <= counter;
110 RADDR <= counter;
111
111
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113 -- WADDR
113 -- WADDR
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
115 WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE
116 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
116 STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE
117 STD_LOGIC_VECTOR(UNSIGNED(counter));
117 STD_LOGIC_VECTOR(UNSIGNED(counter));
118
118
119
119
120 END ar_RAM_CTRLR_v2;
120 END ar_RAM_CTRLR_v2; No newline at end of file
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@@ -164,11 +164,11 BEGIN
164 END IF;
164 END IF;
165
165
166 END IF;
166 END IF;
167 apbo.pconfig <= pconfig;
168 END PROCESS;
167 END PROCESS;
169
168
170 apbo.prdata <= Rdata WHEN apbi.penable = '1';
169 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
171 coarse_time <= r.coarse_time;
170 coarse_time <= r.coarse_time;
172 fine_time <= r.fine_time;
171 fine_time <= r.fine_time;
172 apbo.pconfig <= pconfig;
173
173
174 END Behavioral;
174 END Behavioral; No newline at end of file
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@@ -1,197 +1,196
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 -- MODIFIED by Jean-christophe PELLION
22 -- MODIFIED by Jean-christophe PELLION
23 -- jean-christophe.pellion@lpp.polytechnique.fr
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY IEEE;
25 LIBRARY IEEE;
26 USE IEEE.STD_LOGIC_1164.ALL;
26 USE IEEE.STD_LOGIC_1164.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.general_purpose.SYNC_FF;
29 USE lpp.general_purpose.SYNC_FF;
30
30
31 ENTITY AD7688_drvr IS
31 ENTITY AD7688_drvr IS
32 GENERIC(
32 GENERIC(
33 ChanelCount : INTEGER;
33 ChanelCount : INTEGER;
34 ncycle_cnv_high : INTEGER := 79;
34 ncycle_cnv_high : INTEGER := 79;
35 ncycle_cnv : INTEGER := 500);
35 ncycle_cnv : INTEGER := 500);
36 PORT (
36 PORT (
37 -- CONV --
37 -- CONV --
38 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
40 cnv_run : IN STD_LOGIC;
41 cnv : OUT STD_LOGIC;
41 cnv : OUT STD_LOGIC;
42
42
43 -- DATA --
43 -- DATA --
44 clk : IN STD_LOGIC;
44 clk : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
45 rstn : IN STD_LOGIC;
46 sck : OUT STD_LOGIC;
46 sck : OUT STD_LOGIC;
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
48
48
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
50 sample_val : OUT STD_LOGIC
50 sample_val : OUT STD_LOGIC
51 );
51 );
52 END AD7688_drvr;
52 END AD7688_drvr;
53
53
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
55
55
56 COMPONENT SYNC_FF
56 COMPONENT SYNC_FF
57 GENERIC (
57 GENERIC (
58 NB_FF_OF_SYNC : INTEGER);
58 NB_FF_OF_SYNC : INTEGER);
59 PORT (
59 PORT (
60 clk : IN STD_LOGIC;
60 clk : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
61 rstn : IN STD_LOGIC;
62 A : IN STD_LOGIC;
62 A : IN STD_LOGIC;
63 A_sync : OUT STD_LOGIC);
63 A_sync : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66
66
67 SIGNAL cnv_cycle_counter : INTEGER;
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
74
74
75 SIGNAL cnv_run_sync : STD_LOGIC;
75 SIGNAL cnv_run_sync : STD_LOGIC;
76
76
77 BEGIN
77 BEGIN
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 -- CONV
79 -- CONV
80 -----------------------------------------------------------------------------
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
91 cnv_s <= '1';
92 ELSE
92 ELSE
93 cnv_s <= '0';
93 cnv_s <= '0';
94 END IF;
94 END IF;
95 ELSE
95 ELSE
96 cnv_s <= '1';
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
97 cnv_cycle_counter <= 0;
98 END IF;
98 END IF;
99 ELSE
99 ELSE
100 cnv_s <= '0';
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
101 cnv_cycle_counter <= 0;
102 END IF;
102 END IF;
103 END IF;
103 END IF;
104 END PROCESS;
104 END PROCESS;
105
105
106 cnv <= cnv_s;
106 cnv <= cnv_s;
107
107
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109
109
110
110
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114
114
115 SYNC_FF_cnv : SYNC_FF
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
118 PORT MAP (
119 clk => clk,
119 clk => clk,
120 rstn => rstn,
120 rstn => rstn,
121 A => cnv_s,
121 A => cnv_s,
122 A_sync => cnv_sync);
122 A_sync => cnv_sync);
123
123
124 PROCESS (clk, rstn)
124 PROCESS (clk, rstn)
125 BEGIN
125 BEGIN
126 IF rstn = '0' THEN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
132 END IF;
133 END PROCESS;
133 END PROCESS;
134
134
135 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
136
136
137 SYNC_FF_run : SYNC_FF
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
140 PORT MAP (
141 clk => clk,
141 clk => clk,
142 rstn => rstn,
142 rstn => rstn,
143 A => cnv_run,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
144 A_sync => cnv_run_sync);
145
145
146
146
147
147
148 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
149 -- DATA
149 -- DATA
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
156 END LOOP;
157 sample_bit_counter <= 0;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
158 sample_val <= '0';
159 SCK <= '1';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
160 ELSIF clk'EVENT AND clk = '1' THEN
161
161
162 IF cnv_run_sync = '0' THEN
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
168 END IF;
169
169
170 IF (sample_bit_counter MOD 2) = 1 THEN
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 --shift_reg(l)(15) <= sdo(l);
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
175 shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0);
176 END LOOP;
176 END LOOP;
177 SCK <= '0';
177 SCK <= '0';
178 ELSE
178 ELSE
179 SCK <= '1';
179 SCK <= '1';
180 END IF;
180 END IF;
181
181
182 IF sample_bit_counter = 31 THEN
182 IF sample_bit_counter = 31 THEN
183 sample_val <= '1';
183 sample_val <= '1';
184 FOR l IN 0 TO ChanelCount-1 LOOP
184 FOR l IN 0 TO ChanelCount-1 LOOP
185 --sample(l)(15) <= sdo(l);
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
189 END LOOP;
189 END LOOP;
190 ELSE
190 ELSE
191 sample_val <= '0';
191 sample_val <= '0';
192 END IF;
192 END IF;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 END ar_AD7688_drvr;
196 END ar_AD7688_drvr;
197
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@@ -405,4 +405,4 BEGIN -- beh
405 apbo.prdata <= prdata;
405 apbo.prdata <= prdata;
406
406
407
407
408 END beh;
408 END beh; No newline at end of file
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@@ -1,243 +1,251
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12
12
13 LIBRARY techmap;
13 LIBRARY techmap;
14 USE techmap.gencomp.ALL;
14 USE techmap.gencomp.ALL;
15
15
16 LIBRARY grlib;
16 LIBRARY grlib;
17 USE grlib.amba.ALL;
17 USE grlib.amba.ALL;
18 USE grlib.stdlib.ALL;
18 USE grlib.stdlib.ALL;
19 USE grlib.devices.ALL;
19 USE grlib.devices.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
20 USE GRLIB.DMA2AHB_Package.ALL;
21
21
22 ENTITY lpp_top_lfr_wf_picker IS
22 ENTITY lpp_top_lfr_wf_picker IS
23 GENERIC (
23 GENERIC (
24 hindex : INTEGER := 2;
24 hindex : INTEGER := 2;
25 pindex : INTEGER := 4;
25 pindex : INTEGER := 15;
26 paddr : INTEGER := 4;
26 paddr : INTEGER := 15;
27 pmask : INTEGER := 16#fff#;
27 pmask : INTEGER := 16#fff#;
28 pirq : INTEGER := 0;
28 pirq : INTEGER := 15;
29 tech : INTEGER := 0;
29 tech : INTEGER := 0;
30 nb_burst_available_size : INTEGER := 11;
30 nb_burst_available_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
31 nb_snapshot_param_size : INTEGER := 11;
32 delta_snapshot_size : INTEGER := 16;
32 delta_snapshot_size : INTEGER := 16;
33 delta_f2_f0_size : INTEGER := 10;
33 delta_f2_f0_size : INTEGER := 10;
34 delta_f2_f1_size : INTEGER := 10
34 delta_f2_f1_size : INTEGER := 10
35 );
35 );
36 PORT (
36 PORT (
37 -- ADS7886
37 -- ADS7886
38 cnv_run : IN STD_LOGIC;
38 cnv_run : IN STD_LOGIC;
39 cnv : OUT STD_LOGIC;
39 cnv : OUT STD_LOGIC;
40 sck : OUT STD_LOGIC;
40 sck : OUT STD_LOGIC;
41 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
41 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
42 --
42 --
43 cnv_clk : IN STD_LOGIC;
43 cnv_clk : IN STD_LOGIC;
44 cnv_rstn : IN STD_LOGIC;
44 cnv_rstn : IN STD_LOGIC;
45
45
46 -- AMBA AHB system signals
46 -- AMBA AHB system signals
47 HCLK : IN STD_ULOGIC;
47 HCLK : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
48 HRESETn : IN STD_ULOGIC;
49
49
50 -- AMBA APB Slave Interface
50 -- AMBA APB Slave Interface
51 apbi : IN apb_slv_in_type;
51 apbi : IN apb_slv_in_type;
52 apbo : OUT apb_slv_out_type;
52 apbo : OUT apb_slv_out_type;
53
53
54 -- AMBA AHB Master Interface
54 -- AMBA AHB Master Interface
55 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57
57
58 --
58 --
59 coarse_time_0 : IN STD_LOGIC;
59 coarse_time_0 : IN STD_LOGIC;
60
60
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC
62 data_shaping_BW : OUT STD_LOGIC
63 );
63 );
64 END lpp_top_lfr_wf_picker;
64 END lpp_top_lfr_wf_picker;
65
65
66 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
66 ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS
67
67
68 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 SIGNAL status_error_bad_component_error : STD_LOGIC;
80 SIGNAL status_error_bad_component_error : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
87
88 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
88 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
90 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
91 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
92 SIGNAL data_shaping_SP0 : STD_LOGIC;
92 SIGNAL data_shaping_SP0 : STD_LOGIC;
93 SIGNAL data_shaping_SP1 : STD_LOGIC;
93 SIGNAL data_shaping_SP1 : STD_LOGIC;
94 SIGNAL data_shaping_R0 : STD_LOGIC;
94 SIGNAL data_shaping_R0 : STD_LOGIC;
95 SIGNAL data_shaping_R1 : STD_LOGIC;
95 SIGNAL data_shaping_R1 : STD_LOGIC;
96 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
96 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
97 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
98 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
99 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
99 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
100 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
100 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
101 SIGNAL enable_f0 : STD_LOGIC;
101 SIGNAL enable_f0 : STD_LOGIC;
102 SIGNAL enable_f1 : STD_LOGIC;
102 SIGNAL enable_f1 : STD_LOGIC;
103 SIGNAL enable_f2 : STD_LOGIC;
103 SIGNAL enable_f2 : STD_LOGIC;
104 SIGNAL enable_f3 : STD_LOGIC;
104 SIGNAL enable_f3 : STD_LOGIC;
105 SIGNAL burst_f0 : STD_LOGIC;
105 SIGNAL burst_f0 : STD_LOGIC;
106 SIGNAL burst_f1 : STD_LOGIC;
106 SIGNAL burst_f1 : STD_LOGIC;
107 SIGNAL burst_f2 : STD_LOGIC;
107 SIGNAL burst_f2 : STD_LOGIC;
108 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112
112
113 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
113 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
114 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
114 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
115 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
115 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
116 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
117 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
117 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
118 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
118 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0);
120 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
120 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
121
121
122
122
123 BEGIN
123 BEGIN
124
124
125 lpp_top_apbreg_1: lpp_top_apbreg
125 ready_matrix_f0_0 <= '0';
126 GENERIC MAP (
126 ready_matrix_f0_1 <= '0';
127 nb_burst_available_size => nb_burst_available_size,
127 ready_matrix_f1 <= '0';
128 nb_snapshot_param_size => nb_snapshot_param_size,
128 ready_matrix_f2 <= '0';
129 delta_snapshot_size => delta_snapshot_size,
129 error_anticipating_empty_fifo <= '0';
130 delta_f2_f0_size => delta_f2_f0_size,
130 error_bad_component_error <= '0';
131 delta_f2_f1_size => delta_f2_f1_size,
131 debug_reg <= (others => '0');
132 pindex => pindex,
132
133 paddr => paddr,
133 lpp_top_apbreg_1: lpp_top_apbreg
134 pmask => pmask,
134 GENERIC MAP (
135 pirq => pirq)
135 nb_burst_available_size => nb_burst_available_size,
136 PORT MAP (
136 nb_snapshot_param_size => nb_snapshot_param_size,
137 HCLK => HCLK,
137 delta_snapshot_size => delta_snapshot_size,
138 HRESETn => HRESETn,
138 delta_f2_f0_size => delta_f2_f0_size,
139 apbi => apbi,
139 delta_f2_f1_size => delta_f2_f1_size,
140 apbo => apbo,
140 pindex => pindex,
141
141 paddr => paddr,
142 ready_matrix_f0_0 => ready_matrix_f0_0,
142 pmask => pmask,
143 ready_matrix_f0_1 => ready_matrix_f0_1,
143 pirq => pirq)
144 ready_matrix_f1 => ready_matrix_f1,
144 PORT MAP (
145 ready_matrix_f2 => ready_matrix_f2,
145 HCLK => HCLK,
146 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
146 HRESETn => HRESETn,
147 error_bad_component_error => error_bad_component_error,
147 apbi => apbi,
148 debug_reg => debug_reg,
148 apbo => apbo,
149 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
149
150 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
150 ready_matrix_f0_0 => ready_matrix_f0_0,
151 status_ready_matrix_f1 => status_ready_matrix_f1,
151 ready_matrix_f0_1 => ready_matrix_f0_1,
152 status_ready_matrix_f2 => status_ready_matrix_f2,
152 ready_matrix_f1 => ready_matrix_f1,
153 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
153 ready_matrix_f2 => ready_matrix_f2,
154 status_error_bad_component_error => status_error_bad_component_error,
154 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
155 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
155 error_bad_component_error => error_bad_component_error,
156 config_active_interruption_onError => config_active_interruption_onError,
156 debug_reg => debug_reg,
157 addr_matrix_f0_0 => addr_matrix_f0_0,
157 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
158 addr_matrix_f0_1 => addr_matrix_f0_1,
158 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
159 addr_matrix_f1 => addr_matrix_f1,
159 status_ready_matrix_f1 => status_ready_matrix_f1,
160 addr_matrix_f2 => addr_matrix_f2,
160 status_ready_matrix_f2 => status_ready_matrix_f2,
161
161 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
162 status_full => status_full,
162 status_error_bad_component_error => status_error_bad_component_error,
163 status_full_ack => status_full_ack,
163 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
164 status_full_err => status_full_err,
164 config_active_interruption_onError => config_active_interruption_onError,
165 status_new_err => status_new_err,
165 addr_matrix_f0_0 => addr_matrix_f0_0,
166 data_shaping_BW => data_shaping_BW,
166 addr_matrix_f0_1 => addr_matrix_f0_1,
167 data_shaping_SP0 => data_shaping_SP0,
167 addr_matrix_f1 => addr_matrix_f1,
168 data_shaping_SP1 => data_shaping_SP1,
168 addr_matrix_f2 => addr_matrix_f2,
169 data_shaping_R0 => data_shaping_R0,
169
170 data_shaping_R1 => data_shaping_R1,
170 status_full => status_full,
171 delta_snapshot => delta_snapshot,
171 status_full_ack => status_full_ack,
172 delta_f2_f1 => delta_f2_f1,
172 status_full_err => status_full_err,
173 delta_f2_f0 => delta_f2_f0,
173 status_new_err => status_new_err,
174 nb_burst_available => nb_burst_available,
174 data_shaping_BW => data_shaping_BW,
175 nb_snapshot_param => nb_snapshot_param,
175 data_shaping_SP0 => data_shaping_SP0,
176 enable_f0 => enable_f0,
176 data_shaping_SP1 => data_shaping_SP1,
177 enable_f1 => enable_f1,
177 data_shaping_R0 => data_shaping_R0,
178 enable_f2 => enable_f2,
178 data_shaping_R1 => data_shaping_R1,
179 enable_f3 => enable_f3,
179 delta_snapshot => delta_snapshot,
180 burst_f0 => burst_f0,
180 delta_f2_f1 => delta_f2_f1,
181 burst_f1 => burst_f1,
181 delta_f2_f0 => delta_f2_f0,
182 burst_f2 => burst_f2,
182 nb_burst_available => nb_burst_available,
183 addr_data_f0 => addr_data_f0,
183 nb_snapshot_param => nb_snapshot_param,
184 addr_data_f1 => addr_data_f1,
184 enable_f0 => enable_f0,
185 addr_data_f2 => addr_data_f2,
185 enable_f1 => enable_f1,
186 addr_data_f3 => addr_data_f3);
186 enable_f2 => enable_f2,
187
187 enable_f3 => enable_f3,
188 lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
188 burst_f0 => burst_f0,
189 GENERIC MAP (
189 burst_f1 => burst_f1,
190 hindex => hindex,
190 burst_f2 => burst_f2,
191 nb_burst_available_size => nb_burst_available_size,
191 addr_data_f0 => addr_data_f0,
192 nb_snapshot_param_size => nb_snapshot_param_size,
192 addr_data_f1 => addr_data_f1,
193 delta_snapshot_size => delta_snapshot_size,
193 addr_data_f2 => addr_data_f2,
194 delta_f2_f0_size => delta_f2_f0_size,
194 addr_data_f3 => addr_data_f3);
195 delta_f2_f1_size => delta_f2_f1_size,
195
196 tech => tech)
196 lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip
197 PORT MAP (
197 GENERIC MAP (
198 cnv_run => cnv_run,
198 hindex => hindex,
199 cnv => cnv,
199 nb_burst_available_size => nb_burst_available_size,
200 sck => sck,
200 nb_snapshot_param_size => nb_snapshot_param_size,
201 sdo => sdo,
201 delta_snapshot_size => delta_snapshot_size,
202 cnv_clk => cnv_clk,
202 delta_f2_f0_size => delta_f2_f0_size,
203 cnv_rstn => cnv_rstn,
203 delta_f2_f1_size => delta_f2_f1_size,
204
204 tech => tech)
205 clk => HCLK,
205 PORT MAP (
206 rstn => HRESETn,
206 cnv_run => cnv_run,
207
207 cnv => cnv,
208 sample_f0_wen => sample_f0_wen,
208 sck => sck,
209 sample_f0_wdata => sample_f0_wdata,
209 sdo => sdo,
210 sample_f1_wen => sample_f1_wen,
210 cnv_clk => cnv_clk,
211 sample_f1_wdata => sample_f1_wdata,
211 cnv_rstn => cnv_rstn,
212 sample_f2_wen => sample_f2_wen,
212
213 sample_f2_wdata => sample_f2_wdata,
213 clk => HCLK,
214 sample_f3_wen => sample_f3_wen,
214 rstn => HRESETn,
215 sample_f3_wdata => sample_f3_wdata,
215
216 AHB_Master_In => AHB_Master_In,
216 sample_f0_wen => sample_f0_wen,
217 AHB_Master_Out => AHB_Master_Out,
217 sample_f0_wdata => sample_f0_wdata,
218 coarse_time_0 => coarse_time_0,
218 sample_f1_wen => sample_f1_wen,
219 data_shaping_SP0 => data_shaping_SP0,
219 sample_f1_wdata => sample_f1_wdata,
220 data_shaping_SP1 => data_shaping_SP1,
220 sample_f2_wen => sample_f2_wen,
221 data_shaping_R0 => data_shaping_R0,
221 sample_f2_wdata => sample_f2_wdata,
222 data_shaping_R1 => data_shaping_R1,
222 sample_f3_wen => sample_f3_wen,
223 delta_snapshot => delta_snapshot,
223 sample_f3_wdata => sample_f3_wdata,
224 delta_f2_f1 => delta_f2_f1,
224 AHB_Master_In => AHB_Master_In,
225 delta_f2_f0 => delta_f2_f0,
225 AHB_Master_Out => AHB_Master_Out,
226 enable_f0 => enable_f0,
226 coarse_time_0 => coarse_time_0,
227 enable_f1 => enable_f1,
227 data_shaping_SP0 => data_shaping_SP0,
228 enable_f2 => enable_f2,
228 data_shaping_SP1 => data_shaping_SP1,
229 enable_f3 => enable_f3,
229 data_shaping_R0 => data_shaping_R0,
230 burst_f0 => burst_f0,
230 data_shaping_R1 => data_shaping_R1,
231 burst_f1 => burst_f1,
231 delta_snapshot => delta_snapshot,
232 burst_f2 => burst_f2,
232 delta_f2_f1 => delta_f2_f1,
233 nb_burst_available => nb_burst_available,
233 delta_f2_f0 => delta_f2_f0,
234 nb_snapshot_param => nb_snapshot_param,
234 enable_f0 => enable_f0,
235 status_full => status_full,
235 enable_f1 => enable_f1,
236 status_full_ack => status_full_ack,
236 enable_f2 => enable_f2,
237 status_full_err => status_full_err,
237 enable_f3 => enable_f3,
238 status_new_err => status_new_err,
238 burst_f0 => burst_f0,
239 addr_data_f0 => addr_data_f0,
239 burst_f1 => burst_f1,
240 addr_data_f1 => addr_data_f1,
240 burst_f2 => burst_f2,
241 addr_data_f2 => addr_data_f2,
241 nb_burst_available => nb_burst_available,
242 addr_data_f3 => addr_data_f3);
242 nb_snapshot_param => nb_snapshot_param,
243 END tb;
243 status_full => status_full,
244 status_full_ack => status_full_ack,
245 status_full_err => status_full_err,
246 status_new_err => status_new_err,
247 addr_data_f0 => addr_data_f0,
248 addr_data_f1 => addr_data_f1,
249 addr_data_f2 => addr_data_f2,
250 addr_data_f3 => addr_data_f3);
251 END tb; No newline at end of file
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1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_waveform_dma IS
45 ENTITY lpp_waveform_dma IS
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER := 160;
47 data_size : INTEGER := 160;
48 tech : INTEGER := inferred;
48 tech : INTEGER := inferred;
49 hindex : INTEGER := 2;
49 hindex : INTEGER := 2;
50 nb_burst_available_size : INTEGER := 11
50 nb_burst_available_size : INTEGER := 11
51 );
51 );
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 -- Reg
64 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
69 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
73 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
74 );
74 );
75 END;
75 END;
76
76
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
77 ARCHITECTURE Behavioral OF lpp_waveform_dma IS
78 -----------------------------------------------------------------------------
78 -----------------------------------------------------------------------------
79 SIGNAL DMAIn : DMA_In_Type;
79 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
82 TYPE state_DMAWriteBurst IS (IDLE,
83 SEND_TIME_0, WAIT_TIME_0,
83 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
84 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
85 SEND_5_TIME,
86 SEND_DATA, WAIT_DATA);
86 SEND_DATA, WAIT_DATA);
87 SIGNAL state : state_DMAWriteBurst := IDLE;
87 SIGNAL state : state_DMAWriteBurst;
88 -----------------------------------------------------------------------------
88 -----------------------------------------------------------------------------
89 -- CONTROL
89 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
93 SIGNAL time_select : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
96 SIGNAL time_already_send_s : STD_LOGIC;
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 -- SEND TIME MODULE
98 -- SEND TIME MODULE
99 SIGNAL time_dmai : DMA_In_Type;
99 SIGNAL time_dmai : DMA_In_Type;
100 SIGNAL time_send : STD_LOGIC;
100 SIGNAL time_send : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
101 SIGNAL time_send_ok : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
102 SIGNAL time_send_ko : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
103 SIGNAL time_fifo_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
104 SIGNAL time_ren : STD_LOGIC;
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 -- SEND DATA MODULE
106 -- SEND DATA MODULE
107 SIGNAL data_dmai : DMA_In_Type;
107 SIGNAL data_dmai : DMA_In_Type;
108 SIGNAL data_send : STD_LOGIC;
108 SIGNAL data_send : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
109 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
114 -- SELECT ADDRESS
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
116 SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
117 SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
118 SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0);
120 SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0);
121 SIGNAL count_send_time : INTEGER;
121 SIGNAL count_send_time : INTEGER;
122 BEGIN
122 BEGIN
123
123
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 -- DMA to AHB interface
125 -- DMA to AHB interface
126 DMA2AHB_1 : DMA2AHB
126 DMA2AHB_1 : DMA2AHB
127 GENERIC MAP (
127 GENERIC MAP (
128 hindex => hindex,
128 hindex => hindex,
129 vendorid => VENDOR_LPP,
129 vendorid => VENDOR_LPP,
130 deviceid => 0,
130 deviceid => 10,
131 version => 0,
131 version => 0,
132 syncrst => 1,
132 syncrst => 1,
133 boundary => 1) -- FIX 11/01/2013
133 boundary => 1) -- FIX 11/01/2013
134 PORT MAP (
134 PORT MAP (
135 HCLK => HCLK,
135 HCLK => HCLK,
136 HRESETn => HRESETn,
136 HRESETn => HRESETn,
137 DMAIn => DMAIn,
137 DMAIn => DMAIn,
138 DMAOut => DMAOut,
138 DMAOut => DMAOut,
139 AHBIn => AHB_Master_In,
139 AHBIn => AHB_Master_In,
140 AHBOut => AHB_Master_Out);
140 AHBOut => AHB_Master_Out);
141 -----------------------------------------------------------------------------
141 -----------------------------------------------------------------------------
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- This module memorises when the Times info are write. When FSM send
144 -- This module memorises when the Times info are write. When FSM send
145 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
145 -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset.
146 all_time_write: FOR I IN 3 DOWNTO 0 GENERATE
146 all_time_write: FOR I IN 3 DOWNTO 0 GENERATE
147 PROCESS (HCLK, HRESETn)
147 PROCESS (HCLK, HRESETn)
148 BEGIN -- PROCESS
148 BEGIN -- PROCESS
149 IF HRESETn = '0' THEN -- asynchronous reset (active low)
149 IF HRESETn = '0' THEN -- asynchronous reset (active low)
150 time_already_send(I) <= '0';
150 time_already_send(I) <= '0';
151 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
151 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
152 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
152 IF time_write = '1' AND UNSIGNED(sel_data) = I THEN
153 time_already_send(I) <= '1';
153 time_already_send(I) <= '1';
154 ELSIF status_full_ack(I) = '1' THEN
154 ELSIF status_full_ack(I) = '1' THEN
155 time_already_send(I) <= '0';
155 time_already_send(I) <= '0';
156 END IF;
156 END IF;
157 END IF;
157 END IF;
158 END PROCESS;
158 END PROCESS;
159 END GENERATE all_time_write;
159 END GENERATE all_time_write;
160
160
161 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
162 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
162 sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE
163 "01" WHEN data_ready(1) = '1' ELSE
163 "01" WHEN data_ready(1) = '1' ELSE
164 "10" WHEN data_ready(2) = '1' ELSE
164 "10" WHEN data_ready(2) = '1' ELSE
165 "11";
165 "11";
166
166
167 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
167 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
168 time_already_send(1) WHEN data_ready(1) = '1' ELSE
168 time_already_send(1) WHEN data_ready(1) = '1' ELSE
169 time_already_send(2) WHEN data_ready(2) = '1' ELSE
169 time_already_send(2) WHEN data_ready(2) = '1' ELSE
170 time_already_send(3);
170 time_already_send(3);
171
171
172 -- DMA control
172 -- DMA control
173 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
173 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
174 BEGIN -- PROCESS DMAWriteBurst_p
174 BEGIN -- PROCESS DMAWriteBurst_p
175 IF HRESETn = '0' THEN
175 IF HRESETn = '0' THEN
176 state <= IDLE;
176 state <= IDLE;
177
177
178 sel_data <= "00";
178 sel_data <= "00";
179 update <= "00";
179 update <= "00";
180 time_select <= '0';
180 time_select <= '0';
181 time_fifo_ren <= '1';
181 time_fifo_ren <= '1';
182 data_send <= '0';
182 data_send <= '0';
183 time_send <= '0';
183 time_send <= '0';
184 time_write <= '0';
184 time_write <= '0';
185 send_16_3_time <= "001";
185 send_16_3_time <= "001";
186
186
187 ELSIF HCLK'EVENT AND HCLK = '1' THEN
187 ELSIF HCLK'EVENT AND HCLK = '1' THEN
188
188
189 CASE state IS
189 CASE state IS
190 WHEN IDLE =>
190 WHEN IDLE =>
191 count_send_time <= 0;
191 count_send_time <= 0;
192 sel_data <= "00";
192 sel_data <= "00";
193 update <= "00";
193 update <= "00";
194 time_select <= '0';
194 time_select <= '0';
195 time_fifo_ren <= '1';
195 time_fifo_ren <= '1';
196 data_send <= '0';
196 data_send <= '0';
197 time_send <= '0';
197 time_send <= '0';
198 time_write <= '0';
198 time_write <= '0';
199
199
200 IF data_ready = "0000" THEN
200 IF data_ready = "0000" THEN
201 state <= IDLE;
201 state <= IDLE;
202 ELSE
202 ELSE
203 sel_data <= sel_data_s;
203 sel_data <= sel_data_s;
204 send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2);
204 send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2);
205 IF send_16_3_time(0) = '1' THEN
205 IF send_16_3_time(0) = '1' THEN
206 state <= SEND_TIME_0;
206 state <= SEND_TIME_0;
207 ELSE
207 ELSE
208 state <= SEND_5_TIME;
208 state <= SEND_5_TIME;
209 END IF;
209 END IF;
210 END IF;
210 END IF;
211
211
212 WHEN SEND_TIME_0 =>
212 WHEN SEND_TIME_0 =>
213 time_select <= '1';
213 time_select <= '1';
214 IF time_already_send_s = '0' THEN
214 IF time_already_send_s = '0' THEN
215 time_send <= '1';
215 time_send <= '1';
216 state <= WAIT_TIME_0;
216 state <= WAIT_TIME_0;
217 ELSE
217 ELSE
218 time_send <= '0';
218 time_send <= '0';
219 state <= SEND_TIME_1;
219 state <= SEND_TIME_1;
220 END IF;
220 END IF;
221 time_fifo_ren <= '0';
221 time_fifo_ren <= '0';
222
222
223 WHEN WAIT_TIME_0 =>
223 WHEN WAIT_TIME_0 =>
224 time_fifo_ren <= '1';
224 time_fifo_ren <= '1';
225 update <= "00";
225 update <= "00";
226 time_send <= '0';
226 time_send <= '0';
227 IF time_send_ok = '1' OR time_send_ko = '1' THEN
227 IF time_send_ok = '1' OR time_send_ko = '1' THEN
228 update <= "01";
228 update <= "01";
229 state <= SEND_TIME_1;
229 state <= SEND_TIME_1;
230 END IF;
230 END IF;
231
231
232 WHEN SEND_TIME_1 =>
232 WHEN SEND_TIME_1 =>
233 time_select <= '1';
233 time_select <= '1';
234 IF time_already_send_s = '0' THEN
234 IF time_already_send_s = '0' THEN
235 time_send <= '1';
235 time_send <= '1';
236 state <= WAIT_TIME_1;
236 state <= WAIT_TIME_1;
237 ELSE
237 ELSE
238 time_send <= '0';
238 time_send <= '0';
239 state <= SEND_5_TIME;
239 state <= SEND_5_TIME;
240 END IF;
240 END IF;
241 time_fifo_ren <= '0';
241 time_fifo_ren <= '0';
242
242
243 WHEN WAIT_TIME_1 =>
243 WHEN WAIT_TIME_1 =>
244 time_fifo_ren <= '1';
244 time_fifo_ren <= '1';
245 update <= "00";
245 update <= "00";
246 time_send <= '0';
246 time_send <= '0';
247 IF time_send_ok = '1' OR time_send_ko = '1' THEN
247 IF time_send_ok = '1' OR time_send_ko = '1' THEN
248 time_write <= '1';
248 time_write <= '1';
249 update <= "01";
249 update <= "01";
250 state <= SEND_5_TIME;
250 state <= SEND_5_TIME;
251 END IF;
251 END IF;
252
252
253 WHEN SEND_5_TIME =>
253 WHEN SEND_5_TIME =>
254 update <= "00";
254 update <= "00";
255 time_select <= '1';
255 time_select <= '1';
256 time_fifo_ren <= '0';
256 time_fifo_ren <= '0';
257 count_send_time <= count_send_time + 1;
257 count_send_time <= count_send_time + 1;
258 IF count_send_time = 10 THEN
258 IF count_send_time = 10 THEN
259 state <= SEND_DATA;
259 state <= SEND_DATA;
260 END IF;
260 END IF;
261
261
262 WHEN SEND_DATA =>
262 WHEN SEND_DATA =>
263 time_fifo_ren <= '1';
263 time_fifo_ren <= '1';
264 time_write <= '0';
264 time_write <= '0';
265 time_send <= '0';
265 time_send <= '0';
266
266
267 time_select <= '0';
267 time_select <= '0';
268 data_send <= '1';
268 data_send <= '1';
269 update <= "00";
269 update <= "00";
270 state <= WAIT_DATA;
270 state <= WAIT_DATA;
271
271
272 WHEN WAIT_DATA =>
272 WHEN WAIT_DATA =>
273 data_send <= '0';
273 data_send <= '0';
274
274
275 IF data_send_ok = '1' OR data_send_ko = '1' THEN
275 IF data_send_ok = '1' OR data_send_ko = '1' THEN
276 state <= IDLE;
276 state <= IDLE;
277 update <= "10";
277 update <= "10";
278 END IF;
278 END IF;
279
279
280 WHEN OTHERS => NULL;
280 WHEN OTHERS => NULL;
281 END CASE;
281 END CASE;
282
282
283 END IF;
283 END IF;
284 END PROCESS DMAWriteFSM_p;
284 END PROCESS DMAWriteFSM_p;
285 -----------------------------------------------------------------------------
285 -----------------------------------------------------------------------------
286
286
287
287
288
288
289 -----------------------------------------------------------------------------
289 -----------------------------------------------------------------------------
290 -- SEND 1 word by DMA
290 -- SEND 1 word by DMA
291 -----------------------------------------------------------------------------
291 -----------------------------------------------------------------------------
292 lpp_dma_send_1word_1 : lpp_dma_send_1word
292 lpp_dma_send_1word_1 : lpp_dma_send_1word
293 PORT MAP (
293 PORT MAP (
294 HCLK => HCLK,
294 HCLK => HCLK,
295 HRESETn => HRESETn,
295 HRESETn => HRESETn,
296 DMAIn => time_dmai,
296 DMAIn => time_dmai,
297 DMAOut => DMAOut,
297 DMAOut => DMAOut,
298
298
299 send => time_send,
299 send => time_send,
300 address => data_address,
300 address => data_address,
301 data => data,
301 data => data,
302 send_ok => time_send_ok,
302 send_ok => time_send_ok,
303 send_ko => time_send_ko
303 send_ko => time_send_ko
304 );
304 );
305
305
306 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
307 -- SEND 16 word by DMA (in burst mode)
307 -- SEND 16 word by DMA (in burst mode)
308 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
309 lpp_dma_send_16word_1 : lpp_dma_send_16word
309 lpp_dma_send_16word_1 : lpp_dma_send_16word
310 PORT MAP (
310 PORT MAP (
311 HCLK => HCLK,
311 HCLK => HCLK,
312 HRESETn => HRESETn,
312 HRESETn => HRESETn,
313 DMAIn => data_dmai,
313 DMAIn => data_dmai,
314 DMAOut => DMAOut,
314 DMAOut => DMAOut,
315
315
316 send => data_send,
316 send => data_send,
317 address => data_address,
317 address => data_address,
318 data => data,
318 data => data,
319 ren => data_fifo_ren,
319 ren => data_fifo_ren,
320 send_ok => data_send_ok,
320 send_ok => data_send_ok,
321 send_ko => data_send_ko);
321 send_ko => data_send_ko);
322
322
323 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
323 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
324 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
324 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
325 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
325 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
326
326
327 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
327 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
328 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
328 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
329 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
329 data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
330 END GENERATE all_data_ren;
330 END GENERATE all_data_ren;
331
331
332 -----------------------------------------------------------------------------
332 -----------------------------------------------------------------------------
333 -- SELECT ADDRESS
333 -- SELECT ADDRESS
334 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
334 addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0;
335
335
336 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
336 gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE
337
337
338 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
338 update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00";
339
339
340 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
340 lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress
341 GENERIC MAP (
341 GENERIC MAP (
342 nb_burst_available_size => nb_burst_available_size)
342 nb_burst_available_size => nb_burst_available_size)
343 PORT MAP (
343 PORT MAP (
344 HCLK => HCLK,
344 HCLK => HCLK,
345 HRESETn => HRESETn,
345 HRESETn => HRESETn,
346 update => update_and_sel((2*I)+1 DOWNTO 2*I),
346 update => update_and_sel((2*I)+1 DOWNTO 2*I),
347 nb_burst_available => nb_burst_available,
347 nb_burst_available => nb_burst_available,
348 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
348 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
349 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
349 addr_data => addr_data_vector(32*I+31 DOWNTO 32*I),
350 status_full => status_full(I),
350 status_full => status_full(I),
351 status_full_ack => status_full_ack(I),
351 status_full_ack => status_full_ack(I),
352 status_full_err => status_full_err(I));
352 status_full_err => status_full_err(I));
353
353
354 END GENERATE gen_select_address;
354 END GENERATE gen_select_address;
355
355
356 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
356 data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE
357 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
357 addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE
358 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
358 addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE
359 addr_data_vector(32*3+31 DOWNTO 32*3);
359 addr_data_vector(32*3+31 DOWNTO 32*3);
360 -----------------------------------------------------------------------------
360 -----------------------------------------------------------------------------
361
361
362
362
363 END Behavioral;
363 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,116 +1,114
1 LIBRARY IEEE;
1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 ENTITY lpp_waveform_snapshot_controler IS
5 ENTITY lpp_waveform_snapshot_controler IS
6
6
7 GENERIC (
7 GENERIC (
8 delta_snapshot_size : INTEGER := 16;
8 delta_snapshot_size : INTEGER := 16;
9 delta_f2_f0_size : INTEGER := 10;
9 delta_f2_f0_size : INTEGER := 10;
10 delta_f2_f1_size : INTEGER := 10);
10 delta_f2_f1_size : INTEGER := 10);
11
11
12 PORT (
12 PORT (
13 clk : IN STD_LOGIC;
13 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
15 --config
15 --config
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
19
19
20 --input
20 --input
21 coarse_time_0 : IN STD_LOGIC;
21 coarse_time_0 : IN STD_LOGIC;
22 data_f0_in_valid : IN STD_LOGIC;
22 data_f0_in_valid : IN STD_LOGIC;
23 data_f2_in_valid : IN STD_LOGIC;
23 data_f2_in_valid : IN STD_LOGIC;
24 --output
24 --output
25 start_snapshot_f0 : OUT STD_LOGIC;
25 start_snapshot_f0 : OUT STD_LOGIC;
26 start_snapshot_f1 : OUT STD_LOGIC;
26 start_snapshot_f1 : OUT STD_LOGIC;
27 start_snapshot_f2 : OUT STD_LOGIC
27 start_snapshot_f2 : OUT STD_LOGIC
28 );
28 );
29
29
30 END lpp_waveform_snapshot_controler;
30 END lpp_waveform_snapshot_controler;
31
31
32 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
32 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
33 SIGNAL counter_delta_snapshot : INTEGER;
33 SIGNAL counter_delta_snapshot : INTEGER;
34 SIGNAL counter_delta_f0 : INTEGER;
34 SIGNAL counter_delta_f0 : INTEGER;
35
35
36 SIGNAL coarse_time_0_r : STD_LOGIC;
36 SIGNAL coarse_time_0_r : STD_LOGIC;
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
39 SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC;
39 BEGIN -- beh
40 BEGIN -- beh
40
41
41 PROCESS (clk, rstn)
42 PROCESS (clk, rstn)
42 BEGIN
43 BEGIN
43 IF rstn = '0' THEN
44 IF rstn = '0' THEN
44 start_snapshot_f0 <= '0';
45 start_snapshot_f0 <= '0';
45 start_snapshot_f1 <= '0';
46 start_snapshot_f1 <= '0';
46 start_snapshot_f2 <= '0';
47 start_snapshot_f2 <= '0';
47 counter_delta_snapshot <= 0;
48 counter_delta_snapshot <= 0;
48 counter_delta_f0 <= 0;
49 counter_delta_f0 <= 0;
49 coarse_time_0_r <= '0';
50 coarse_time_0_r <= '0';
50 start_snapshot_f2_temp <= '0';
51 start_snapshot_f2_temp <= '0';
51 start_snapshot_fothers_temp <= '0';
52 start_snapshot_fothers_temp <= '0';
52 ELSIF clk'EVENT AND clk = '1' THEN
53 start_snapshot_fothers_temp2 <= '0';
53 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
54 ELSIF clk'EVENT AND clk = '1' THEN
54 start_snapshot_f2_temp <= '1';
55 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
55 ELSE
56 start_snapshot_f2_temp <= '1';
56 start_snapshot_f2_temp <= '0';
57 ELSE
57 END IF;
58 start_snapshot_f2_temp <= '0';
58 -------------------------------------------------------------------------
59 END IF;
59 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
60 -------------------------------------------------------------------------
60 start_snapshot_f2 <= '1';
61 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
61 ELSE
62 start_snapshot_f2 <= '1';
62 start_snapshot_f2 <= '0';
63 ELSE
63 END IF;
64 start_snapshot_f2 <= '0';
64 -------------------------------------------------------------------------
65 END IF;
65 coarse_time_0_r <= coarse_time_0;
66 -------------------------------------------------------------------------
66 IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN
67 coarse_time_0_r <= coarse_time_0;
67 IF counter_delta_snapshot = 0 THEN
68 IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN
68 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
69 IF counter_delta_snapshot = 0 THEN
69 ELSE
70 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
70 counter_delta_snapshot <= counter_delta_snapshot - 1;
71 ELSE
71 END IF;
72 counter_delta_snapshot <= counter_delta_snapshot - 1;
72 END IF;
73 END IF;
73
74 END IF;
74
75
75 -------------------------------------------------------------------------
76
76
77 -------------------------------------------------------------------------
77
78
78
79
79 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
80
80 start_snapshot_f1 <= '1';
81 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
81 ELSE
82 start_snapshot_f1 <= '1';
82 start_snapshot_f1 <= '0';
83 ELSE
83 END IF;
84 start_snapshot_f1 <= '0';
84
85 END IF;
85 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
86
86 start_snapshot_f0 <= '1';
87 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
87 ELSE
88 start_snapshot_f0 <= '1';
88 start_snapshot_f0 <= '0';
89 ELSE
89 END IF;
90 start_snapshot_f0 <= '0';
90
91 END IF;
91 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
92
92 AND start_snapshot_f2_temp = '0'
93 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
93 THEN --
94 AND start_snapshot_f2_temp = '0'
94 start_snapshot_fothers_temp <= '1';
95 THEN --
95 ELSIF counter_delta_f0 > 0 THEN
96 start_snapshot_fothers_temp <= '1';
96 start_snapshot_fothers_temp <= '0';
97 ELSIF counter_delta_f0 > 0 THEN
97 END IF;
98 start_snapshot_fothers_temp <= '0';
98
99 END IF;
99
100
100 -------------------------------------------------------------------------
101
101 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
102 -------------------------------------------------------------------------
102 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
103 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
103 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
104 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
104 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
105 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
105 ELSE
106 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
106 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
107 ELSE
107 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
108 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
108 END IF;
109 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
109 END IF;
110 END IF;
110 -------------------------------------------------------------------------
111 END IF;
111 END IF;
112 -------------------------------------------------------------------------
112 END PROCESS;
113 END IF;
113
114 END PROCESS;
114 END beh; No newline at end of file
115
116 END beh;
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