diff --git a/lib/lpp/dirs.txt b/lib/lpp/dirs.txt --- a/lib/lpp/dirs.txt +++ b/lib/lpp/dirs.txt @@ -1,11 +1,11 @@ ./amba_lcd_16x2_ctrlr -./dsp/iir_filter -./dsp/lpp_downsampling -./dsp/lpp_fft ./general_purpose ./general_purpose/lpp_AMR ./general_purpose/lpp_balise ./general_purpose/lpp_delay +./dsp/iir_filter +./dsp/lpp_downsampling +./dsp/lpp_fft ./lfr_time_management ./lpp_ad_Conv ./lpp_amba diff --git a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd --- a/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd +++ b/lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd @@ -1,120 +1,120 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr ----------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_1164.ALL; -LIBRARY lpp; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.general_purpose.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - -ENTITY RAM_CTRLR_v2 IS - GENERIC( - tech : INTEGER := 0; - Input_SZ_1 : INTEGER := 16; - Mem_use : INTEGER := use_RAM - ); - PORT( - rstn : IN STD_LOGIC; - clk : IN STD_LOGIC; - -- R/W Ctrl - ram_write : IN STD_LOGIC; - ram_read : IN STD_LOGIC; - -- ADDR Ctrl - raddr_rst : IN STD_LOGIC; - raddr_add1 : IN STD_LOGIC; - waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); - -- Data - sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) - ); -END RAM_CTRLR_v2; - - -ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS - - SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); - SIGNAL WEN, REN : STD_LOGIC; - SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); - -BEGIN - - sample_out <= RD(Input_SZ_1-1 DOWNTO 0); - WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; - ----------------------------------------------------------------------------- - -- RAM - ----------------------------------------------------------------------------- - - memCEL : IF Mem_use = use_CEL GENERATE - WEN <= NOT ram_write; - REN <= NOT ram_read; - RAMblk : RAM_CEL_N - GENERIC MAP(Input_SZ_1) - PORT MAP( - WD => WD, - RD => RD, - WEN => WEN, - REN => REN, - WADDR => WADDR, - RADDR => RADDR, - RWCLK => clk, - RESET => rstn - ) ; - END GENERATE; - - memRAM : IF Mem_use = use_RAM GENERATE - SRAM : syncram_2p - GENERIC MAP(tech, 8, Input_SZ_1) - PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); - END GENERATE; - - ----------------------------------------------------------------------------- - -- RADDR - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN -- asynchronous reset (active low) - counter <= (OTHERS => '0'); - ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge - IF raddr_rst = '1' THEN - counter <= (OTHERS => '0'); - ELSIF raddr_add1 = '1' THEN - counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); - END IF; - END IF; - END PROCESS; - RADDR <= counter; - - ----------------------------------------------------------------------------- - -- WADDR - ----------------------------------------------------------------------------- - WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE - STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE - STD_LOGIC_VECTOR(UNSIGNED(counter)); - - -END ar_RAM_CTRLR_v2; +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +---------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_1164.ALL; +LIBRARY lpp; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.general_purpose.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + +ENTITY RAM_CTRLR_v2 IS + GENERIC( + tech : INTEGER := 0; + Input_SZ_1 : INTEGER := 16; + Mem_use : INTEGER := use_RAM + ); + PORT( + rstn : IN STD_LOGIC; + clk : IN STD_LOGIC; + -- R/W Ctrl + ram_write : IN STD_LOGIC; + ram_read : IN STD_LOGIC; + -- ADDR Ctrl + raddr_rst : IN STD_LOGIC; + raddr_add1 : IN STD_LOGIC; + waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + -- Data + sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0) + ); +END RAM_CTRLR_v2; + + +ARCHITECTURE ar_RAM_CTRLR_v2 OF RAM_CTRLR_v2 IS + + SIGNAL WD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL RD : STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); + SIGNAL WEN, REN : STD_LOGIC; + SIGNAL RADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL WADDR : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL counter : STD_LOGIC_VECTOR(7 DOWNTO 0); + +BEGIN + + sample_out <= RD(Input_SZ_1-1 DOWNTO 0); + WD(Input_SZ_1-1 DOWNTO 0) <= sample_in; + ----------------------------------------------------------------------------- + -- RAM + ----------------------------------------------------------------------------- + + memCEL : IF Mem_use = use_CEL GENERATE + WEN <= NOT ram_write; + REN <= NOT ram_read; + RAMblk : RAM_CEL_N + GENERIC MAP(Input_SZ_1) + PORT MAP( + WD => WD, + RD => RD, + WEN => WEN, + REN => REN, + WADDR => WADDR, + RADDR => RADDR, + RWCLK => clk, + RESET => rstn + ) ; + END GENERATE; + + memRAM : IF Mem_use = use_RAM GENERATE + SRAM : syncram_2p + GENERIC MAP(tech, 8, Input_SZ_1) + PORT MAP(clk, ram_read, RADDR, RD, clk, ram_write, WADDR, WD); + END GENERATE; + + ----------------------------------------------------------------------------- + -- RADDR + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + counter <= (OTHERS => '0'); + ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge + IF raddr_rst = '1' THEN + counter <= (OTHERS => '0'); + ELSIF raddr_add1 = '1' THEN + counter <= STD_LOGIC_VECTOR(UNSIGNED(counter)+1); + END IF; + END IF; + END PROCESS; + RADDR <= counter; + + ----------------------------------------------------------------------------- + -- WADDR + ----------------------------------------------------------------------------- + WADDR <= STD_LOGIC_VECTOR(UNSIGNED(counter)-2) WHEN waddr_previous = "10" ELSE + STD_LOGIC_VECTOR(UNSIGNED(counter)-1) WHEN waddr_previous = "01" ELSE + STD_LOGIC_VECTOR(UNSIGNED(counter)); + + +END ar_RAM_CTRLR_v2; \ No newline at end of file diff --git a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd --- a/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd +++ b/lib/lpp/lfr_time_management/apb_lfr_time_management.vhd @@ -164,11 +164,11 @@ BEGIN END IF; END IF; - apbo.pconfig <= pconfig; END PROCESS; - apbo.prdata <= Rdata WHEN apbi.penable = '1'; + apbo.prdata <= Rdata ;--WHEN apbi.penable = '1'; coarse_time <= r.coarse_time; fine_time <= r.fine_time; + apbo.pconfig <= pconfig; -END Behavioral; +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd --- a/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd +++ b/lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd @@ -1,197 +1,196 @@ ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Alexis Jeandet --- Mail : alexis.jeandet@lpp.polytechnique.fr -------------------------------------------------------------------------------- --- MODIFIED by Jean-christophe PELLION --- jean-christophe.pellion@lpp.polytechnique.fr -------------------------------------------------------------------------------- -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.general_purpose.SYNC_FF; - -ENTITY AD7688_drvr IS - GENERIC( - ChanelCount : INTEGER; - ncycle_cnv_high : INTEGER := 79; - ncycle_cnv : INTEGER := 500); - PORT ( - -- CONV -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - - -- DATA -- - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); - - sample : OUT Samples(ChanelCount-1 DOWNTO 0); - sample_val : OUT STD_LOGIC - ); -END AD7688_drvr; - -ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS - - COMPONENT SYNC_FF - GENERIC ( - NB_FF_OF_SYNC : INTEGER); - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - A : IN STD_LOGIC; - A_sync : OUT STD_LOGIC); - END COMPONENT; - - - SIGNAL cnv_cycle_counter : INTEGER; - SIGNAL cnv_s : STD_LOGIC; - SIGNAL cnv_sync : STD_LOGIC; - SIGNAL cnv_sync_r : STD_LOGIC; - SIGNAL cnv_done : STD_LOGIC; - SIGNAL sample_bit_counter : INTEGER; - SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); - - SIGNAL cnv_run_sync : STD_LOGIC; - -BEGIN - ----------------------------------------------------------------------------- - -- CONV - ----------------------------------------------------------------------------- - PROCESS (cnv_clk, cnv_rstn) - BEGIN -- PROCESS - IF cnv_rstn = '0' THEN -- asynchronous reset (active low) - cnv_cycle_counter <= 0; - cnv_s <= '0'; - ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge - IF cnv_run = '1' THEN - IF cnv_cycle_counter < ncycle_cnv THEN - cnv_cycle_counter <= cnv_cycle_counter +1; - IF cnv_cycle_counter < ncycle_cnv_high THEN - cnv_s <= '1'; - ELSE - cnv_s <= '0'; - END IF; - ELSE - cnv_s <= '1'; - cnv_cycle_counter <= 0; - END IF; - ELSE - cnv_s <= '0'; - cnv_cycle_counter <= 0; - END IF; - END IF; - END PROCESS; - - cnv <= cnv_s; - - ----------------------------------------------------------------------------- - - - ----------------------------------------------------------------------------- - -- SYNC CNV - ----------------------------------------------------------------------------- - - SYNC_FF_cnv : SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - A => cnv_s, - A_sync => cnv_sync); - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - cnv_sync_r <= '0'; - cnv_done <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - cnv_sync_r <= cnv_sync; - cnv_done <= (NOT cnv_sync) AND cnv_sync_r; - END IF; - END PROCESS; - - ----------------------------------------------------------------------------- - - SYNC_FF_run : SYNC_FF - GENERIC MAP ( - NB_FF_OF_SYNC => 2) - PORT MAP ( - clk => clk, - rstn => rstn, - A => cnv_run, - A_sync => cnv_run_sync); - - - - ----------------------------------------------------------------------------- - -- DATA - ----------------------------------------------------------------------------- - PROCESS (clk, rstn) - BEGIN -- PROCESS - IF rstn = '0' THEN - FOR l IN 0 TO ChanelCount-1 LOOP - shift_reg(l) <= (OTHERS => '0'); - END LOOP; - sample_bit_counter <= 0; - sample_val <= '0'; - SCK <= '1'; - ELSIF clk'EVENT AND clk = '1' THEN - - IF cnv_run_sync = '0' THEN - sample_bit_counter <= 0; - ELSIF cnv_done = '1' THEN - sample_bit_counter <= 1; - ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN - sample_bit_counter <= sample_bit_counter + 1; - END IF; - - IF (sample_bit_counter MOD 2) = 1 THEN - FOR l IN 0 TO ChanelCount-1 LOOP - --shift_reg(l)(15) <= sdo(l); - --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); - shift_reg(l)(0) <= sdo(l); - shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); - END LOOP; - SCK <= '0'; - ELSE - SCK <= '1'; - END IF; - - IF sample_bit_counter = 31 THEN - sample_val <= '1'; - FOR l IN 0 TO ChanelCount-1 LOOP - --sample(l)(15) <= sdo(l); - --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); - sample(l)(0) <= sdo(l); - sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); - END LOOP; - ELSE - sample_val <= '0'; - END IF; - END IF; - END PROCESS; - -END ar_AD7688_drvr; - +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Alexis Jeandet +-- Mail : alexis.jeandet@lpp.polytechnique.fr +------------------------------------------------------------------------------- +-- MODIFIED by Jean-christophe PELLION +-- jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.general_purpose.SYNC_FF; + +ENTITY AD7688_drvr IS + GENERIC( + ChanelCount : INTEGER; + ncycle_cnv_high : INTEGER := 79; + ncycle_cnv : INTEGER := 500); + PORT ( + -- CONV -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + + -- DATA -- + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0); + + sample : OUT Samples(ChanelCount-1 DOWNTO 0); + sample_val : OUT STD_LOGIC + ); +END AD7688_drvr; + +ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS + + COMPONENT SYNC_FF + GENERIC ( + NB_FF_OF_SYNC : INTEGER); + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + A : IN STD_LOGIC; + A_sync : OUT STD_LOGIC); + END COMPONENT; + + + SIGNAL cnv_cycle_counter : INTEGER; + SIGNAL cnv_s : STD_LOGIC; + SIGNAL cnv_sync : STD_LOGIC; + SIGNAL cnv_sync_r : STD_LOGIC; + SIGNAL cnv_done : STD_LOGIC; + SIGNAL sample_bit_counter : INTEGER; + SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0); + + SIGNAL cnv_run_sync : STD_LOGIC; + +BEGIN + ----------------------------------------------------------------------------- + -- CONV + ----------------------------------------------------------------------------- + PROCESS (cnv_clk, cnv_rstn) + BEGIN -- PROCESS + IF cnv_rstn = '0' THEN -- asynchronous reset (active low) + cnv_cycle_counter <= 0; + cnv_s <= '0'; + ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge + IF cnv_run = '1' THEN + IF cnv_cycle_counter < ncycle_cnv THEN + cnv_cycle_counter <= cnv_cycle_counter +1; + IF cnv_cycle_counter < ncycle_cnv_high THEN + cnv_s <= '1'; + ELSE + cnv_s <= '0'; + END IF; + ELSE + cnv_s <= '1'; + cnv_cycle_counter <= 0; + END IF; + ELSE + cnv_s <= '0'; + cnv_cycle_counter <= 0; + END IF; + END IF; + END PROCESS; + + cnv <= cnv_s; + + ----------------------------------------------------------------------------- + + + ----------------------------------------------------------------------------- + -- SYNC CNV + ----------------------------------------------------------------------------- + + SYNC_FF_cnv : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_s, + A_sync => cnv_sync); + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + cnv_sync_r <= '0'; + cnv_done <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + cnv_sync_r <= cnv_sync; + cnv_done <= (NOT cnv_sync) AND cnv_sync_r; + END IF; + END PROCESS; + + ----------------------------------------------------------------------------- + + SYNC_FF_run : SYNC_FF + GENERIC MAP ( + NB_FF_OF_SYNC => 2) + PORT MAP ( + clk => clk, + rstn => rstn, + A => cnv_run, + A_sync => cnv_run_sync); + + + + ----------------------------------------------------------------------------- + -- DATA + ----------------------------------------------------------------------------- + PROCESS (clk, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN + FOR l IN 0 TO ChanelCount-1 LOOP + shift_reg(l) <= (OTHERS => '0'); + END LOOP; + sample_bit_counter <= 0; + sample_val <= '0'; + SCK <= '1'; + ELSIF clk'EVENT AND clk = '1' THEN + + IF cnv_run_sync = '0' THEN + sample_bit_counter <= 0; + ELSIF cnv_done = '1' THEN + sample_bit_counter <= 1; + ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN + sample_bit_counter <= sample_bit_counter + 1; + END IF; + + IF (sample_bit_counter MOD 2) = 1 THEN + FOR l IN 0 TO ChanelCount-1 LOOP + --shift_reg(l)(15) <= sdo(l); + --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + shift_reg(l)(0) <= sdo(l); + shift_reg(l)(14 DOWNTO 1) <= shift_reg(l)(13 DOWNTO 0); + END LOOP; + SCK <= '0'; + ELSE + SCK <= '1'; + END IF; + + IF sample_bit_counter = 31 THEN + sample_val <= '1'; + FOR l IN 0 TO ChanelCount-1 LOOP + --sample(l)(15) <= sdo(l); + --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1); + sample(l)(0) <= sdo(l); + sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0); + END LOOP; + ELSE + sample_val <= '0'; + END IF; + END IF; + END PROCESS; + +END ar_AD7688_drvr; diff --git a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_apbreg.vhd @@ -405,4 +405,4 @@ BEGIN -- beh apbo.prdata <= prdata; -END beh; +END beh; \ No newline at end of file diff --git a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd --- a/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd +++ b/lib/lpp/lpp_top_lfr/lpp_top_lfr_wf_picker.vhd @@ -1,243 +1,251 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; - -LIBRARY lpp; -USE lpp.lpp_ad_conv.ALL; -USE lpp.iir_filter.ALL; -USE lpp.FILTERcfg.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_waveform_pkg.ALL; -USE lpp.lpp_top_lfr_pkg.ALL; - -LIBRARY techmap; -USE techmap.gencomp.ALL; - -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; - -ENTITY lpp_top_lfr_wf_picker IS - GENERIC ( - hindex : INTEGER := 2; - pindex : INTEGER := 4; - paddr : INTEGER := 4; - pmask : INTEGER := 16#fff#; - pirq : INTEGER := 0; - tech : INTEGER := 0; - nb_burst_available_size : INTEGER := 11; - nb_snapshot_param_size : INTEGER := 11; - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10 - ); - PORT ( - -- ADS7886 - cnv_run : IN STD_LOGIC; - cnv : OUT STD_LOGIC; - sck : OUT STD_LOGIC; - sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); - -- - cnv_clk : IN STD_LOGIC; - cnv_rstn : IN STD_LOGIC; - - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - - -- AMBA APB Slave Interface - apbi : IN apb_slv_in_type; - apbo : OUT apb_slv_out_type; - - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - - -- - coarse_time_0 : IN STD_LOGIC; - - -- - data_shaping_BW : OUT STD_LOGIC - ); -END lpp_top_lfr_wf_picker; - -ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS - - SIGNAL ready_matrix_f0_0 : STD_LOGIC; - SIGNAL ready_matrix_f0_1 : STD_LOGIC; - SIGNAL ready_matrix_f1 : STD_LOGIC; - SIGNAL ready_matrix_f2 : STD_LOGIC; - SIGNAL error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL error_bad_component_error : STD_LOGIC; - SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; - SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; - SIGNAL status_ready_matrix_f1 : STD_LOGIC; - SIGNAL status_ready_matrix_f2 : STD_LOGIC; - SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; - SIGNAL status_error_bad_component_error : STD_LOGIC; - SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; - SIGNAL config_active_interruption_onError : STD_LOGIC; - SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL data_shaping_SP0 : STD_LOGIC; - SIGNAL data_shaping_SP1 : STD_LOGIC; - SIGNAL data_shaping_R0 : STD_LOGIC; - SIGNAL data_shaping_R1 : STD_LOGIC; - SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); - SIGNAL enable_f0 : STD_LOGIC; - SIGNAL enable_f1 : STD_LOGIC; - SIGNAL enable_f2 : STD_LOGIC; - SIGNAL enable_f3 : STD_LOGIC; - SIGNAL burst_f0 : STD_LOGIC; - SIGNAL burst_f1 : STD_LOGIC; - SIGNAL burst_f2 : STD_LOGIC; - SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); - - SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); - SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); - - -BEGIN - - lpp_top_apbreg_1: lpp_top_apbreg - GENERIC MAP ( - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size, - pindex => pindex, - paddr => paddr, - pmask => pmask, - pirq => pirq) - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - apbi => apbi, - apbo => apbo, - - ready_matrix_f0_0 => ready_matrix_f0_0, - ready_matrix_f0_1 => ready_matrix_f0_1, - ready_matrix_f1 => ready_matrix_f1, - ready_matrix_f2 => ready_matrix_f2, - error_anticipating_empty_fifo => error_anticipating_empty_fifo, - error_bad_component_error => error_bad_component_error, - debug_reg => debug_reg, - status_ready_matrix_f0_0 => status_ready_matrix_f0_0, - status_ready_matrix_f0_1 => status_ready_matrix_f0_1, - status_ready_matrix_f1 => status_ready_matrix_f1, - status_ready_matrix_f2 => status_ready_matrix_f2, - status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, - status_error_bad_component_error => status_error_bad_component_error, - config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, - config_active_interruption_onError => config_active_interruption_onError, - addr_matrix_f0_0 => addr_matrix_f0_0, - addr_matrix_f0_1 => addr_matrix_f0_1, - addr_matrix_f1 => addr_matrix_f1, - addr_matrix_f2 => addr_matrix_f2, - - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - data_shaping_BW => data_shaping_BW, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); - - lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip - GENERIC MAP ( - hindex => hindex, - nb_burst_available_size => nb_burst_available_size, - nb_snapshot_param_size => nb_snapshot_param_size, - delta_snapshot_size => delta_snapshot_size, - delta_f2_f0_size => delta_f2_f0_size, - delta_f2_f1_size => delta_f2_f1_size, - tech => tech) - PORT MAP ( - cnv_run => cnv_run, - cnv => cnv, - sck => sck, - sdo => sdo, - cnv_clk => cnv_clk, - cnv_rstn => cnv_rstn, - - clk => HCLK, - rstn => HRESETn, - - sample_f0_wen => sample_f0_wen, - sample_f0_wdata => sample_f0_wdata, - sample_f1_wen => sample_f1_wen, - sample_f1_wdata => sample_f1_wdata, - sample_f2_wen => sample_f2_wen, - sample_f2_wdata => sample_f2_wdata, - sample_f3_wen => sample_f3_wen, - sample_f3_wdata => sample_f3_wdata, - AHB_Master_In => AHB_Master_In, - AHB_Master_Out => AHB_Master_Out, - coarse_time_0 => coarse_time_0, - data_shaping_SP0 => data_shaping_SP0, - data_shaping_SP1 => data_shaping_SP1, - data_shaping_R0 => data_shaping_R0, - data_shaping_R1 => data_shaping_R1, - delta_snapshot => delta_snapshot, - delta_f2_f1 => delta_f2_f1, - delta_f2_f0 => delta_f2_f0, - enable_f0 => enable_f0, - enable_f1 => enable_f1, - enable_f2 => enable_f2, - enable_f3 => enable_f3, - burst_f0 => burst_f0, - burst_f1 => burst_f1, - burst_f2 => burst_f2, - nb_burst_available => nb_burst_available, - nb_snapshot_param => nb_snapshot_param, - status_full => status_full, - status_full_ack => status_full_ack, - status_full_err => status_full_err, - status_new_err => status_new_err, - addr_data_f0 => addr_data_f0, - addr_data_f1 => addr_data_f1, - addr_data_f2 => addr_data_f2, - addr_data_f3 => addr_data_f3); -END tb; +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +ENTITY lpp_top_lfr_wf_picker IS + GENERIC ( + hindex : INTEGER := 2; + pindex : INTEGER := 15; + paddr : INTEGER := 15; + pmask : INTEGER := 16#fff#; + pirq : INTEGER := 15; + tech : INTEGER := 0; + nb_burst_available_size : INTEGER := 11; + nb_snapshot_param_size : INTEGER := 11; + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10 + ); + PORT ( + -- ADS7886 + cnv_run : IN STD_LOGIC; + cnv : OUT STD_LOGIC; + sck : OUT STD_LOGIC; + sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + -- + cnv_clk : IN STD_LOGIC; + cnv_rstn : IN STD_LOGIC; + + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + + -- AMBA APB Slave Interface + apbi : IN apb_slv_in_type; + apbo : OUT apb_slv_out_type; + + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + + -- + coarse_time_0 : IN STD_LOGIC; + + -- + data_shaping_BW : OUT STD_LOGIC + ); +END lpp_top_lfr_wf_picker; + +ARCHITECTURE tb OF lpp_top_lfr_wf_picker IS + + SIGNAL ready_matrix_f0_0 : STD_LOGIC; + SIGNAL ready_matrix_f0_1 : STD_LOGIC; + SIGNAL ready_matrix_f1 : STD_LOGIC; + SIGNAL ready_matrix_f2 : STD_LOGIC; + SIGNAL error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL error_bad_component_error : STD_LOGIC; + SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL status_ready_matrix_f0_0 : STD_LOGIC; + SIGNAL status_ready_matrix_f0_1 : STD_LOGIC; + SIGNAL status_ready_matrix_f1 : STD_LOGIC; + SIGNAL status_ready_matrix_f2 : STD_LOGIC; + SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC; + SIGNAL status_error_bad_component_error : STD_LOGIC; + SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC; + SIGNAL config_active_interruption_onError : STD_LOGIC; + SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL data_shaping_SP0 : STD_LOGIC; + SIGNAL data_shaping_SP1 : STD_LOGIC; + SIGNAL data_shaping_R0 : STD_LOGIC; + SIGNAL data_shaping_R1 : STD_LOGIC; + SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(5 DOWNTO 0); + SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0); + + +BEGIN + + ready_matrix_f0_0 <= '0'; + ready_matrix_f0_1 <= '0'; + ready_matrix_f1 <= '0'; + ready_matrix_f2 <= '0'; + error_anticipating_empty_fifo <= '0'; + error_bad_component_error <= '0'; + debug_reg <= (others => '0'); + + lpp_top_apbreg_1: lpp_top_apbreg + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + pindex => pindex, + paddr => paddr, + pmask => pmask, + pirq => pirq) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + apbi => apbi, + apbo => apbo, + + ready_matrix_f0_0 => ready_matrix_f0_0, + ready_matrix_f0_1 => ready_matrix_f0_1, + ready_matrix_f1 => ready_matrix_f1, + ready_matrix_f2 => ready_matrix_f2, + error_anticipating_empty_fifo => error_anticipating_empty_fifo, + error_bad_component_error => error_bad_component_error, + debug_reg => debug_reg, + status_ready_matrix_f0_0 => status_ready_matrix_f0_0, + status_ready_matrix_f0_1 => status_ready_matrix_f0_1, + status_ready_matrix_f1 => status_ready_matrix_f1, + status_ready_matrix_f2 => status_ready_matrix_f2, + status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo, + status_error_bad_component_error => status_error_bad_component_error, + config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, + config_active_interruption_onError => config_active_interruption_onError, + addr_matrix_f0_0 => addr_matrix_f0_0, + addr_matrix_f0_1 => addr_matrix_f0_1, + addr_matrix_f1 => addr_matrix_f1, + addr_matrix_f2 => addr_matrix_f2, + + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + data_shaping_BW => data_shaping_BW, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); + + lpp_top_lfr_wf_picker_ip_1: lpp_top_lfr_wf_picker_ip + GENERIC MAP ( + hindex => hindex, + nb_burst_available_size => nb_burst_available_size, + nb_snapshot_param_size => nb_snapshot_param_size, + delta_snapshot_size => delta_snapshot_size, + delta_f2_f0_size => delta_f2_f0_size, + delta_f2_f1_size => delta_f2_f1_size, + tech => tech) + PORT MAP ( + cnv_run => cnv_run, + cnv => cnv, + sck => sck, + sdo => sdo, + cnv_clk => cnv_clk, + cnv_rstn => cnv_rstn, + + clk => HCLK, + rstn => HRESETn, + + sample_f0_wen => sample_f0_wen, + sample_f0_wdata => sample_f0_wdata, + sample_f1_wen => sample_f1_wen, + sample_f1_wdata => sample_f1_wdata, + sample_f2_wen => sample_f2_wen, + sample_f2_wdata => sample_f2_wdata, + sample_f3_wen => sample_f3_wen, + sample_f3_wdata => sample_f3_wdata, + AHB_Master_In => AHB_Master_In, + AHB_Master_Out => AHB_Master_Out, + coarse_time_0 => coarse_time_0, + data_shaping_SP0 => data_shaping_SP0, + data_shaping_SP1 => data_shaping_SP1, + data_shaping_R0 => data_shaping_R0, + data_shaping_R1 => data_shaping_R1, + delta_snapshot => delta_snapshot, + delta_f2_f1 => delta_f2_f1, + delta_f2_f0 => delta_f2_f0, + enable_f0 => enable_f0, + enable_f1 => enable_f1, + enable_f2 => enable_f2, + enable_f3 => enable_f3, + burst_f0 => burst_f0, + burst_f1 => burst_f1, + burst_f2 => burst_f2, + nb_burst_available => nb_burst_available, + nb_snapshot_param => nb_snapshot_param, + status_full => status_full, + status_full_ack => status_full_ack, + status_full_err => status_full_err, + status_new_err => status_new_err, + addr_data_f0 => addr_data_f0, + addr_data_f1 => addr_data_f1, + addr_data_f2 => addr_data_f2, + addr_data_f3 => addr_data_f3); +END tb; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_dma.vhd @@ -1,363 +1,363 @@ - ------------------------------------------------------------------------------- --- This file is a part of the LPP VHDL IP LIBRARY --- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS --- --- This program is free software; you can redistribute it and/or modify --- it under the terms of the GNU General Public License as published by --- the Free Software Foundation; either version 3 of the License, or --- (at your option) any later version. --- --- This program is distributed in the hope that it will be useful, --- but WITHOUT ANY WARRANTY; without even the implied warranty of --- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --- GNU General Public License for more details. --- --- You should have received a copy of the GNU General Public License --- along with this program; if not, write to the Free Software --- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -------------------------------------------------------------------------------- --- Author : Jean-christophe Pellion --- Mail : jean-christophe.pellion@lpp.polytechnique.fr --- jean-christophe.pellion@easii-ic.com -------------------------------------------------------------------------------- --- 1.0 - initial version --- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) -------------------------------------------------------------------------------- -LIBRARY ieee; -USE ieee.std_logic_1164.ALL; -USE ieee.numeric_std.ALL; -LIBRARY grlib; -USE grlib.amba.ALL; -USE grlib.stdlib.ALL; -USE grlib.devices.ALL; -USE GRLIB.DMA2AHB_Package.ALL; -LIBRARY lpp; -USE lpp.lpp_amba.ALL; -USE lpp.apb_devices_list.ALL; -USE lpp.lpp_memory.ALL; -USE lpp.lpp_dma_pkg.ALL; -USE lpp.lpp_waveform_pkg.ALL; -LIBRARY techmap; -USE techmap.gencomp.ALL; - - -ENTITY lpp_waveform_dma IS - GENERIC ( - data_size : INTEGER := 160; - tech : INTEGER := inferred; - hindex : INTEGER := 2; - nb_burst_available_size : INTEGER := 11 - ); - PORT ( - -- AMBA AHB system signals - HCLK : IN STD_ULOGIC; - HRESETn : IN STD_ULOGIC; - -- AMBA AHB Master Interface - AHB_Master_In : IN AHB_Mst_In_Type; - AHB_Master_Out : OUT AHB_Mst_Out_Type; - -- - data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo - data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo - -- Reg - nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); - status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); - status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma - addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); - addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) - ); -END; - -ARCHITECTURE Behavioral OF lpp_waveform_dma IS - ----------------------------------------------------------------------------- - SIGNAL DMAIn : DMA_In_Type; - SIGNAL DMAOut : DMA_OUt_Type; - ----------------------------------------------------------------------------- - TYPE state_DMAWriteBurst IS (IDLE, - SEND_TIME_0, WAIT_TIME_0, - SEND_TIME_1, WAIT_TIME_1, - SEND_5_TIME, - SEND_DATA, WAIT_DATA); - SIGNAL state : state_DMAWriteBurst := IDLE; - ----------------------------------------------------------------------------- - -- CONTROL - SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); - SIGNAL time_select : STD_LOGIC; - SIGNAL time_write : STD_LOGIC; - SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); - SIGNAL time_already_send_s : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SEND TIME MODULE - SIGNAL time_dmai : DMA_In_Type; - SIGNAL time_send : STD_LOGIC; - SIGNAL time_send_ok : STD_LOGIC; - SIGNAL time_send_ko : STD_LOGIC; - SIGNAL time_fifo_ren : STD_LOGIC; - SIGNAL time_ren : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SEND DATA MODULE - SIGNAL data_dmai : DMA_In_Type; - SIGNAL data_send : STD_LOGIC; - SIGNAL data_send_ok : STD_LOGIC; - SIGNAL data_send_ko : STD_LOGIC; - SIGNAL data_fifo_ren : STD_LOGIC; - SIGNAL data_ren : STD_LOGIC; - ----------------------------------------------------------------------------- - -- SELECT ADDRESS - SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); - SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); - SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); - ----------------------------------------------------------------------------- - SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); - SIGNAL count_send_time : INTEGER; -BEGIN - - ----------------------------------------------------------------------------- - -- DMA to AHB interface - DMA2AHB_1 : DMA2AHB - GENERIC MAP ( - hindex => hindex, - vendorid => VENDOR_LPP, - deviceid => 0, - version => 0, - syncrst => 1, - boundary => 1) -- FIX 11/01/2013 - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => DMAIn, - DMAOut => DMAOut, - AHBIn => AHB_Master_In, - AHBOut => AHB_Master_Out); - ----------------------------------------------------------------------------- - - ----------------------------------------------------------------------------- - -- This module memorises when the Times info are write. When FSM send - -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. - all_time_write: FOR I IN 3 DOWNTO 0 GENERATE - PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS - IF HRESETn = '0' THEN -- asynchronous reset (active low) - time_already_send(I) <= '0'; - ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge - IF time_write = '1' AND UNSIGNED(sel_data) = I THEN - time_already_send(I) <= '1'; - ELSIF status_full_ack(I) = '1' THEN - time_already_send(I) <= '0'; - END IF; - END IF; - END PROCESS; - END GENERATE all_time_write; - - ----------------------------------------------------------------------------- - sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE - "01" WHEN data_ready(1) = '1' ELSE - "10" WHEN data_ready(2) = '1' ELSE - "11"; - - time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE - time_already_send(1) WHEN data_ready(1) = '1' ELSE - time_already_send(2) WHEN data_ready(2) = '1' ELSE - time_already_send(3); - - -- DMA control - DMAWriteFSM_p : PROCESS (HCLK, HRESETn) - BEGIN -- PROCESS DMAWriteBurst_p - IF HRESETn = '0' THEN - state <= IDLE; - - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - send_16_3_time <= "001"; - - ELSIF HCLK'EVENT AND HCLK = '1' THEN - - CASE state IS - WHEN IDLE => - count_send_time <= 0; - sel_data <= "00"; - update <= "00"; - time_select <= '0'; - time_fifo_ren <= '1'; - data_send <= '0'; - time_send <= '0'; - time_write <= '0'; - - IF data_ready = "0000" THEN - state <= IDLE; - ELSE - sel_data <= sel_data_s; - send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); - IF send_16_3_time(0) = '1' THEN - state <= SEND_TIME_0; - ELSE - state <= SEND_5_TIME; - END IF; - END IF; - - WHEN SEND_TIME_0 => - time_select <= '1'; - IF time_already_send_s = '0' THEN - time_send <= '1'; - state <= WAIT_TIME_0; - ELSE - time_send <= '0'; - state <= SEND_TIME_1; - END IF; - time_fifo_ren <= '0'; - - WHEN WAIT_TIME_0 => - time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; - IF time_send_ok = '1' OR time_send_ko = '1' THEN - update <= "01"; - state <= SEND_TIME_1; - END IF; - - WHEN SEND_TIME_1 => - time_select <= '1'; - IF time_already_send_s = '0' THEN - time_send <= '1'; - state <= WAIT_TIME_1; - ELSE - time_send <= '0'; - state <= SEND_5_TIME; - END IF; - time_fifo_ren <= '0'; - - WHEN WAIT_TIME_1 => - time_fifo_ren <= '1'; - update <= "00"; - time_send <= '0'; - IF time_send_ok = '1' OR time_send_ko = '1' THEN - time_write <= '1'; - update <= "01"; - state <= SEND_5_TIME; - END IF; - - WHEN SEND_5_TIME => - update <= "00"; - time_select <= '1'; - time_fifo_ren <= '0'; - count_send_time <= count_send_time + 1; - IF count_send_time = 10 THEN - state <= SEND_DATA; - END IF; - - WHEN SEND_DATA => - time_fifo_ren <= '1'; - time_write <= '0'; - time_send <= '0'; - - time_select <= '0'; - data_send <= '1'; - update <= "00"; - state <= WAIT_DATA; - - WHEN WAIT_DATA => - data_send <= '0'; - - IF data_send_ok = '1' OR data_send_ko = '1' THEN - state <= IDLE; - update <= "10"; - END IF; - - WHEN OTHERS => NULL; - END CASE; - - END IF; - END PROCESS DMAWriteFSM_p; - ----------------------------------------------------------------------------- - - - - ----------------------------------------------------------------------------- - -- SEND 1 word by DMA - ----------------------------------------------------------------------------- - lpp_dma_send_1word_1 : lpp_dma_send_1word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => time_dmai, - DMAOut => DMAOut, - - send => time_send, - address => data_address, - data => data, - send_ok => time_send_ok, - send_ko => time_send_ko - ); - - ----------------------------------------------------------------------------- - -- SEND 16 word by DMA (in burst mode) - ----------------------------------------------------------------------------- - lpp_dma_send_16word_1 : lpp_dma_send_16word - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - DMAIn => data_dmai, - DMAOut => DMAOut, - - send => data_send, - address => data_address, - data => data, - ren => data_fifo_ren, - send_ok => data_send_ok, - send_ko => data_send_ko); - - DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; - data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; - time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; - - all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE - data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; - data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; - END GENERATE all_data_ren; - - ----------------------------------------------------------------------------- - -- SELECT ADDRESS - addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; - - gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE - - update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; - - lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress - GENERIC MAP ( - nb_burst_available_size => nb_burst_available_size) - PORT MAP ( - HCLK => HCLK, - HRESETn => HRESETn, - update => update_and_sel((2*I)+1 DOWNTO 2*I), - nb_burst_available => nb_burst_available, - addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), - addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), - status_full => status_full(I), - status_full_ack => status_full_ack(I), - status_full_err => status_full_err(I)); - - END GENERATE gen_select_address; - - data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE - addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE - addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE - addr_data_vector(32*3+31 DOWNTO 32*3); - ----------------------------------------------------------------------------- - - -END Behavioral; + +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +-- jean-christophe.pellion@easii-ic.com +------------------------------------------------------------------------------- +-- 1.0 - initial version +-- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS) +------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; +LIBRARY lpp; +USE lpp.lpp_amba.ALL; +USE lpp.apb_devices_list.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_waveform_pkg.ALL; +LIBRARY techmap; +USE techmap.gencomp.ALL; + + +ENTITY lpp_waveform_dma IS + GENERIC ( + data_size : INTEGER := 160; + tech : INTEGER := inferred; + hindex : INTEGER := 2; + nb_burst_available_size : INTEGER := 11 + ); + PORT ( + -- AMBA AHB system signals + HCLK : IN STD_ULOGIC; + HRESETn : IN STD_ULOGIC; + -- AMBA AHB Master Interface + AHB_Master_In : IN AHB_Mst_In_Type; + AHB_Master_Out : OUT AHB_Mst_Out_Type; + -- + data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo + data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo + -- Reg + nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); +-- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma + addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); +END; + +ARCHITECTURE Behavioral OF lpp_waveform_dma IS + ----------------------------------------------------------------------------- + SIGNAL DMAIn : DMA_In_Type; + SIGNAL DMAOut : DMA_OUt_Type; + ----------------------------------------------------------------------------- + TYPE state_DMAWriteBurst IS (IDLE, + SEND_TIME_0, WAIT_TIME_0, + SEND_TIME_1, WAIT_TIME_1, + SEND_5_TIME, + SEND_DATA, WAIT_DATA); + SIGNAL state : state_DMAWriteBurst; + ----------------------------------------------------------------------------- + -- CONTROL + SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0); + SIGNAL time_select : STD_LOGIC; + SIGNAL time_write : STD_LOGIC; + SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL time_already_send_s : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND TIME MODULE + SIGNAL time_dmai : DMA_In_Type; + SIGNAL time_send : STD_LOGIC; + SIGNAL time_send_ok : STD_LOGIC; + SIGNAL time_send_ko : STD_LOGIC; + SIGNAL time_fifo_ren : STD_LOGIC; + SIGNAL time_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SEND DATA MODULE + SIGNAL data_dmai : DMA_In_Type; + SIGNAL data_send : STD_LOGIC; + SIGNAL data_send_ok : STD_LOGIC; + SIGNAL data_send_ko : STD_LOGIC; + SIGNAL data_fifo_ren : STD_LOGIC; + SIGNAL data_ren : STD_LOGIC; + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + SIGNAL data_address : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL update_and_sel : STD_LOGIC_VECTOR(7 DOWNTO 0); + SIGNAL addr_data_reg_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + SIGNAL addr_data_vector : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); + ----------------------------------------------------------------------------- + SIGNAL send_16_3_time : STD_LOGIC_VECTOR(2 DOWNTO 0); + SIGNAL count_send_time : INTEGER; +BEGIN + + ----------------------------------------------------------------------------- + -- DMA to AHB interface + DMA2AHB_1 : DMA2AHB + GENERIC MAP ( + hindex => hindex, + vendorid => VENDOR_LPP, + deviceid => 10, + version => 0, + syncrst => 1, + boundary => 1) -- FIX 11/01/2013 + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => DMAIn, + DMAOut => DMAOut, + AHBIn => AHB_Master_In, + AHBOut => AHB_Master_Out); + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- This module memorises when the Times info are write. When FSM send + -- the Times info, the "reg" is set and when a full_ack is received the "reg" is reset. + all_time_write: FOR I IN 3 DOWNTO 0 GENERATE + PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS + IF HRESETn = '0' THEN -- asynchronous reset (active low) + time_already_send(I) <= '0'; + ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge + IF time_write = '1' AND UNSIGNED(sel_data) = I THEN + time_already_send(I) <= '1'; + ELSIF status_full_ack(I) = '1' THEN + time_already_send(I) <= '0'; + END IF; + END IF; + END PROCESS; + END GENERATE all_time_write; + + ----------------------------------------------------------------------------- + sel_data_s <= "00" WHEN data_ready(0) = '1' ELSE + "01" WHEN data_ready(1) = '1' ELSE + "10" WHEN data_ready(2) = '1' ELSE + "11"; + + time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE + time_already_send(1) WHEN data_ready(1) = '1' ELSE + time_already_send(2) WHEN data_ready(2) = '1' ELSE + time_already_send(3); + + -- DMA control + DMAWriteFSM_p : PROCESS (HCLK, HRESETn) + BEGIN -- PROCESS DMAWriteBurst_p + IF HRESETn = '0' THEN + state <= IDLE; + + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + send_16_3_time <= "001"; + + ELSIF HCLK'EVENT AND HCLK = '1' THEN + + CASE state IS + WHEN IDLE => + count_send_time <= 0; + sel_data <= "00"; + update <= "00"; + time_select <= '0'; + time_fifo_ren <= '1'; + data_send <= '0'; + time_send <= '0'; + time_write <= '0'; + + IF data_ready = "0000" THEN + state <= IDLE; + ELSE + sel_data <= sel_data_s; + send_16_3_time <= send_16_3_time(1 DOWNTO 0) & send_16_3_time(2); + IF send_16_3_time(0) = '1' THEN + state <= SEND_TIME_0; + ELSE + state <= SEND_5_TIME; + END IF; + END IF; + + WHEN SEND_TIME_0 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_0; + ELSE + time_send <= '0'; + state <= SEND_TIME_1; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_0 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + update <= "01"; + state <= SEND_TIME_1; + END IF; + + WHEN SEND_TIME_1 => + time_select <= '1'; + IF time_already_send_s = '0' THEN + time_send <= '1'; + state <= WAIT_TIME_1; + ELSE + time_send <= '0'; + state <= SEND_5_TIME; + END IF; + time_fifo_ren <= '0'; + + WHEN WAIT_TIME_1 => + time_fifo_ren <= '1'; + update <= "00"; + time_send <= '0'; + IF time_send_ok = '1' OR time_send_ko = '1' THEN + time_write <= '1'; + update <= "01"; + state <= SEND_5_TIME; + END IF; + + WHEN SEND_5_TIME => + update <= "00"; + time_select <= '1'; + time_fifo_ren <= '0'; + count_send_time <= count_send_time + 1; + IF count_send_time = 10 THEN + state <= SEND_DATA; + END IF; + + WHEN SEND_DATA => + time_fifo_ren <= '1'; + time_write <= '0'; + time_send <= '0'; + + time_select <= '0'; + data_send <= '1'; + update <= "00"; + state <= WAIT_DATA; + + WHEN WAIT_DATA => + data_send <= '0'; + + IF data_send_ok = '1' OR data_send_ko = '1' THEN + state <= IDLE; + update <= "10"; + END IF; + + WHEN OTHERS => NULL; + END CASE; + + END IF; + END PROCESS DMAWriteFSM_p; + ----------------------------------------------------------------------------- + + + + ----------------------------------------------------------------------------- + -- SEND 1 word by DMA + ----------------------------------------------------------------------------- + lpp_dma_send_1word_1 : lpp_dma_send_1word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => time_dmai, + DMAOut => DMAOut, + + send => time_send, + address => data_address, + data => data, + send_ok => time_send_ok, + send_ko => time_send_ko + ); + + ----------------------------------------------------------------------------- + -- SEND 16 word by DMA (in burst mode) + ----------------------------------------------------------------------------- + lpp_dma_send_16word_1 : lpp_dma_send_16word + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + DMAIn => data_dmai, + DMAOut => DMAOut, + + send => data_send, + address => data_address, + data => data, + ren => data_fifo_ren, + send_ok => data_send_ok, + send_ko => data_send_ko); + + DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai; + data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren; + time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1'; + + all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE + data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + data_time_ren(I) <= time_ren WHEN UNSIGNED(sel_data) = I ELSE '1'; + END GENERATE all_data_ren; + + ----------------------------------------------------------------------------- + -- SELECT ADDRESS + addr_data_reg_vector <= addr_data_f3 & addr_data_f2 & addr_data_f1 & addr_data_f0; + + gen_select_address : FOR I IN 3 DOWNTO 0 GENERATE + + update_and_sel((2*I)+1 DOWNTO 2*I) <= update WHEN UNSIGNED(sel_data) = I ELSE "00"; + + lpp_waveform_dma_selectaddress_I : lpp_waveform_dma_selectaddress + GENERIC MAP ( + nb_burst_available_size => nb_burst_available_size) + PORT MAP ( + HCLK => HCLK, + HRESETn => HRESETn, + update => update_and_sel((2*I)+1 DOWNTO 2*I), + nb_burst_available => nb_burst_available, + addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I), + addr_data => addr_data_vector(32*I+31 DOWNTO 32*I), + status_full => status_full(I), + status_full_ack => status_full_ack(I), + status_full_err => status_full_err(I)); + + END GENERATE gen_select_address; + + data_address <= addr_data_vector(31 DOWNTO 0) WHEN UNSIGNED(sel_data) = 0 ELSE + addr_data_vector(32*1+31 DOWNTO 32*1) WHEN UNSIGNED(sel_data) = 1 ELSE + addr_data_vector(32*2+31 DOWNTO 32*2) WHEN UNSIGNED(sel_data) = 2 ELSE + addr_data_vector(32*3+31 DOWNTO 32*3); + ----------------------------------------------------------------------------- + + +END Behavioral; \ No newline at end of file diff --git a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd --- a/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd +++ b/lib/lpp/lpp_waveform/lpp_waveform_snapshot_controler.vhd @@ -1,116 +1,114 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE ieee.numeric_std.ALL; - -ENTITY lpp_waveform_snapshot_controler IS - - GENERIC ( - delta_snapshot_size : INTEGER := 16; - delta_f2_f0_size : INTEGER := 10; - delta_f2_f1_size : INTEGER := 10); - - PORT ( - clk : IN STD_LOGIC; - rstn : IN STD_LOGIC; - --config - delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); - delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); - delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); - - --input - coarse_time_0 : IN STD_LOGIC; - data_f0_in_valid : IN STD_LOGIC; - data_f2_in_valid : IN STD_LOGIC; - --output - start_snapshot_f0 : OUT STD_LOGIC; - start_snapshot_f1 : OUT STD_LOGIC; - start_snapshot_f2 : OUT STD_LOGIC - ); - -END lpp_waveform_snapshot_controler; - -ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS - SIGNAL counter_delta_snapshot : INTEGER; - SIGNAL counter_delta_f0 : INTEGER; - - SIGNAL coarse_time_0_r : STD_LOGIC; - SIGNAL start_snapshot_f2_temp : STD_LOGIC; - SIGNAL start_snapshot_fothers_temp : STD_LOGIC; - SIGNAL start_snapshot_fothers_temp2 : STD_LOGIC; -BEGIN -- beh - - PROCESS (clk, rstn) - BEGIN - IF rstn = '0' THEN - start_snapshot_f0 <= '0'; - start_snapshot_f1 <= '0'; - start_snapshot_f2 <= '0'; - counter_delta_snapshot <= 0; - counter_delta_f0 <= 0; - coarse_time_0_r <= '0'; - start_snapshot_f2_temp <= '0'; - start_snapshot_fothers_temp <= '0'; - start_snapshot_fothers_temp2 <= '0'; - ELSIF clk'EVENT AND clk = '1' THEN - IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN - start_snapshot_f2_temp <= '1'; - ELSE - start_snapshot_f2_temp <= '0'; - END IF; - ------------------------------------------------------------------------- - IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN - start_snapshot_f2 <= '1'; - ELSE - start_snapshot_f2 <= '0'; - END IF; - ------------------------------------------------------------------------- - coarse_time_0_r <= coarse_time_0; - IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN - IF counter_delta_snapshot = 0 THEN - counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); - ELSE - counter_delta_snapshot <= counter_delta_snapshot - 1; - END IF; - END IF; - - - ------------------------------------------------------------------------- - - - - IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN - start_snapshot_f1 <= '1'; - ELSE - start_snapshot_f1 <= '0'; - END IF; - - IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN - start_snapshot_f0 <= '1'; - ELSE - start_snapshot_f0 <= '0'; - END IF; - - IF counter_delta_snapshot = UNSIGNED(delta_snapshot) - AND start_snapshot_f2_temp = '0' - THEN -- - start_snapshot_fothers_temp <= '1'; - ELSIF counter_delta_f0 > 0 THEN - start_snapshot_fothers_temp <= '0'; - END IF; - - - ------------------------------------------------------------------------- - IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN - --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- - --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN - counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; - ELSE - IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN - counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; - END IF; - END IF; - ------------------------------------------------------------------------- - END IF; - END PROCESS; - -END beh; +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE ieee.numeric_std.ALL; + +ENTITY lpp_waveform_snapshot_controler IS + + GENERIC ( + delta_snapshot_size : INTEGER := 16; + delta_f2_f0_size : INTEGER := 10; + delta_f2_f1_size : INTEGER := 10); + + PORT ( + clk : IN STD_LOGIC; + rstn : IN STD_LOGIC; + --config + delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0); + delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0); + delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0); + + --input + coarse_time_0 : IN STD_LOGIC; + data_f0_in_valid : IN STD_LOGIC; + data_f2_in_valid : IN STD_LOGIC; + --output + start_snapshot_f0 : OUT STD_LOGIC; + start_snapshot_f1 : OUT STD_LOGIC; + start_snapshot_f2 : OUT STD_LOGIC + ); + +END lpp_waveform_snapshot_controler; + +ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS + SIGNAL counter_delta_snapshot : INTEGER; + SIGNAL counter_delta_f0 : INTEGER; + + SIGNAL coarse_time_0_r : STD_LOGIC; + SIGNAL start_snapshot_f2_temp : STD_LOGIC; + SIGNAL start_snapshot_fothers_temp : STD_LOGIC; +BEGIN -- beh + + PROCESS (clk, rstn) + BEGIN + IF rstn = '0' THEN + start_snapshot_f0 <= '0'; + start_snapshot_f1 <= '0'; + start_snapshot_f2 <= '0'; + counter_delta_snapshot <= 0; + counter_delta_f0 <= 0; + coarse_time_0_r <= '0'; + start_snapshot_f2_temp <= '0'; + start_snapshot_fothers_temp <= '0'; + ELSIF clk'EVENT AND clk = '1' THEN + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + start_snapshot_f2_temp <= '1'; + ELSE + start_snapshot_f2_temp <= '0'; + END IF; + ------------------------------------------------------------------------- + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN + start_snapshot_f2 <= '1'; + ELSE + start_snapshot_f2 <= '0'; + END IF; + ------------------------------------------------------------------------- + coarse_time_0_r <= coarse_time_0; + IF coarse_time_0 = NOT coarse_time_0_r AND coarse_time_0 = '1' THEN + IF counter_delta_snapshot = 0 THEN + counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot)); + ELSE + counter_delta_snapshot <= counter_delta_snapshot - 1; + END IF; + END IF; + + + ------------------------------------------------------------------------- + + + + IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN + start_snapshot_f1 <= '1'; + ELSE + start_snapshot_f1 <= '0'; + END IF; + + IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN + start_snapshot_f0 <= '1'; + ELSE + start_snapshot_f0 <= '0'; + END IF; + + IF counter_delta_snapshot = UNSIGNED(delta_snapshot) + AND start_snapshot_f2_temp = '0' + THEN -- + start_snapshot_fothers_temp <= '1'; + ELSIF counter_delta_f0 > 0 THEN + start_snapshot_fothers_temp <= '0'; + END IF; + + + ------------------------------------------------------------------------- + IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN + --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN -- + --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN + counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0; + ELSE + IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN + counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1; + END IF; + END IF; + ------------------------------------------------------------------------- + END IF; + END PROCESS; + +END beh; \ No newline at end of file