##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

fusionner
Alexis -
r50:ce61e79b0d95 merge default
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,129
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fifo.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL de la FIFO et le bus Amba
34
35 entity APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
47 );
48 end APB_FIFO;
49
50
51 architecture ar_APB_FIFO of APB_FIFO is
52
53 constant REVISION : integer := 1;
54
55 constant pconfig : apb_config_type := (
56 0 => ahb_device_reg (VENDOR_LPP, LPP_FIFO, 0, REVISION, 0),
57 1 => apb_iobar(paddr, pmask));
58
59 type FIFO_ctrlr_Reg is record
60 FIFO_Cfg : std_logic_vector(3 downto 0);
61 FIFO_DataW : std_logic_vector(15 downto 0);
62 FIFO_DataR : std_logic_vector(15 downto 0);
63 end record;
64
65 signal Rec : FIFO_ctrlr_Reg;
66 signal Rdata : std_logic_vector(31 downto 0);
67
68 signal flag_RE : std_logic;
69 signal flag_WR : std_logic;
70 signal full : std_logic;
71 signal empty : std_logic;
72 begin
73
74 flag_RE <= Rec.FIFO_Cfg(0);
75 flag_WR <= Rec.FIFO_Cfg(1);
76 Rec.FIFO_Cfg(2) <= empty;
77 Rec.FIFO_Cfg(3) <= full;
78
79 CONVERTER : entity Work.Top_FIFO
80 port map(clk,rst,flag_RE,flag_WR,Rec.FIFO_DataW,full,empty,Rec.FIFO_DataR);
81
82
83 process(rst,clk)
84 begin
85 if(rst='0')then
86 Rec.FIFO_DataW <= (others => '0');
87
88 elsif(clk'event and clk='1')then
89
90
91 --APB Write OP
92 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
93 case apbi.paddr(abits-1 downto 2) is
94 when "000000" =>
95 Rec.FIFO_Cfg(0) <= apbi.pwdata(0);
96 Rec.FIFO_Cfg(1) <= apbi.pwdata(4);
97 when "000001" =>
98 Rec.FIFO_DataW <= apbi.pwdata(15 downto 0);
99 when others =>
100 null;
101 end case;
102 end if;
103
104 --APB READ OP
105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 case apbi.paddr(abits-1 downto 2) is
107 when "000000" =>
108 Rdata(3 downto 0) <= "000" & Rec.FIFO_Cfg(0);
109 Rdata(7 downto 4) <= "000" & Rec.FIFO_Cfg(1);
110 Rdata(11 downto 8) <= "000" & Rec.FIFO_Cfg(2);
111 Rdata(15 downto 12) <= "000" & Rec.FIFO_Cfg(3);
112 Rdata(31 downto 16) <= X"AAAA";
113 when "000001" =>
114 Rdata(31 downto 16) <= X"AAAA";
115 Rdata(15 downto 0) <= Rec.FIFO_DataW;
116 when "000010" =>
117 Rdata(31 downto 16) <= X"AAAA";
118 Rdata(15 downto 0) <= Rec.FIFO_DataR;
119 when others =>
120 Rdata <= (others => '0');
121 end case;
122 end if;
123
124 end if;
125 apbo.pconfig <= pconfig;
126 end process;
127
128 apbo.prdata <= Rdata when apbi.penable = '1';
129 end ar_APB_FIFO;
Show file before | Show file after | Hide comments
@@ -0,0 +1,36
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 Package FIFO_Config is
27
28 --===========================================================|
29 --================= Generic de Config =======================|
30 --===========================================================|
31 constant Data_sz : integer := 16;
32 constant addr_sz : integer := 8;
33 constant addr_max_int : integer := 256;
34
35
36 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO de lecture
28
29 entity Fifo_Read is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
33 WAD : in integer range 0 to addr_max_int; --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme entiοΏ½re)
34 empty : out std_logic; --! Flag, MοΏ½moire vide
35 RAD : out integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mοΏ½moire (forme entiοΏ½re)
36 Raddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre de lecture de la mοΏ½moire (forme vectorielle)
37 );
38 end Fifo_Read;
39
40 --! @details En aval de la SRAM Gaisler
41
42 architecture ar_Fifo_Read of Fifo_Read is
43
44 signal Rad_int : integer range 0 to addr_max_int;
45
46 begin
47 process (clk,raz)
48 begin
49 if(raz='0')then
50 Rad_int <= 0;
51 empty <= '1';
52
53 elsif(clk' event and clk='1')then
54 if(flag_RE='1')then
55 if(Rad_int=addr_max_int)then
56 Rad_int <= 0;
57 else
58 Rad_int <= Rad_int+1;
59 end if;
60 end if;
61 if(Rad_int=WAD)then
62 empty <= '1';
63 else
64 empty <= '0';
65 end if;
66 end if;
67 end process;
68
69 RAD <= Rad_int;
70 Raddr <= std_logic_vector(to_unsigned(Rad_int,addr_sz));
71 end ar_Fifo_Read; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,75
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.FIFO_Config.all;
26
27 --! Programme de la FIFO d'οΏ½criture
28
29 entity Fifo_Write is
30 port(
31 clk,raz : in std_logic; --! Horloge et reset general du composant
32 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
33 RAD : in integer range 0 to addr_max_int; --! Adresse du registre de lecture de la mοΏ½moire (forme entiοΏ½re)
34 full : out std_logic; --! Flag, MοΏ½moire pleine
35 WAD : out integer range 0 to addr_max_int; --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme entiοΏ½re)
36 Waddr : out std_logic_vector(addr_sz-1 downto 0) --! Adresse du registre d'οΏ½criture dans la mοΏ½moire (forme vectorielle)
37 );
38 end Fifo_Write;
39
40 --! @details En amont de la SRAM Gaisler
41
42 architecture ar_Fifo_Write of Fifo_Write is
43
44 signal Wad_int : integer range 0 to addr_max_int;
45 signal full_int : std_logic;
46
47 begin
48 process (clk,raz)
49 begin
50 if(raz='0')then
51 Wad_int <= 0;
52 full_int <= '0';
53
54 elsif(clk' event and clk='1')then
55 if(flag_WR='1')then
56 if(Wad_int=addr_max_int)then
57 Wad_int <= 0;
58 elsif(full_int='1')then
59 Wad_int <= Wad_int;
60 else
61 Wad_int <= Wad_int+1;
62 end if;
63 end if;
64 if(Wad_int=RAD-1 or (Wad_int=addr_max_int and RAD=0))then
65 full_int <= '1';
66 else
67 full_int <= '0';
68 end if;
69 end if;
70 end process;
71
72 full <= full_int;
73 WAD <= Wad_int;
74 Waddr <= std_logic_vector(to_unsigned(Wad_int,addr_sz));
75 end ar_Fifo_Write; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,83
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library techmap;
26 use techmap.gencomp.all;
27 use work.FIFO_Config.all;
28 use work.config.all;
29
30 --! Programme de la FIFO
31
32 entity Top_FIFO is
33 port(
34 clk,raz : in std_logic; --! Horloge et reset general du composant
35 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
36 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
37 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
38 full : out std_logic; --! Flag, MοΏ½moire pleine
39 empty : out std_logic; --! Flag, MοΏ½moire vide
40 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
41 );
42 end Top_FIFO;
43
44 --! @details Une mοΏ½moire SRAM de chez Gaisler est utilisοΏ½e,
45 --! associοΏ½e a deux fifos, une pour οΏ½crire l'autre pour lire cette mοΏ½moire
46
47 architecture ar_Top_FIFO of Top_FIFO is
48
49 component syncram_2p
50 generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8; sepclk : integer
51 := 0);
52 port (
53 rclk : in std_ulogic;
54 renable : in std_ulogic;
55 raddress : in std_logic_vector((abits -1) downto 0);
56 dataout : out std_logic_vector((dbits -1) downto 0);
57 wclk : in std_ulogic;
58 write : in std_ulogic;
59 waddress : in std_logic_vector((abits -1) downto 0);
60 datain : in std_logic_vector((dbits -1) downto 0));
61 end component;
62
63 signal RAD : integer range 0 to addr_max_int;
64 signal WAD : integer range 0 to addr_max_int;
65 signal Raddr : std_logic_vector(addr_sz-1 downto 0);
66 signal Waddr : std_logic_vector(addr_sz-1 downto 0);
67
68 begin
69
70 SRAM : syncram_2p
71 generic map(CFG_MEMTECH,addr_sz,Data_sz)
72 port map(clk,flag_RE,Raddr,Data_out,clk,flag_WR,Waddr,Data_in);
73
74
75 WR : entity work.Fifo_Write
76 port map(clk,raz,flag_WR,RAD,full,WAD,Waddr);
77
78
79 RE : entity work.Fifo_Read
80 port map(clk,raz,flag_RE,WAD,empty,RAD,Raddr);
81
82
83 end ar_Top_FIFO; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,90
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use std.textio.all;
27 library lpp;
28 use lpp.lpp_amba.all;
29 use work.FIFO_Config.all;
30
31 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
32
33 package lpp_fifo is
34
35 component APB_FIFO is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic;
44 rst : in std_logic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type
47 );
48 end component;
49
50
51 component Top_FIFO is
52 port(
53 clk : in std_logic;
54 raz : in std_logic;
55 flag_RE : in std_logic;
56 flag_WR : in std_logic;
57 Data_in : in std_logic_vector(Data_sz-1 downto 0);
58 full : out std_logic;
59 empty : out std_logic;
60 Data_out : out std_logic_vector(Data_sz-1 downto 0)
61 );
62 end component;
63
64
65 component Fifo_Read is
66 port(
67 clk : in std_logic;
68 raz : in std_logic;
69 flag_RE : in std_logic;
70 WAD : in integer range 0 to addr_max_int;
71 empty : out std_logic;
72 RAD : out integer range 0 to addr_max_int;
73 Raddr : out std_logic_vector(addr_sz-1 downto 0)
74 );
75 end component;
76
77
78 component Fifo_Write is
79 port(
80 clk : in std_logic;
81 raz : in std_logic;
82 flag_WR : in std_logic;
83 RAD : in integer range 0 to addr_max_int;
84 full : out std_logic;
85 WAD : out integer range 0 to addr_max_int;
86 Waddr : out std_logic_vector(addr_sz-1 downto 0)
87 );
88 end component;
89
90 end;
Show file before | Show file after | Hide comments
@@ -1,30 +1,32
1 1 # use glob syntax.
2 2 syntax: glob
3 3
4 4 *.tex
5 5 *.html
6 6 *log*
7 7 *.png
8 8 *.dot
9 9 *.css
10 10 *.md5
11 11 *.eps
12 12 *.pdf
13 13 *.toc
14 14 *.map
15 15 *.sty
16 16 *.3
17 17 *.js
18 18 *.aux
19 19 *.idx
20 20 *doc*
21 21 *Doc*
22 22 *vhdlsyn.txt
23 23 *dirs.txt
24 24 *.orig
25 25 *.o
26 26 *.a
27 27 *.bin
28 28 *~
29 29 LPP_drivers/libsrc/AMBA/apb_devices_list.h
30 apb_devices_list.h
30 31 lib/lpp/lpp_amba/apb_devices_list.vhd
32 apb_devices_list.vhd
Show file before | Show file after | Hide comments
@@ -1,12 +1,13
1 1 vendor VENDOR_LPP 19
2 2
3 3 device ROCKET_TM 1
4 4 device otherCore 2
5 5 device LPP_SIMPLE_DIODE 3
6 6 device LPP_MULTI_DIODE 4
7 7 device LPP_LCD_CTRLR 5
8 8 device LPP_UART 6
9 9 device LPP_CNA 7
10 10 device LPP_APB_ADC 8
11 11 device LPP_CHENILLARD 9
12 12 device LPP_IIR_CEL_FILTER 10
13 device LPP_FIFO 11
Show file before | Show file after | Hide comments
1 NO CONTENT: modified file, binary diff hidden
Show file before | Show file after | Hide comments
@@ -1,86 +1,89
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 22 #include "apb_dac_Driver.h"
20 23 #include "lpp_apb_functions.h"
21 24 #include <stdio.h>
22 25
23 26
24 27 DAC_Device* DacOpen(int count)
25 28 {
26 29 DAC_Device* dac0;
27 30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
28 31 dac0->configReg = DAC_enable;
29 32 return dac0;
30 33 }
31 34
32 35 /*
33 36 DAC_Device* DacClose(int count)
34 37 {
35 38 DAC_Device* dac1;
36 39 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
37 40 dac1->configReg = DAC_disable;
38 41 return dac1;
39 42 }
40 43 */
41 44
42 45
43 46 int DacTable()
44 47 {
45 48 int i;
46 49 DAC_Device* dac2;
47 50 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
48 51 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
49 52 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
50 53 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
51 54 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
52 55 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
53 56 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
54 57 dac2 = (DAC_Device*)0x80000800;
55 58 dac2->configReg = DAC_enable;
56 59 dac2->dataReg = tablo[0];
57 60
58 61 while(1)
59 62 {
60 63 for (i = 0 ; i < 251 ; i++)
61 64 {
62 65 while(!((dac2->configReg & DAC_ready) == DAC_ready));
63 66 dac2->dataReg = tablo[i];
64 67 while((dac2->configReg & DAC_ready) == DAC_ready);
65 68 }
66 69 }
67 70 return 0;
68 71 }
69 72
70 73
71 74
72 75 int DacConst()
73 76 {
74 77 DAC_Device* dac3;
75 78 int Value = 0x1FFF;
76 79 dac3 = (DAC_Device*)0x80000800;
77 80 dac3->configReg = DAC_enable;
78 81 while(1)
79 82 {
80 83 printf("\nEntrer une valeur entre 4096 et 8191 : ");
81 84 scanf("%d",&Value);
82 85 dac3->dataReg = Value;
83 86 }
84 87 return 0;
85 88 }
86 89
Show file before | Show file after | Hide comments
@@ -1,53 +1,60
1 1 /*------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------*/
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
19 22 #ifndef APB_CNA_DRIVER_H
20 23 #define APB_CNA_DRIVER_H
21 24
22 25 #define DAC_ready 3
23 26 #define DAC_enable 1
24 27 #define DAC_disable 0
25 28
26 29
27 30 /*===================================================
28 31 T Y P E S D E F
29 32 ====================================================*/
30 33
34 /** Structure reprοΏ½sentant le registre du CNA */
31 35 struct DAC_Driver
32 36 {
33 int configReg;
34 int dataReg;
37 int configReg; /**< Registre de configuration: Flag Ready [1] ; Flag Enable [0] */
38 int dataReg; /**< Registre de donnοΏ½e sur 16 bits */
35 39 };
36 40
37 41 typedef struct DAC_Driver DAC_Device;
38 42
39 43 /*===================================================
40 44 F U N C T I O N S
41 45 ====================================================*/
42 46
47 /** Ouvre l'accοΏ½ au CNA */
43 48 DAC_Device* DacOpen(int count);
44 49
45 50 //DAC_Device* DacClose(int count);
46 51
52 /** Les donnοΏ½es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
47 53 int DacTable();
48 54
55 /** Les donnοΏ½es sont entrοΏ½e par l'utilisateur, la conversion se fait a chaque nouvelle donnοΏ½e */
49 56 int DacConst();
50 57
51 58
52 59
53 60 #endif
Show file before | Show file after | Hide comments
@@ -1,12 +1,12
1 1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
2 4 FILTERcfg.vhd
3 5 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 6 IIR_CEL_CTRLR.vhd
7 7 IIR_CEL_FILTER.vhd
8 iir_filter.vhd
8 RAM.vhd
9 9 RAM_CEL.vhd
10 10 RAM_CTRLR2.vhd
11 RAM.vhd
12 11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
Show file before | Show file after | Hide comments
@@ -1,14 +1,14
1 Adder.vhd
2 1 ADDRcntr.vhd
3 2 ALU.vhd
3 Adder.vhd
4 4 Clk_divider.vhd
5 general_purpose.vhd
5 MAC.vhd
6 6 MAC_CONTROLER.vhd
7 MAC_MUX2.vhd
8 7 MAC_MUX.vhd
8 MAC_MUX2.vhd
9 9 MAC_REG.vhd
10 MAC.vhd
10 MUX2.vhd
11 11 Multiplier.vhd
12 MUX2.vhd
13 12 REG.vhd
14 13 Shifter.vhd
14 general_purpose.vhd
Show file before | Show file after | Hide comments
@@ -1,105 +1,109
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 --use ieee.numeric_std.all;
22 25 library grlib;
23 26 use grlib.amba.all;
24 27 use grlib.stdlib.all;
25 28 use grlib.devices.all;
26 29 library lpp;
30 use lpp.apb_devices_list.all;
27 31 use lpp.lpp_amba.all;
28 32
29 33
30 34 entity APB_MULTI_DIODE is
31 35 generic (
32 36 pindex : integer := 0;
33 37 paddr : integer := 0;
34 38 pmask : integer := 16#fff#;
35 39 pirq : integer := 0;
36 40 abits : integer := 8);
37 41 port (
38 42 rst : in std_ulogic;
39 43 clk : in std_ulogic;
40 44 apbi : in apb_slv_in_type;
41 45 apbo : out apb_slv_out_type;
42 46 LED : out std_logic_vector(2 downto 0)
43 47 );
44 48 end;
45 49
46 50
47 51 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
48 52
49 53 constant REVISION : integer := 1;
50 54
51 55 constant pconfig : apb_config_type := (
52 56 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
53 57 1 => apb_iobar(paddr, pmask));
54 58
55 59
56 60
57 61 type LEDregs is record
58 62 DATAin : std_logic_vector(31 downto 0);
59 63 DATAout : std_logic_vector(31 downto 0);
60 64 end record;
61 65
62 66 signal r : LEDregs;
63 67 signal Rdata : std_logic_vector(31 downto 0);
64 68
65 69
66 70 begin
67 71
68 72 r.DATAout <= r.DATAin xor X"FFFFFFFF";
69 73
70 74 process(rst,clk)
71 75 begin
72 76 if rst = '0' then
73 77 LED <= "000";
74 78 r.DATAin <= (others => '0');
75 79
76 80 elsif clk'event and clk = '1' then
77 81
78 82 LED <= r.DATAin(2 downto 0);
79 83
80 84 --APB Write OP
81 85 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
82 86 case apbi.paddr(abits-1 downto 2) is
83 87 when "000000" =>
84 88 r.DATAin <= apbi.pwdata;
85 89 when others =>
86 90 null;
87 91 end case;
88 92 end if;
89 93
90 94 --APB READ OP
91 95 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
92 96 case apbi.paddr(abits-1 downto 2) is
93 97 when "000000" =>
94 98 Rdata <= r.DATAin;
95 99 when others =>
96 100 Rdata <= r.DATAout;
97 101 end case;
98 102 end if;
99 103
100 104 end if;
101 105 apbo.pconfig <= pconfig;
102 106 end process;
103 107
104 108 apbo.prdata <= Rdata when apbi.penable = '1';
105 109 end ar_APB_MULTI_DIODE;
Show file before | Show file after | Hide comments
@@ -1,130 +1,131
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 --use ieee.numeric_std.all;
25 25 library grlib;
26 26 use grlib.amba.all;
27 27 use grlib.stdlib.all;
28 28 use grlib.devices.all;
29 29 library lpp;
30 use lpp.apb_devices_list.all;
30 31 use lpp.lpp_amba.all;
31 32
32 33
33 34 entity APB_SIMPLE_DIODE is
34 35 generic (
35 36 pindex : integer := 0;
36 37 paddr : integer := 0;
37 38 pmask : integer := 16#fff#;
38 39 pirq : integer := 0;
39 40 abits : integer := 8);
40 41 port (
41 42 rst : in std_ulogic;
42 43 clk : in std_ulogic;
43 44 apbi : in apb_slv_in_type;
44 45 apbo : out apb_slv_out_type;
45 46 LED : out std_ulogic
46 47 );
47 48 end;
48 49
49 50
50 51 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
51 52
52 53 constant REVISION : integer := 1;
53 54
54 55 constant pconfig : apb_config_type := (
55 56 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
56 57 1 => apb_iobar(paddr, pmask));
57 58
58 59
59 60
60 61 type LEDregs is record
61 62 DATAin : std_logic_vector(31 downto 0);
62 63 DATAout : std_logic_vector(31 downto 0);
63 64 end record;
64 65
65 66 signal r : LEDregs;
66 67 signal Rdata : std_logic_vector(31 downto 0);
67 68
68 69 begin
69 70
70 71 r.DATAout <= r.DATAin xor X"FFFFFFFF";
71 72
72 73 process(rst,clk)
73 74 begin
74 75 if rst = '0' then
75 76 LED <= '0';
76 77 r.DATAin <= (others => '0');
77 78
78 79 elsif clk'event and clk = '1' then
79 80
80 81 LED <= r.DATAin(0);
81 82
82 83 --APB Write OP
83 84 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
84 85 case apbi.paddr(abits-1 downto 2) is
85 86 when "000000" =>
86 87 r.DATAin <= apbi.pwdata;
87 88 when others =>
88 89 null;
89 90 end case;
90 91 end if;
91 92
92 93 --APB READ OP
93 94 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
94 95 case apbi.paddr(abits-1 downto 2) is
95 96 when "000000" =>
96 97 Rdata <= r.DATAin;
97 98 when others =>
98 99 Rdata <= r.DATAout;
99 100 end case;
100 101 end if;
101 102
102 103 end if;
103 104 apbo.pconfig <= pconfig;
104 105 end process;
105 106
106 107 apbo.prdata <= Rdata when apbi.penable = '1';
107 108
108 109 -- pragma translate_off
109 110 -- bootmsg : report_version
110 111 -- generic map ("apbuart" & tost(pindex) &
111 112 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
112 113 -- ", irq " & tost(pirq));
113 114 -- pragma translate_on
114 115
115 116
116 117
117 118 end ar_APB_SIMPLE_DIODE;
118 119
119 120
120 121
121 122
122 123
123 124
124 125
125 126
126 127
127 128
128 129
129 130
130 131
Show file before | Show file after | Hide comments
@@ -1,119 +1,123
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- APB_CNA.vhd
20
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 22 library ieee;
22 23 use ieee.std_logic_1164.all;
23 24 library grlib;
24 25 use grlib.amba.all;
25 26 use grlib.stdlib.all;
26 27 use grlib.devices.all;
27 28 library lpp;
28 29 use lpp.lpp_amba.all;
29 30 use lpp.apb_devices_list.all;
30 31 use lpp.lpp_cna.all;
31 32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
32 34
33 35 entity APB_CNA is
34 36 generic (
35 37 pindex : integer := 0;
36 38 paddr : integer := 0;
37 39 pmask : integer := 16#fff#;
38 40 pirq : integer := 0;
39 41 abits : integer := 8);
40 42 port (
41 clk : in std_logic;
42 rst : in std_logic;
43 apbi : in apb_slv_in_type;
44 apbo : out apb_slv_out_type;
45 SYNC : out std_logic;
46 SCLK : out std_logic;
47 DATA : out std_logic
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
48 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
48 50 );
49 51 end APB_CNA;
50 52
53 --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus
54 --! et les sorties seront cablοΏ½es vers le convertisseur.
51 55
52 56 architecture ar_APB_CNA of APB_CNA is
53 57
54 58 constant REVISION : integer := 1;
55 59
56 60 constant pconfig : apb_config_type := (
57 61 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
58 62 1 => apb_iobar(paddr, pmask));
59 63
60 64 signal enable : std_logic;
61 65 signal flag_sd : std_logic;
62 66
63 67 type CNA_ctrlr_Reg is record
64 68 CNA_Cfg : std_logic_vector(1 downto 0);
65 69 CNA_Data : std_logic_vector(15 downto 0);
66 70 end record;
67 71
68 72 signal Rec : CNA_ctrlr_Reg;
69 73 signal Rdata : std_logic_vector(31 downto 0);
70 74
71 75 begin
72 76
73 77 enable <= Rec.CNA_Cfg(0);
74 78 Rec.CNA_Cfg(1) <= flag_sd;
75 79
76 80 CONVERTER : entity Work.CNA_TabloC
77 81 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
78 82
79 83
80 84 process(rst,clk)
81 85 begin
82 86 if(rst='0')then
83 87 Rec.CNA_Data <= (others => '0');
84 88
85 89 elsif(clk'event and clk='1')then
86 90
87 91
88 92 --APB Write OP
89 93 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
90 94 case apbi.paddr(abits-1 downto 2) is
91 95 when "000000" =>
92 96 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
93 97 when "000001" =>
94 98 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
95 99 when others =>
96 100 null;
97 101 end case;
98 102 end if;
99 103
100 104 --APB READ OP
101 105 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
102 106 case apbi.paddr(abits-1 downto 2) is
103 107 when "000000" =>
104 108 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
105 109 Rdata(1 downto 0) <= Rec.CNA_Cfg;
106 110 when "000001" =>
107 111 Rdata(31 downto 16) <= X"FD18";
108 112 Rdata(15 downto 0) <= Rec.CNA_Data;
109 113 when others =>
110 114 Rdata <= (others => '0');
111 115 end case;
112 116 end if;
113 117
114 118 end if;
115 119 apbo.pconfig <= pconfig;
116 120 end process;
117 121
118 122 apbo.prdata <= Rdata when apbi.penable = '1';
119 123 end ar_APB_CNA;
Show file before | Show file after | Hide comments
@@ -1,85 +1,82
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- CNA_TabloC.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25 use work.Convertisseur_config.all;
24 26
27 --! Programme du Convertisseur NumοΏ½rique/Analogique
28
25 29 entity CNA_TabloC is
26 port(
27 clock : in std_logic;
28 rst : in std_logic;
29 enable : in std_logic;
30 --bp : in std_logic;
31 Data_C : in std_logic_vector(15 downto 0);
32 SYNC : out std_logic;
33 SCLK : out std_logic;
34 --Rz : out std_logic;
35 flag_sd : out std_logic;
36 Data : out std_logic
37 );
30 port(
31 clock : in std_logic; --! Horloge du composant
32 rst : in std_logic; --! Reset general du composant
33 enable : in std_logic; --! Autorise ou non l'utilisation du composant
34 Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits
35 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
36 SCLK : out std_logic; --! Horloge systeme du convertisseur
37 flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e
38 Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
39 );
38 40 end CNA_TabloC;
39 41
42 --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits,
43 --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur.
40 44
41 45 architecture ar_CNA_TabloC of CNA_TabloC is
42 46
43 47 component CLKINT
44 48 port( A : in std_logic := 'U';
45 49 Y : out std_logic);
46 50 end component;
47 51
48 52 signal clk : std_logic;
49 53
50 54 signal raz : std_logic;
51 55 signal s_SCLK : std_logic;
52 56 signal OKAI_send : std_logic;
53 --signal Data_int : std_logic_vector(15 downto 0);
54 57
55 58 begin
56 59
57
58 60 CLKINT_0 : CLKINT
59 61 port map(A => clock, Y => clk);
60 62
61 63 CLKINT_1 : CLKINT
62 64 port map(A => rst, Y => raz);
63 65
64 66
65 67 SystemCLK : entity work.Systeme_Clock
66 68 generic map (nb_serial)
67 69 port map (clk,raz,s_SCLK);
68 70
69 71
70 72 Signal_sync : entity work.Gene_SYNC
71 73 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
72 74
73 75
74 76 Serial : entity work.serialize
75 77 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
76 78
77 79
78 --Rz <= raz;
79 80 SCLK <= s_SCLK;
80 81
81 --with bp select
82 -- Data_int <= X"9555" when '1',
83 -- Data_C when others;
84
85 82 end ar_CNA_TabloC; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,42 +1,34
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Convertisseur_config.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25
24 26 Package Convertisseur_config is
25 27
26
27 --===========================================================|
28 --================= Valeurs Sinus 1Khz ======================|
29 --===========================================================|
30 type Tbl is array(natural range <>) of std_logic_vector(11 downto 0);
31 constant Tablo : Tbl (0 to 49):= (X"800",X"901",X"9FD",X"AF2",X"BDB",X"CB4",X"D7A",X"E2A",X"EC1",X"F3D",X"F9C",X"FDC",X"FFC",X"FFC",X"FDC",X"F9C",X"F3D",X"EC1",X"E2A",X"D7A",X"CB4",X"BDB",X"AF2",X"9FD",X"901",X"800",X"6FF",X"603",X"50E",X"425",X"34C",X"286",X"1D6",X"13F",X"0C3",X"064",X"024",X"004",X"004",X"024",X"064",X"0C3",X"13F",X"1D6",X"286",X"34C",X"425",X"50E",X"603",X"6FF");
32
33 --constant Tablo : Tbl (0 to 49):= (X"C00",X"C80",X"CFF",X"D79",X"DED",X"E5A",X"EBD",X"F15",X"F61",X"F9F",X"FCE",X"FEE",X"FFE",X"FFE",X"FEE",X"FCE",X"F9F",X"F61",X"F15",X"EBD",X"E5A",X"DED",X"D79",X"CFF",X"C80",X"C00",X"B80",X"B01",X"A87",X"A13",X"9A6",X"943",X"8EB",X"89F",X"861",X"832",X"812",X"802",X"802",X"812",X"832",X"861",X"89F",X"8EB",X"943",X"9A6",X"A13",X"A87",X"B01",X"B80");
34
35
36 28 --===========================================================|
37 29 --============= FrοΏ½quence de sοΏ½rialisation ==================|
38 30 --===========================================================|
39 31 constant Freq_serial : integer := 5_000_000;
40 32 constant nb_serial : integer := 30_000_000 / Freq_serial;
41 33
42 34 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,71 +1,69
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Gene_SYNC.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25
24 entity Gene_SYNC is
26 --! Programme qui va permettre de gοΏ½nοΏ½rer le signal SYNC
25 27
26 port(
27 SCLK,raz : in std_logic;
28 enable : in std_logic;
29 -- Sysclk : in std_logic;
30 OKAI_send : out std_logic;
31 SYNC : out std_logic
32 );
33
28 entity Gene_SYNC is
29 port(
30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 OKAI_send : out std_logic; --! Flag, Autorise l'envoi (sοΏ½rialisation) d'une nouvelle donnοΏ½e
33 SYNC : out std_logic --! Signal de synchronisation du convertisseur gοΏ½nοΏ½rοΏ½
34 );
34 35 end Gene_SYNC;
35 36
37 --! @details NB: Ce programme est uniquement synchronisοΏ½ sur l'horloge Systeme (sclk)
36 38
37 39 architecture ar_Gene_SYNC of Gene_SYNC is
38 40
39 --signal Sysclk_reg : std_logic;
40 41 signal count : integer;
41 42
42
43 43 begin
44 44 process (SCLK,raz)
45 45 begin
46 46 if(raz='0')then
47 47 SYNC <= '0';
48 -- Sysclk_reg <= '0';
49 48 count <= 14;
50 49 OKAI_send <= '0';
51 50
52 51 elsif(SCLK' event and SCLK='1')then
53 52 if(enable='1')then
54
55 -- Sysclk_reg <= Sysclk;
53
56 54 if(count=15)then
57 55 SYNC <= '1';
58 56 count <= count+1;
59 57 elsif(count=16)then
60 58 count <= 0;
61 59 SYNC <= '0';
62 60 OKAI_send <= '1';
63 61 else
64 62 count <= count+1;
65 63 OKAI_send <= '0';
66 64 end if;
65
67 66 end if;
68 67 end if;
69 end process;
70
68 end process;
71 69 end ar_Gene_SYNC; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,104 +1,107
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Serialize.vhd
20 library IEEE;
21 use IEEE.numeric_std.all;
22 use IEEE.std_logic_1164.all;
23
24 entity Serialize is
25
26 port(
27 clk,raz : in std_logic;
28 sclk : in std_logic;
29 vectin : in std_logic_vector(15 downto 0);
30 send : in std_logic;
31 sended : out std_logic;
32 Data : out std_logic);
33
34 end Serialize;
35
36
37 architecture ar_Serialize of Serialize is
38
39 type etat is (attente,serialize);
40 signal ect : etat;
41
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 --! Programme qui permet de sοΏ½rialiser un vecteur
27
28 entity Serialize is
29 port(
30 clk,raz : in std_logic; --! Horloge et Reset du composant
31 sclk : in std_logic; --! Horloge Systeme
32 vectin : in std_logic_vector(15 downto 0); --! Vecteur d'entrοΏ½e
33 send : in std_logic; --! Flag, Une nouvelle donnοΏ½e est prοΏ½sente
34 sended : out std_logic; --! Flag, La donnοΏ½e a οΏ½tοΏ½ sοΏ½rialisοΏ½e
35 Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
36 );
37 end Serialize;
38
39
40 architecture ar_Serialize of Serialize is
41
42 type etat is (attente,serialize);
43 signal ect : etat;
44
42 45 signal vector_int : std_logic_vector(16 downto 0);
43 signal vectin_reg : std_logic_vector(15 downto 0);
44 signal load : std_logic;
45 signal N : integer range 0 to 16;
46 signal vectin_reg : std_logic_vector(15 downto 0);
47 signal load : std_logic;
48 signal N : integer range 0 to 16;
46 49 signal CPT_ended : std_logic:='0';
47
48 begin
49 process(clk,raz)
50 begin
51 if(raz='0')then
50
51 begin
52 process(clk,raz)
53 begin
54 if(raz='0')then
52 55 ect <= attente;
53 vectin_reg <= (others=> '0');
56 vectin_reg <= (others=> '0');
54 57 load <= '0';
55 sended <= '1';
56
58 sended <= '1';
59
57 60 elsif(clk'event and clk='1')then
58 vectin_reg <= vectin;
59
60 case ect is
61 when attente =>
61 vectin_reg <= vectin;
62
63 case ect is
64 when attente =>
62 65 if (send='1') then
63 66 sended <= '0';
64 67 load <= '1';
65 68 ect <= serialize;
66 69 else
67 ect <= attente;
68 end if;
69
70 ect <= attente;
71 end if;
72
70 73 when serialize =>
71 load <= '0';
72 if(CPT_ended='1')then
74 load <= '0';
75 if(CPT_ended='1')then
73 76 ect <= attente;
74 sended <= '1';
77 sended <= '1';
75 78 end if;
76
77 end case;
78 end if;
79 end process;
80
81 process(sclk,load,raz)
82 begin
83 if (raz='0')then
84 vector_int <= (others=> '0');
85 N <= 16;
86 elsif(load='1')then
87 vector_int <= vectin & '0';
88 N <= 0;
89 elsif(sclk'event and sclk='1')then
90 if (CPT_ended='0') then
91 vector_int <= vector_int(15 downto 0) & '0';
92 N <= N+1;
93 end if;
94 end if;
95 end process;
96
79
80 end case;
81 end if;
82 end process;
83
84 process(sclk,load,raz)
85 begin
86 if (raz='0')then
87 vector_int <= (others=> '0');
88 N <= 16;
89 elsif(load='1')then
90 vector_int <= vectin & '0';
91 N <= 0;
92 elsif(sclk'event and sclk='1')then
93 if (CPT_ended='0') then
94 vector_int <= vector_int(15 downto 0) & '0';
95 N <= N+1;
96 end if;
97 end if;
98 end process;
99
97 100 CPT_ended <= '1' when N = 16 else '0';
98
99 with ect select
100 Data <= vector_int(16) when serialize,
101 '0' when others;
102
103 end ar_Serialize;
104
101
102 with ect select
103 Data <= vector_int(16) when serialize,
104 '0' when others;
105
106 end ar_Serialize;
107
Show file before | Show file after | Hide comments
@@ -1,58 +1,61
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Systeme_Clock.vhd
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
20 22 library IEEE;
21 23 use IEEE.std_logic_1164.all;
22 24 use IEEE.numeric_std.all;
23 25
24 26 --! Programme qui va permetre de gοΏ½nοΏ½rer l'horloge systeme (sclk)
25 27
26 28 entity Systeme_Clock is
27 generic(N :integer := 695); --! GοΏ½nοΏ½rique contenant le rοΏ½sultat de la division clk/sclk
28 port(
29 clk, raz : in std_logic; --! Horloge et Reset globale
29 generic(N :integer := 695); --! GοΏ½nοΏ½rique contenant le rοΏ½sultat de la division clk/sclk
30 port(
31 clk, raz : in std_logic; --! Horloge et Reset globale du composant
30 32 sclk : out std_logic --! Horloge Systeme gοΏ½nοΏ½rοΏ½e
31 );
33 );
32 34 end Systeme_Clock;
33 35
34 36 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
37
35 38 architecture ar_Systeme_Clock of Systeme_Clock is
36 39
37 40 signal clockint : std_logic;
38 41 signal countint : integer range 0 to N/2-1;
39 42
40 43 begin
41 44 process (clk,raz)
42 45 begin
43 46 if(raz = '0') then
44 47 countint <= 0;
45 48 clockint <= '0';
46 49 elsif (clk' event and clk='1') then
47 50 if (countint = N/2-1) then
48 51 countint <= 0;
49 52 clockint <= not clockint;
50 53 else
51 54 countint <= countint+1;
52 55 end if;
53 56 end if;
54 57 end process;
55 58
56 59 sclk <= clockint;
57 60
58 61 end ar_Systeme_Clock; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,95 +1,97
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
22 25 use grlib.amba.all;
23 -- pragma translate_off
24 26 use std.textio.all;
25 -- pragma translate_on
26 27 library lpp;
27 28 use lpp.lpp_amba.all;
28 29
30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
29 31
30 32 package lpp_cna is
31 33
32 34 component APB_CNA is
33 35 generic (
34 36 pindex : integer := 0;
35 37 paddr : integer := 0;
36 38 pmask : integer := 16#fff#;
37 39 pirq : integer := 0;
38 40 abits : integer := 8);
39 41 port (
40 42 clk : in std_logic;
41 43 rst : in std_logic;
42 44 apbi : in apb_slv_in_type;
43 45 apbo : out apb_slv_out_type;
44 46 SYNC : out std_logic;
45 47 SCLK : out std_logic;
46 48 DATA : out std_logic
47 49 );
48 50 end component;
49 51
50 52
51 53 component CNA_TabloC is
52 54 port(
53 55 clock : in std_logic;
54 56 rst : in std_logic;
55 57 flag_nw : in std_logic;
56 58 bp : in std_logic;
57 59 Data_C : in std_logic_vector(15 downto 0);
58 60 SYNC : out std_logic;
59 61 SCLK : out std_logic;
60 62 Rz : out std_logic;
61 63 flag_sd : out std_logic;
62 64 Data : out std_logic
63 65 );
64 66 end component;
65 67
66 68
67 69 component Systeme_Clock is
68 70 generic(N :integer := 695);
69 71 port(
70 72 clk, raz : in std_logic ;
71 73 clock : out std_logic);
72 74 end component;
73 75
74 76
75 77 component Gene_SYNC is
76 78 port(
77 79 clk,raz : in std_logic;
78 80 send : in std_logic;
79 81 Sysclk : in std_logic;
80 82 OKAI_send : out std_logic;
81 83 SYNC : out std_logic);
82 84 end component;
83 85
84 86
85 87 component Serialize is
86 88 port(
87 89 clk,raz : in std_logic;
88 90 sclk : in std_logic;
89 91 vectin : in std_logic_vector(15 downto 0);
90 92 send : in std_logic;
91 93 sended : out std_logic;
92 94 Data : out std_logic);
93 95 end component;
94 96
95 97 end;
Show file before | Show file after | Hide comments
@@ -1,136 +1,146
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
19 22 library ieee;
20 23 use ieee.std_logic_1164.all;
21 24 library grlib;
22 25 use grlib.amba.all;
23 26 use grlib.stdlib.all;
24 27 use grlib.devices.all;
25 28 library lpp;
26 29 use lpp.lpp_amba.all;
27 30 use lpp.apb_devices_list.all;
28 31 use lpp.lpp_uart.all;
29 32
33 --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba
34
30 35 entity APB_UART is
31 36 generic (
32 37 pindex : integer := 0;
33 38 paddr : integer := 0;
34 39 pmask : integer := 16#fff#;
35 40 pirq : integer := 0;
36 41 abits : integer := 8;
37 42 Data_sz : integer := 8);
38 43 port (
39 clk : in std_logic;
40 rst : in std_logic;
41 apbi : in apb_slv_in_type;
42 apbo : out apb_slv_out_type;
43 TXD : out std_logic;
44 RXD : in std_logic
44 clk : in std_logic; --! Horloge du composant
45 rst : in std_logic; --! Reset general du composant
46 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant
49 RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant
45 50 );
46 51 end APB_UART;
47 52
48 53
49 54 architecture ar_APB_UART of APB_UART is
50 55
51 56 constant REVISION : integer := 1;
52 57
53 58 constant pconfig : apb_config_type := (
54 59 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
55 60 1 => apb_iobar(paddr, pmask));
56 61
57 62 signal NwData : std_logic;
58 63 signal ACK : std_logic;
59 64 signal Capture : std_logic;
60 65 signal Send : std_logic;
61 66 signal Sended : std_logic;
62 67
63 68 type UART_ctrlr_Reg is record
64 UART_Cfg : std_logic_vector(4 downto 0);
69 UART_Cfg : std_logic_vector(2 downto 0);
65 70 UART_Wdata : std_logic_vector(7 downto 0);
66 71 UART_Rdata : std_logic_vector(7 downto 0);
67 72 UART_BTrig : std_logic_vector(11 downto 0);
68 73 end record;
69 74
70 75 signal Rec : UART_ctrlr_Reg;
71 76 signal Rdata : std_logic_vector(31 downto 0);
77 signal temp_ND : std_logic;
72 78
73 79 begin
74 80
75 81 Capture <= Rec.UART_Cfg(0);
76 --ACK <= Rec.UART_Cfg(1);
77 --Send <= Rec.UART_Cfg(2);
78 Rec.UART_Cfg(3) <= Sended;
79 Rec.UART_Cfg(4) <= NwData;
82 Rec.UART_Cfg(1) <= Sended;
83 Rec.UART_Cfg(2) <= NwData;
80 84
81 85
82 86 COM0 : entity work.UART
83 87 generic map (Data_sz)
84 88 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
85 89
86 90
87 91 process(rst,clk)
88 92 begin
89 93 if(rst='0')then
90 94 Rec.UART_Wdata <= (others => '0');
91 95
92 96
93 elsif(clk'event and clk='1')then
94
97 elsif(clk'event and clk='1')then
98 temp_ND <= NwData;
99 if(NwData='1' and temp_ND='1')then
100 ACK <= '1';
101 else
102 ACK <= '0';
103 end if;
95 104
96 105 --APB Write OP
97 106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
98 107 case apbi.paddr(7 downto 2) is
99 108 when "000000" =>
100 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
109 Rec.UART_Cfg(0) <= apbi.pwdata(0);
101 110 when "000001" =>
102 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
103 Send <= '1';
111 Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0);
112 Send <= '1';
104 113 when others =>
105 114 null;
106 115 end case;
107 else
108 Send <= '0';
116 else
117 Send <= '0';
109 118 end if;
110 119
111 120 --APB READ OP
112 121 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
113 122 case apbi.paddr(7 downto 2) is
114 123 when "000000" =>
115 Rdata(4 downto 0) <= Rec.UART_Cfg;
116 Rdata(26 downto 12) <= (others => '0');
117 Rdata(27 downto 16) <= Rec.UART_BTrig;
124 Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0);
125 Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1);
126 Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2);
127 Rdata(19 downto 12) <= X"EE";
128 Rdata(31 downto 20) <= Rec.UART_BTrig;
118 129 when "000001" =>
130 Rdata(31 downto 8) <= X"EEEEEE";
119 131 Rdata(7 downto 0) <= Rec.UART_Wdata;
120 132 when "000010" =>
133 Rdata(31 downto 8) <= X"EEEEEE";
121 134 Rdata(7 downto 0) <= Rec.UART_Rdata;
122 Ack <= '1';
123 135 when others =>
124 136 Rdata <= (others => '0');
125 137 end case;
126 else
127 Ack <= '0';
128 138 end if;
129 139
130 140 end if;
131 141 apbo.pconfig <= pconfig;
132 142 end process;
133 143
134 144 apbo.prdata <= Rdata when apbi.penable = '1';
135 145
136 146 end ar_APB_UART;
Show file before | Show file after | Hide comments
@@ -1,112 +1,115
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25
26 26 --! Gestion Reception/Transmission
27 27
28 28 entity Shift_REG is
29 29 generic(Data_sz : integer := 10);
30 30 port(
31 31 clk : in std_logic;
32 32 Sclk : in std_logic;
33 33 reset : in std_logic;
34 34 SIN : in std_logic;
35 35 SOUT : out std_logic;
36 36 Serialize : in std_logic;
37 37 Serialized : out std_logic;
38 38 D : in std_logic_vector(Data_sz-1 downto 0);
39 39 Q : out std_logic_vector(Data_sz-1 downto 0)
40 40 );
41 41 end entity;
42 42
43 43
44 44 architecture ar_Shift_REG of Shift_REG is
45 45
46 46 signal REG : std_logic_vector(Data_sz-1 downto 0);
47 47 signal Serialized_int : std_logic;
48 48 signal Serialize_reg : std_logic;
49 signal Serial_reg : std_logic;
49 50 signal CptBits : std_logic_vector(Data_sz-1 downto 0);
50 51 constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1');
51 52 signal CptBits_flag : std_logic;
52 53 signal CptBits_flag_reg : std_logic;
53 54
54 55 begin
55 56
56 57 Serialized <= Serialized_int;
57 58 CptBits_flag <= '1' when CptBits = CptBits_trig else '0';
58 59
59 60 process(reset,clk)
60 61 begin
61 62 if reset = '0' then
62 63 Serialized_int <= '1';
63 64 CptBits_flag_reg <= '0';
65 Serial_reg <= '0';
64 66 Q <= (others => '0');
65 67 elsif clk'event and clk = '1' then
66 68 CptBits_flag_reg <= CptBits_flag;
69 Serial_reg <= Serialize;
67 70
68 71 if CptBits_flag = '1' and CptBits_flag_reg = '0' then
69 72 Serialized_int <= '1';
70 73 Q <= REG;
71 elsif Serialize = '1' then
74 elsif(Serial_reg='0' and Serialize='1')then
72 75 Serialized_int <= '0';
73 76 end if;
74 77 end if;
75 78 end process;
76 79
77 80
78 81 process(reset,Sclk)
79 82 begin
80 83 if reset = '0' then
81 84 CptBits <= (others => '0');
82 85 REG <= (others => '0');
83 86 SOUT <= '1';
84 87 Serialize_reg <= '0';
85 88 elsif Sclk'event and Sclk = '1' then
86 89 Serialize_reg <= Serialized_int;
87 90 if (Serialized_int = '0' and Serialize_reg ='1') then
88 91 REG <= SIN & D(Data_sz-1 downto 1);
89 92 SOUT <= D(0);
90 93 elsif CptBits_flag ='1' then
91 94 REG <= SIN & D(Data_sz-1 downto 1);
92 95 SOUT <= D(0);
93 96 elsif Serialized_int = '0' then
94 97 REG <= SIN & REG(Data_sz-1 downto 1);
95 98 SOUT <= REG(0);
96 99 else
97 100 SOUT <= '1';
98 101 end if;
99 102 if Serialized_int = '0' then
100 103 if CptBits_flag = '1' then
101 104 CptBits <= (others => '0');
102 105 else
103 106 CptBits <= '1' & CptBits(Data_sz-1 downto 1);
104 107 end if;
105 108 else
106 109 CptBits <= (others => '0');
107 110 end if;
108 111
109 112 end if;
110 113 end process;
111 114
112 115 end ar_Shift_REG;
Show file before | Show file after | Hide comments
@@ -1,106 +1,106
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.numeric_std.all;
24 24 use IEEE.std_logic_1164.all;
25 25 library lpp;
26 26 use lpp.lpp_uart.all;
27 27
28 28 --! Programme qui va gerer toute la communication entre le PC et le FPGA
29 29
30 30 entity UART is
31 31 generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee
32 32 port(
33 33 clk : in std_logic; --! Horloge a 25Mhz du systeme
34 34 reset : in std_logic; --! Reset du systeme
35 35 TXD : out std_logic; --! Transmission, cote PC
36 36 RXD : in std_logic; --! Reception, cote PC
37 37 Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global
38 38 NwDat : out std_logic; --! Flag, Nouvelle donnee presente
39 39 ACK : in std_logic; --! Flag, Reponse au flag precedent
40 40 Send : in std_logic; --! Flag, Demande d'envoi sur le bus
41 41 Sended : out std_logic; --! Flag, Envoi termine
42 42 BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission
43 43 RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Mot de donnee en provenance de l'utilisateur
44 44 WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur
45 45 );
46 46 end entity;
47 47
48
49 48 --! @details Gestion de la Reception/Transmission donc de la Vectorisation/Serialisation
50 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
49 --! ainsi que la detection et le reglage de le frequence de transmission optimale sur le bus (Generateur de Bauds)
50
51 51 architecture ar_UART of UART is
52 52 signal Bclk : std_logic;
53 53
54 54 signal RDATA_int : std_logic_vector(Data_sz+1 downto 0);
55 55 signal WDATA_int : std_logic_vector(Data_sz+1 downto 0);
56 56
57 57 signal TXD_Dummy : std_logic;
58 58 signal NwDat_int : std_logic;
59 59 signal NwDat_int_reg : std_logic;
60 60 signal receive : std_logic;
61 61 constant zeroVect : std_logic_vector(Data_sz+1 downto 0) := (others => '0');
62 62
63 63 begin
64 64
65 65
66 66
67 67 WDATA_int <= '1' & WDATA & '0';
68 68
69 69 BaudGenerator : BaudGen
70 70 port map(clk,reset,Capture,Bclk,RXD,BTrigger);
71 71
72 72
73 73 RX_REG : Shift_REG
74 74 generic map(Data_sz+2)
75 75 port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int);
76 76
77 77 TX_REG : Shift_REG
78 78 generic map(Data_sz+2)
79 79 port map(clk,Bclk,reset,'1',TXD,Send,Sended,WDATA_int);
80 80
81 81
82 82
83 83 process(clk,reset)
84 84 begin
85 85 if reset = '0' then
86 86 NwDat <= '0';
87 87 elsif clk'event and clk = '1' then
88 88 NwDat_int_reg <= NwDat_int;
89 89 if RXD = '1' and NwDat_int = '1' then
90 90 receive <= '0';
91 91 elsif RXD = '0' then
92 92 receive <= '1';
93 93 end if;
94 94 if NwDat_int_reg = '0' and NwDat_int = '1' then
95 95 NwDat <= '1';
96 96 RDATA <= RDATA_int(8 downto 1);
97 97 elsif ack = '1' then
98 98 NwDat <= '0';
99 99 end if;
100 100 end if;
101 101 end process;
102 102
103 103 end ar_UART;
104 104
105 105
106 106
General Comments 0
You need to be logged in to leave comments. Login now