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update CAL 2/2 + driver C
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_cna.all;
32 32
33 33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34 34
35 35 entity APB_CNA is
36 36 generic (
37 37 pindex : integer := 0;
38 38 paddr : integer := 0;
39 39 pmask : integer := 16#fff#;
40 40 pirq : integer := 0;
41 41 abits : integer := 8);
42 42 port (
43 43 clk : in std_logic; --! Horloge du composant
44 44 rst : in std_logic; --! Reset general du composant
45 45 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
46 46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
47 48 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
48 49 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 50 DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
50 51 );
51 52 end APB_CNA;
52 53
53 54 --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus
54 55 --! et les sorties seront cablοΏ½es vers le convertisseur.
55 56
56 57 architecture ar_APB_CNA of APB_CNA is
57 58
58 59 constant REVISION : integer := 1;
59 60
60 61 constant pconfig : apb_config_type := (
61 62 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
62 63 1 => apb_iobar(paddr, pmask));
63 64
64 65 signal enable : std_logic;
65 66 signal flag_sd : std_logic;
66 67
67 68 type CNA_ctrlr_Reg is record
68 69 CNA_Cfg : std_logic_vector(1 downto 0);
69 70 CNA_Data : std_logic_vector(15 downto 0);
70 71 end record;
71 72
72 73 signal Rec : CNA_ctrlr_Reg;
73 74 signal Rdata : std_logic_vector(31 downto 0);
74 75
75 76 begin
76 77
77 78 enable <= Rec.CNA_Cfg(0);
78 79 Rec.CNA_Cfg(1) <= flag_sd;
79 80
80 81 CONVERTER : CNA_TabloC
81 82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
82 83
83 84
84 85 process(rst,clk)
85 86 begin
86 87 if(rst='0')then
87 88 Rec.CNA_Data <= (others => '0');
88 89
89 90 elsif(clk'event and clk='1')then
90 91
91 92
92 93 --APB Write OP
93 94 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
94 95 case apbi.paddr(abits-1 downto 2) is
95 96 when "000000" =>
96 97 Rec.CNA_Cfg(0) <= apbi.pwdata(0);
97 98 when "000001" =>
98 99 Rec.CNA_Data <= apbi.pwdata(15 downto 0);
99 100 when others =>
100 101 null;
101 102 end case;
102 103 end if;
103 104
104 105 --APB READ OP
105 106 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
106 107 case apbi.paddr(abits-1 downto 2) is
107 108 when "000000" =>
108 109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
109 110 Rdata(1 downto 0) <= Rec.CNA_Cfg;
110 111 when "000001" =>
111 112 Rdata(31 downto 16) <= X"FD18";
112 113 Rdata(15 downto 0) <= Rec.CNA_Data;
113 114 when others =>
114 115 Rdata <= (others => '0');
115 116 end case;
116 117 end if;
117 118
118 119 end if;
119 120 apbo.pconfig <= pconfig;
120 121 end process;
121 122
122 123 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
123 125 end ar_APB_CNA;
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@@ -1,82 +1,67
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 use work.Convertisseur_config.all;
26 26
27 27 --! Programme du Convertisseur NumοΏ½rique/Analogique
28 28
29 29 entity CNA_TabloC is
30 30 port(
31 clock : in std_logic; --! Horloge du composant
31 clk : in std_logic; --! Horloge du composant
32 32 rst : in std_logic; --! Reset general du composant
33 33 enable : in std_logic; --! Autorise ou non l'utilisation du composant
34 34 Data_C : in std_logic_vector(15 downto 0); --! DonnοΏ½e NumοΏ½rique d'entrοΏ½e sur 16 bits
35 35 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
36 36 SCLK : out std_logic; --! Horloge systeme du convertisseur
37 37 flag_sd : out std_logic; --! Flag, signale la fin de la sοΏ½rialisation d'une donnοΏ½e
38 38 Data : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½
39 39 );
40 40 end CNA_TabloC;
41 41
42 42 --! @details Un driver C va permettre de gοΏ½nerer un tableau de donnοΏ½es sur 16 bits,
43 43 --! qui seront sοΏ½rialisοΏ½ pour οΏ½tre ensuite dirigοΏ½es vers le convertisseur.
44 44
45 45 architecture ar_CNA_TabloC of CNA_TabloC is
46 46
47 --component CLKINT
48 --port( A : in std_logic := 'U';
49 -- Y : out std_logic);
50 --end component;
51
52 --signal clk : std_logic;
53
54 --signal raz : std_logic;
55 47 signal s_SCLK : std_logic;
56 48 signal OKAI_send : std_logic;
57 49
58 50 begin
59 51
60 --CLKINT_0 : CLKINT
61 -- port map(A => clock, Y => clk);
62
63 --CLKINT_1 : CLKINT
64 -- port map(A => rst, Y => raz);
65
66
67 52 SystemCLK : entity work.Systeme_Clock
68 53 generic map (nb_serial)
69 port map (clock,rst,s_SCLK);
54 port map (clk,rst,s_SCLK);
70 55
71 56
72 57 Signal_sync : entity work.Gene_SYNC
73 58 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
74 59
75 60
76 61 Serial : entity work.serialize
77 port map (clock,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
62 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
78 63
79 64
80 65 SCLK <= s_SCLK;
81 66
82 67 end ar_CNA_TabloC; No newline at end of file
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@@ -1,95 +1,96
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
31 31
32 32 package lpp_cna is
33 33
34 34 component APB_CNA is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8);
41 41 port (
42 42 clk : in std_logic;
43 43 rst : in std_logic;
44 44 apbi : in apb_slv_in_type;
45 45 apbo : out apb_slv_out_type;
46 Cal_EN : out std_logic;
46 47 SYNC : out std_logic;
47 48 SCLK : out std_logic;
48 49 DATA : out std_logic
49 50 );
50 51 end component;
51 52
52 53
53 54 component CNA_TabloC is
54 55 port(
55 clock : in std_logic;
56 clk : in std_logic;
56 57 rst : in std_logic;
57 58 enable : in std_logic;
58 59 Data_C : in std_logic_vector(15 downto 0);
59 60 SYNC : out std_logic;
60 61 SCLK : out std_logic;
61 62 flag_sd : out std_logic;
62 63 Data : out std_logic
63 64 );
64 65 end component;
65 66
66 67
67 68 component Systeme_Clock is
68 69 generic(N :integer := 695);
69 70 port(
70 71 clk, raz : in std_logic ;
71 72 clock : out std_logic);
72 73 end component;
73 74
74 75
75 76 component Gene_SYNC is
76 77 port(
77 78 clk,raz : in std_logic;
78 79 send : in std_logic;
79 80 Sysclk : in std_logic;
80 81 OKAI_send : out std_logic;
81 82 SYNC : out std_logic);
82 83 end component;
83 84
84 85
85 86 component Serialize is
86 87 port(
87 88 clk,raz : in std_logic;
88 89 sclk : in std_logic;
89 90 vectin : in std_logic_vector(15 downto 0);
90 91 send : in std_logic;
91 92 sended : out std_logic;
92 93 Data : out std_logic);
93 94 end component;
94 95
95 96 end;
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