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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
27 LIBRARY lpp;
28 USE lpp.lpp_ad_conv.ALL;
29 USE lpp.iir_filter.ALL;
30 USE lpp.FILTERcfg.ALL;
31 USE lpp.lpp_memory.ALL;
32 USE lpp.lpp_waveform_pkg.ALL;
33 USE lpp.lpp_dma_pkg.ALL;
34 USE lpp.lpp_top_lfr_pkg.ALL;
35 USE lpp.lpp_lfr_pkg.ALL;
36 USE lpp.general_purpose.ALL;
37 USE lpp.lpp_lfr_pkg.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.iir_filter.ALL;
40 USE lpp.spectral_matrix_package.ALL;
41 USE lpp.lpp_fft.ALL;
42 USE lpp.fft_components.ALL;
43 USE lpp.CY7C1061DV33_pkg.ALL;
44 USE lpp.testbench_package.ALL;
45
46
47 LIBRARY grlib;
48 USE grlib.amba.ALL;
49 USE grlib.stdlib.ALL;
50 USE grlib.devices.ALL;
51 USE GRLIB.DMA2AHB_Package.ALL;
52
53 LIBRARY gaisler;
54 USE gaisler.memctrl.ALL;
55 USE gaisler.misc.ALL;
56
57 LIBRARY techmap;
58 USE techmap.gencomp.ALL;
59
60 LIBRARY esa;
61 USE esa.memoryctrl.ALL;
62
63
64 ENTITY TB IS
65 END TB;
66
67
68 ARCHITECTURE beh OF TB IS
69 CONSTANT INDEX_LFR : INTEGER := 15;
70 CONSTANT ADDR_LFR : INTEGER := 15;
71 -- REG MS
72 CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00";
73 CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04";
74 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08";
75 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C";
76
77 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10";
78 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14";
79 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18";
80 CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C";
81
82 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20";
83 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24";
84 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28";
85 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C";
86
87 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30";
88 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34";
89 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38";
90 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C";
91
92 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40";
93 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44";
94 CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48";
95 CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C";
96
97 -- REG WAVEFORM
98 CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50";
99 CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54";
100 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58";
101 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C";
102
103 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60";
104 CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64";
105 CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68";
106 CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C";
107
108 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70";
109 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74";
110 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78";
111 CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C";
112
113 CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F80";
114 CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F84";
115 CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F88";
116 CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F8C";
117 -- RAM ADDRESS
118 CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#;
119 CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#;
120 CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#;
121 CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#;
122
123
124 -- Common signal
125 SIGNAL clk49_152MHz : STD_LOGIC := '0';
126 SIGNAL clk25MHz : STD_LOGIC := '0';
127 SIGNAL rstn : STD_LOGIC := '0';
128
129 -- ADC interface
130 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT
131 SIGNAL ADC_smpclk : STD_LOGIC; -- OUT
132 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN
133
134 -- AD Converter RHF1401
135 SIGNAL sample : Samples14v(7 DOWNTO 0);
136 SIGNAL sample_s : Samples(7 DOWNTO 0);
137 SIGNAL sample_val : STD_LOGIC;
138
139 -- AHB/APB SIGNAL
140 SIGNAL apbi : apb_slv_in_type;
141 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
142 SIGNAL ahbsi : ahb_slv_in_type;
143 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
144 SIGNAL ahbmi : ahb_mst_in_type;
145 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
146
147 SIGNAL bias_fail_bw : STD_LOGIC;
148
149 -----------------------------------------------------------------------------
150 -- LPP_WAVEFORM
151 -----------------------------------------------------------------------------
152 CONSTANT data_size : INTEGER := 96;
153 CONSTANT nb_burst_available_size : INTEGER := 50;
154 CONSTANT nb_snapshot_param_size : INTEGER := 2;
155 CONSTANT delta_vector_size : INTEGER := 2;
156 CONSTANT delta_vector_size_f0_2 : INTEGER := 2;
157
158 SIGNAL reg_run : STD_LOGIC;
159 SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
160 SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
161 SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
163 SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
164 SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL enable_f0 : STD_LOGIC;
166 SIGNAL enable_f1 : STD_LOGIC;
167 SIGNAL enable_f2 : STD_LOGIC;
168 SIGNAL enable_f3 : STD_LOGIC;
169 SIGNAL burst_f0 : STD_LOGIC;
170 SIGNAL burst_f1 : STD_LOGIC;
171 SIGNAL burst_f2 : STD_LOGIC;
172 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
174 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
180 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL data_f0_in_valid : STD_LOGIC;
182 SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
183 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f1_in_valid : STD_LOGIC;
185 SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
186 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f2_in_valid : STD_LOGIC;
188 SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
189 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f3_in_valid : STD_LOGIC;
191 SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
192 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 SIGNAL data_f0_data_out_valid : STD_LOGIC;
195 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
196 SIGNAL data_f0_data_out_ack : STD_LOGIC;
197 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f1_data_out_valid : STD_LOGIC;
200 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f1_data_out_ack : STD_LOGIC;
202 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f2_data_out_valid : STD_LOGIC;
205 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
206 SIGNAL data_f2_data_out_ack : STD_LOGIC;
207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
211 SIGNAL data_f3_data_out_ack : STD_LOGIC;
212
213 --MEM CTRLR
214 SIGNAL memi : memory_in_type;
215 SIGNAL memo : memory_out_type;
216 SIGNAL wpo : wprot_out_type;
217 SIGNAL sdo : sdram_out_type;
218
219 SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000";
220 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL nSRAM_BE0 : STD_LOGIC;
222 SIGNAL nSRAM_BE1 : STD_LOGIC;
223 SIGNAL nSRAM_BE2 : STD_LOGIC;
224 SIGNAL nSRAM_BE3 : STD_LOGIC;
225 SIGNAL nSRAM_WE : STD_LOGIC;
226 SIGNAL nSRAM_CE : STD_LOGIC;
227 SIGNAL nSRAM_OE : STD_LOGIC;
228
229 CONSTANT padtech : INTEGER := inferred;
230 SIGNAL not_ramsn_0 : STD_LOGIC;
231
232 -----------------------------------------------------------------------------
233 SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0);
234 SIGNAL read_buffer : STD_LOGIC;
235 -----------------------------------------------------------------------------
236 SIGNAL run_test_waveform_picker : STD_LOGIC := '1';
237 SIGNAL state_read_buffer_on_going : STD_LOGIC;
238 CONSTANT hindex : INTEGER := 1;
239 SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0);
240 SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0);
241 SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0);
242 SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0);
243
244 SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245 SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
246 SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
247 SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
248
249 SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
250 SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
251 SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
252
253 SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
254 SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
255 SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
256
257 SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
258 SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
259 SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
260
261 SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
262 SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
263 SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
264
265 SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
266 SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
267 SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
268
269 SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
270 SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
271 SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
272 -----------------------------------------------------------------------------
273
274 SIGNAL current_data : INTEGER;
275 SIGNAL LIMIT_DATA : INTEGER := 64;
276
277 SIGNAL read_buffer_temp : STD_LOGIC;
278 SIGNAL read_buffer_temp_2 : STD_LOGIC;
279
280
281 BEGIN
282
283 -----------------------------------------------------------------------------
284
285 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
286 clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz
287
288 -----------------------------------------------------------------------------
289
290 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
291 TestModule_RHF1401_1 : TestModule_RHF1401
292 GENERIC MAP (
293 freq => 24*(I+1),
294 amplitude => 8000/(I+1),
295 impulsion => 0)
296 PORT MAP (
297 ADC_smpclk => ADC_smpclk,
298 ADC_OEB_bar => ADC_OEB_bar_CH(I),
299 ADC_data => ADC_data);
300 END GENERATE MODULE_RHF1401;
301
302 -----------------------------------------------------------------------------
303
304 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
305 GENERIC MAP (
306 ChanelCount => 8,
307 ncycle_cnv_high => 79,
308 ncycle_cnv => 500)
309 PORT MAP (
310 cnv_clk => clk49_152MHz,
311 cnv_rstn => rstn,
312 cnv => ADC_smpclk,
313 clk => clk25MHz,
314 rstn => rstn,
315 ADC_data => ADC_data,
316 ADC_nOE => ADC_OEB_bar_CH,
317 sample => sample,
318 sample_val => sample_val);
319 -----------------------------------------------------------------------------
320
321
322 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
323 sample_s(I) <= sample(I) & '0' & '0';
324 END GENERATE all_sample;
325 -----------------------------------------------------------------------------
326
327 lpp_lfr_1 : lpp_lfr
328 GENERIC MAP (
329 Mem_use => use_CEL, -- use_RAM
330 nb_data_by_buffer_size => 32,
331 nb_word_by_buffer_size => 30,
332 nb_snapshot_param_size => 32,
333 delta_vector_size => 32,
334 delta_vector_size_f0_2 => 32,
335 pindex => INDEX_LFR,
336 paddr => ADDR_LFR,
337 pmask => 16#fff#,
338 pirq_ms => 6,
339 pirq_wfp => 14,
340 hindex => 0,
341 top_lfr_version => X"000001")
342 PORT MAP (
343 clk => clk25MHz,
344 rstn => rstn,
345 sample_B => sample_s(2 DOWNTO 0),
346 sample_E => sample_s(7 DOWNTO 3),
347 sample_val => sample_val,
348 apbi => apbi,
349 apbo => apbo(15),
350 ahbi => ahbmi,
351 ahbo => ahbmo(0),
352 coarse_time => coarse_time,
353 fine_time => fine_time,
354 data_shaping_BW => bias_fail_bw);
355
356 -----------------------------------------------------------------------------
357 --- AHB CONTROLLER -------------------------------------------------
358 ahb0 : ahbctrl -- AHB arbiter/multiplexer
359 GENERIC MAP (defmast => 0, split => 0,
360 rrobin => 1, ioaddr => 16#FFF#,
361 ioen => 0, nahbm => 2, nahbs => 1)
362 PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso);
363
364
365
366 --- AHB RAM ----------------------------------------------------------
367 --ahbram0 : ahbram
368 -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0)
369 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0));
370 --ahbram1 : ahbram
371 -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0)
372 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1));
373 --ahbram2 : ahbram
374 -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0)
375 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2));
376 --ahbram3 : ahbram
377 -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0)
378 -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3));
379
380 -----------------------------------------------------------------------------
381 ----------------------------------------------------------------------
382 --- Memory controllers ---------------------------------------------
383 ----------------------------------------------------------------------
384 memctrlr : mctrl GENERIC MAP (
385 hindex => 0,
386 pindex => 0,
387 paddr => 0,
388 srbanks => 1
389 )
390 PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
391
392 memi.brdyn <= '1';
393 memi.bexcn <= '1';
394 memi.writen <= '1';
395 memi.wrn <= "1111";
396 memi.bwidth <= "10";
397
398 bdr : FOR i IN 0 TO 3 GENERATE
399 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
400 PORT MAP (
401 data(31-i*8 DOWNTO 24-i*8),
402 memo.data(31-i*8 DOWNTO 24-i*8),
403 memo.bdrive(i),
404 memi.data(31-i*8 DOWNTO 24-i*8));
405 END GENERATE;
406
407 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
408 PORT MAP (address, memo.address(21 DOWNTO 2));
409
410 not_ramsn_0 <= NOT(memo.ramsn(0));
411
412 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0);
413 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
414 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
415 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
416 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
417 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
418 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
419
420 async_1Mx16_0 : CY7C1061DV33
421 GENERIC MAP (
422 ADDR_BITS => 20,
423 DATA_BITS => 16,
424 depth => 1048576,
425 MEM_ARRAY_DEBUG => 32,
426 TimingInfo => true,
427 TimingChecks => '1')
428 PORT MAP (
429 CE1_b => '0',
430 CE2 => nSRAM_CE,
431 WE_b => nSRAM_WE,
432 OE_b => nSRAM_OE,
433 BHE_b => nSRAM_BE1,
434 BLE_b => nSRAM_BE0,
435 A => address,
436 DQ => data(15 DOWNTO 0));
437
438 async_1Mx16_1 : CY7C1061DV33
439 GENERIC MAP (
440 ADDR_BITS => 20,
441 DATA_BITS => 16,
442 depth => 1048576,
443 MEM_ARRAY_DEBUG => 32,
444 TimingInfo => true,
445 TimingChecks => '1')
446 PORT MAP (
447 CE1_b => '0',
448 CE2 => nSRAM_CE,
449 WE_b => nSRAM_WE,
450 OE_b => nSRAM_OE,
451 BHE_b => nSRAM_BE3,
452 BLE_b => nSRAM_BE2,
453 A => address,
454 DQ => data(31 DOWNTO 16));
455
456
457 -----------------------------------------------------------------------------
458
459 WaveGen_Proc : PROCESS
460 BEGIN
461
462 -- insert signal assignments here
463 WAIT UNTIL clk25MHz = '1';
464 rstn <= '0';
465 apbi.psel(15) <= '0';
466 apbi.pwrite <= '0';
467 apbi.penable <= '0';
468 apbi.paddr <= (OTHERS => '0');
469 apbi.pwdata <= (OTHERS => '0');
470 fine_time <= (OTHERS => '0');
471 coarse_time <= (OTHERS => '0');
472 WAIT UNTIL clk25MHz = '1';
473 -- ahbmi.HGRANT(2) <= '1';
474 -- ahbmi.HREADY <= '1';
475 -- ahbmi.HRESP <= HRESP_OKAY;
476
477 WAIT UNTIL clk25MHz = '1';
478 WAIT UNTIL clk25MHz = '1';
479 rstn <= '1';
480 WAIT UNTIL clk25MHz = '1';
481 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"40000000");
482 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"40020000");
483 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"40040000");
484 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 , X"40060000");
485
486 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000007");
487 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000");
488
489 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
490 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
491 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
492 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
493
494 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020"); --"00000020"
495 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019"); --"00000019"
496 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007"); --"00000007"
497 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019"); --"00000019"
498 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001"); --"00000001"
499
500 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
501 --
502 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010");
503 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
504 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022");
505
506
507 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080");
508 WAIT UNTIL clk25MHz = '1';
509 ---------------------------------------------------------------------------
510 -- CONFIGURATION STEP
511 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000");
512 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000");
513 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
514 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
515
516 WAIT UNTIL clk25MHz = '1';
517 WAIT UNTIL clk25MHz = '1';
518
519
520 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000097");
521 WAIT UNTIL clk25MHz = '1';
522 WAIT UNTIL clk25MHz = '1';
523 WAIT UNTIL clk25MHz = '1';
524 WAIT UNTIL clk25MHz = '1';
525 WAIT UNTIL clk25MHz = '1';
526 WAIT UNTIL clk25MHz = '1';
527 WAIT FOR 1 us;
528 coarse_time <= X"00000001";
529 ---------------------------------------------------------------------------
530 -- RUN STEP
531 WAIT FOR 200 ms;
532 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
533 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010");
534 WAIT FOR 10 us;
535 WAIT UNTIL clk25MHz = '1';
536 WAIT UNTIL clk25MHz = '1';
537 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF");
538 WAIT UNTIL clk25MHz = '1';
539 coarse_time <= X"00000010";
540 WAIT FOR 100 ms;
541 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000");
542 WAIT FOR 10 us;
543 APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF");
544 WAIT FOR 200 ms;
545 REPORT "*** END simulation ***" SEVERITY failure;
546
547
548 WAIT;
549
550 END PROCESS WaveGen_Proc;
551 -----------------------------------------------------------------------------
552
553 -----------------------------------------------------------------------------
554 -- IRQ
555 -----------------------------------------------------------------------------
556 PROCESS (clk25MHz, rstn)
557 BEGIN -- PROCESS
558 IF rstn = '0' THEN -- asynchronous reset (active low)
559
560 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
561
562 END IF;
563 END PROCESS;
564 -----------------------------------------------------------------------------
565
566 END beh;
567
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@@ -0,0 +1,3
1 log -R *
2 do wave.do
3 run -all No newline at end of file
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@@ -0,0 +1,136
1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
7 --LIBRARY gaisler;
8 --USE gaisler.libdcom.ALL;
9 --USE gaisler.sim.ALL;
10 --USE gaisler.jtagtst.ALL;
11 --LIBRARY techmap;
12 --USE techmap.gencomp.ALL;
13
14
15 PACKAGE testbench_package IS
16
17 PROCEDURE APB_WRITE (
18 SIGNAL clk : IN STD_LOGIC;
19 CONSTANT pindex : IN INTEGER;
20 SIGNAL apbi : OUT apb_slv_in_type;
21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
23 );
24
25 PROCEDURE APB_READ (
26 SIGNAL clk : IN STD_LOGIC;
27 CONSTANT pindex : IN INTEGER;
28 SIGNAL apbi : OUT apb_slv_in_type;
29 SIGNAL apbo : IN apb_slv_out_type;
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
32 );
33
34 PROCEDURE AHB_READ (
35 SIGNAL clk : IN STD_LOGIC;
36 CONSTANT hindex : IN INTEGER;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
41 );
42
43 END testbench_package;
44
45 PACKAGE BODY testbench_package IS
46
47 PROCEDURE APB_WRITE (
48 SIGNAL clk : IN STD_LOGIC;
49 CONSTANT pindex : IN INTEGER;
50 SIGNAL apbi : OUT apb_slv_in_type;
51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 ) IS
54 BEGIN
55 apbi.psel(pindex) <= '1';
56 apbi.pwrite <= '1';
57 apbi.penable <= '1';
58 apbi.paddr <= paddr;
59 apbi.pwdata <= pwdata;
60 WAIT UNTIL clk = '0';
61 WAIT UNTIL clk = '1';
62 apbi.psel(pindex) <= '0';
63 apbi.pwrite <= '0';
64 apbi.penable <= '0';
65 apbi.paddr <= (OTHERS => '0');
66 apbi.pwdata <= (OTHERS => '0');
67 WAIT UNTIL clk = '0';
68 WAIT UNTIL clk = '1';
69
70 END APB_WRITE;
71
72 PROCEDURE APB_READ (
73 SIGNAL clk : IN STD_LOGIC;
74 CONSTANT pindex : IN INTEGER;
75 SIGNAL apbi : OUT apb_slv_in_type;
76 SIGNAL apbo : IN apb_slv_out_type;
77 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
79 ) IS
80 BEGIN
81 apbi.psel(pindex) <= '1';
82 apbi.pwrite <= '0';
83 apbi.penable <= '1';
84 apbi.paddr <= paddr;
85 WAIT UNTIL clk = '0';
86 WAIT UNTIL clk = '1';
87 apbi.psel(pindex) <= '0';
88 apbi.pwrite <= '0';
89 apbi.penable <= '0';
90 apbi.paddr <= (OTHERS => '0');
91 WAIT UNTIL clk = '0';
92 WAIT UNTIL clk = '1';
93 prdata <= apbo.prdata;
94 END APB_READ;
95
96 PROCEDURE AHB_READ (
97 SIGNAL clk : IN STD_LOGIC;
98 CONSTANT hindex : IN INTEGER;
99 SIGNAL ahbmi : IN ahb_mst_in_type;
100 SIGNAL ahbmo : OUT ahb_mst_out_type;
101 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 ) IS
104 BEGIN
105 WAIT UNTIL clk = '1';
106 ahbmo.HADDR <= haddr;
107 ahbmo.HPROT <= "0011";
108 ahbmo.HIRQ <= (OTHERS => '0');
109 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
110 ahbmo.HINDEX <= hindex;
111 ahbmo.HBUSREQ <= '1';
112 ahbmo.HLOCK <= '1';
113 ahbmo.HSIZE <= HSIZE_WORD;
114 ahbmo.HBURST <= HBURST_SINGLE;
115 ahbmo.HTRANS <= HTRANS_NONSEQ;
116 ahbmo.HWRITE <= '0';
117 WHILE ahbmi.HREADY = '0' LOOP
118 WAIT UNTIL clk = '1';
119 END LOOP;
120 WAIT UNTIL clk = '1';
121 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
122 ahbmo.HBUSREQ <= '0';
123 ahbmo.HLOCK <= '0';
124 ahbmo.HTRANS <= HTRANS_IDLE;
125 WHILE ahbmi.HREADY = '0' LOOP
126 WAIT UNTIL clk = '1';
127 END LOOP;
128 WAIT UNTIL clk = '1';
129 hrdata <= ahbmi.HRDATA;
130 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
131 ahbmo.HLOCK <= '0';
132 WAIT UNTIL clk = '1';
133
134 END AHB_READ;
135
136 END testbench_package;
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@@ -0,0 +1,69
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
4 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
5 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
6 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
7 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
8 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
9 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
10 add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
11 add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable
12 add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable
13 add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot
14 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on
15 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s
16 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre
17 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount
18 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init
19 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot
20 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0
21 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0
22 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid
23 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid
24 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0
25 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1
26 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2
27 add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on
28 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in
29 add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out
30 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send
31 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst
32 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done
33 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren
34 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address
35 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data
36 add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay
37 add wave -noupdate /tb/async_1mx16_0/ce1_b
38 add wave -noupdate /tb/async_1mx16_0/ce2
39 add wave -noupdate /tb/async_1mx16_0/we_b
40 add wave -noupdate /tb/async_1mx16_0/oe_b
41 add wave -noupdate /tb/async_1mx16_0/bhe_b
42 add wave -noupdate /tb/async_1mx16_0/ble_b
43 add wave -noupdate /tb/async_1mx16_0/a
44 add wave -noupdate /tb/async_1mx16_0/dq
45 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0
46 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_1
47 add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2
48 add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3
49 add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(7) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(6) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(5) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(4) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(3) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(2) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(1) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(0) {-radix unsigned}} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect
50 add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd
51 TreeUpdate [SetDefaultTree]
52 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {209437155 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0}
53 configure wave -namecolwidth 618
54 configure wave -valuecolwidth 472
55 configure wave -justifyvalue left
56 configure wave -signalnamewidth 0
57 configure wave -snapdistance 10
58 configure wave -datasetprefix 0
59 configure wave -rowmargin 4
60 configure wave -childrowmargin 2
61 configure wave -gridoffset 0
62 configure wave -gridperiod 1
63 configure wave -griddelta 40
64 configure wave -timeline 0
65 configure wave -timelineunits ps
66 update
67 WaveRestoreZoom {0 ps} {91678875750 ps}
68 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
69 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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