diff --git a/designs/Validation_LFR/TB.vhd b/designs/Validation_LFR/TB.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR/TB.vhd @@ -0,0 +1,567 @@ +------------------------------------------------------------------------------ +-- This file is a part of the LPP VHDL IP LIBRARY +-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 3 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +------------------------------------------------------------------------------- +-- Author : Jean-christophe Pellion +-- Mail : jean-christophe.pellion@lpp.polytechnique.fr +------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.NUMERIC_STD.ALL; + +LIBRARY lpp; +USE lpp.lpp_ad_conv.ALL; +USE lpp.iir_filter.ALL; +USE lpp.FILTERcfg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.lpp_waveform_pkg.ALL; +USE lpp.lpp_dma_pkg.ALL; +USE lpp.lpp_top_lfr_pkg.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.general_purpose.ALL; +USE lpp.lpp_lfr_pkg.ALL; +USE lpp.lpp_memory.ALL; +USE lpp.iir_filter.ALL; +USE lpp.spectral_matrix_package.ALL; +USE lpp.lpp_fft.ALL; +USE lpp.fft_components.ALL; +USE lpp.CY7C1061DV33_pkg.ALL; +USE lpp.testbench_package.ALL; + + +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +USE grlib.devices.ALL; +USE GRLIB.DMA2AHB_Package.ALL; + +LIBRARY gaisler; +USE gaisler.memctrl.ALL; +USE gaisler.misc.ALL; + +LIBRARY techmap; +USE techmap.gencomp.ALL; + +LIBRARY esa; +USE esa.memoryctrl.ALL; + + +ENTITY TB IS +END TB; + + +ARCHITECTURE beh OF TB IS + CONSTANT INDEX_LFR : INTEGER := 15; + CONSTANT ADDR_LFR : INTEGER := 15; + -- REG MS + CONSTANT ADDR_SPECTRAL_MATRIX_CONFIG : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F00"; + CONSTANT ADDR_SPECTRAL_MATRIX_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F04"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F08"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F0C"; + + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F10"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F14"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F18"; + CONSTANT ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F1C"; + + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F20"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F24"; + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F28"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F2C"; + + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F30"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F34"; + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F38"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F3C"; + + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F40"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F44"; + CONSTANT ADDR_SPECTRAL_MATRIX_COARSE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F48"; + CONSTANT ADDR_SPECTRAL_MATRIX_FINE_TIME_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F4C"; + + -- REG WAVEFORM + CONSTANT ADDR_WAVEFORM_PICKER_DATASHAPING : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F50"; + CONSTANT ADDR_WAVEFORM_PICKER_CONTROL : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F54"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F58"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F5C"; + + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F60"; + CONSTANT ADDR_WAVEFORM_PICKER_ADDRESS_F3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F64"; + CONSTANT ADDR_WAVEFORM_PICKER_STATUS : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F68"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTASNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F6C"; + + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F70"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F0_2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F74"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F78"; + CONSTANT ADDR_WAVEFORM_PICKER_DELTA_F2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F7C"; + + CONSTANT ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F80"; + CONSTANT ADDR_WAVEFORM_PICKER_NBSNAPSHOT : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F84"; + CONSTANT ADDR_WAVEFORM_PICKER_START_DATE : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F88"; + CONSTANT ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"00000F8C"; + -- RAM ADDRESS + CONSTANT AHB_RAM_ADDR_0 : INTEGER := 16#000#; + CONSTANT AHB_RAM_ADDR_1 : INTEGER := 16#200#; + CONSTANT AHB_RAM_ADDR_2 : INTEGER := 16#300#; + CONSTANT AHB_RAM_ADDR_3 : INTEGER := 16#400#; + + + -- Common signal + SIGNAL clk49_152MHz : STD_LOGIC := '0'; + SIGNAL clk25MHz : STD_LOGIC := '0'; + SIGNAL rstn : STD_LOGIC := '0'; + + -- ADC interface + SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); -- OUT + SIGNAL ADC_smpclk : STD_LOGIC; -- OUT + SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); -- IN + + -- AD Converter RHF1401 + SIGNAL sample : Samples14v(7 DOWNTO 0); + SIGNAL sample_s : Samples(7 DOWNTO 0); + SIGNAL sample_val : STD_LOGIC; + + -- AHB/APB SIGNAL + SIGNAL apbi : apb_slv_in_type; + SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); + SIGNAL ahbsi : ahb_slv_in_type; + SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); + SIGNAL ahbmi : ahb_mst_in_type; + SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); + + SIGNAL bias_fail_bw : STD_LOGIC; + + ----------------------------------------------------------------------------- + -- LPP_WAVEFORM + ----------------------------------------------------------------------------- + CONSTANT data_size : INTEGER := 96; + CONSTANT nb_burst_available_size : INTEGER := 50; + CONSTANT nb_snapshot_param_size : INTEGER := 2; + CONSTANT delta_vector_size : INTEGER := 2; + CONSTANT delta_vector_size_f0_2 : INTEGER := 2; + + SIGNAL reg_run : STD_LOGIC; + SIGNAL reg_start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); + SIGNAL reg_delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); + SIGNAL reg_delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL reg_delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); + SIGNAL enable_f0 : STD_LOGIC; + SIGNAL enable_f1 : STD_LOGIC; + SIGNAL enable_f2 : STD_LOGIC; + SIGNAL enable_f3 : STD_LOGIC; + SIGNAL burst_f0 : STD_LOGIC; + SIGNAL burst_f1 : STD_LOGIC; + SIGNAL burst_f2 : STD_LOGIC; + SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0); + SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); + SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); + SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_in_valid : STD_LOGIC; + SIGNAL data_f0_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_in_valid : STD_LOGIC; + SIGNAL data_f1_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_in_valid : STD_LOGIC; + SIGNAL data_f2_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_in_valid : STD_LOGIC; + SIGNAL data_f3_in : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0); + SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f0_data_out_valid : STD_LOGIC; + SIGNAL data_f0_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f0_data_out_ack : STD_LOGIC; + SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f1_data_out_valid : STD_LOGIC; + SIGNAL data_f1_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f1_data_out_ack : STD_LOGIC; + SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f2_data_out_valid : STD_LOGIC; + SIGNAL data_f2_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f2_data_out_ack : STD_LOGIC; + SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_f3_data_out_valid : STD_LOGIC; + SIGNAL data_f3_data_out_valid_burst : STD_LOGIC; + SIGNAL data_f3_data_out_ack : STD_LOGIC; + + --MEM CTRLR + SIGNAL memi : memory_in_type; + SIGNAL memo : memory_out_type; + SIGNAL wpo : wprot_out_type; + SIGNAL sdo : sdram_out_type; + + SIGNAL address : STD_LOGIC_VECTOR(19 DOWNTO 0) := "00000000000000000000"; + SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL nSRAM_BE0 : STD_LOGIC; + SIGNAL nSRAM_BE1 : STD_LOGIC; + SIGNAL nSRAM_BE2 : STD_LOGIC; + SIGNAL nSRAM_BE3 : STD_LOGIC; + SIGNAL nSRAM_WE : STD_LOGIC; + SIGNAL nSRAM_CE : STD_LOGIC; + SIGNAL nSRAM_OE : STD_LOGIC; + + CONSTANT padtech : INTEGER := inferred; + SIGNAL not_ramsn_0 : STD_LOGIC; + + ----------------------------------------------------------------------------- + SIGNAL status : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL read_buffer : STD_LOGIC; + ----------------------------------------------------------------------------- + SIGNAL run_test_waveform_picker : STD_LOGIC := '1'; + SIGNAL state_read_buffer_on_going : STD_LOGIC; + CONSTANT hindex : INTEGER := 1; + SIGNAL time_mem_f0 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f1 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f2 : STD_LOGIC_VECTOR(63 DOWNTO 0); + SIGNAL time_mem_f3 : STD_LOGIC_VECTOR(63 DOWNTO 0); + + SIGNAL data_mem_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL data_mem_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0); + + SIGNAL data_0_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_0_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_0_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_1_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_1_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_1_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_2_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_2_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_2_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_3_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_3_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_3_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_4_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_4_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_4_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + + SIGNAL data_5_f1 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_5_f2 : STD_LOGIC_VECTOR(15 DOWNTO 0); + SIGNAL data_5_f0 : STD_LOGIC_VECTOR(15 DOWNTO 0); + ----------------------------------------------------------------------------- + + SIGNAL current_data : INTEGER; + SIGNAL LIMIT_DATA : INTEGER := 64; + + SIGNAL read_buffer_temp : STD_LOGIC; + SIGNAL read_buffer_temp_2 : STD_LOGIC; + + +BEGIN + + ----------------------------------------------------------------------------- + + clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz + clk25MHz <= NOT clk25MHz AFTER 5 ns; -- 100 MHz + + ----------------------------------------------------------------------------- + + MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE + TestModule_RHF1401_1 : TestModule_RHF1401 + GENERIC MAP ( + freq => 24*(I+1), + amplitude => 8000/(I+1), + impulsion => 0) + PORT MAP ( + ADC_smpclk => ADC_smpclk, + ADC_OEB_bar => ADC_OEB_bar_CH(I), + ADC_data => ADC_data); + END GENERATE MODULE_RHF1401; + + ----------------------------------------------------------------------------- + + top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401 + GENERIC MAP ( + ChanelCount => 8, + ncycle_cnv_high => 79, + ncycle_cnv => 500) + PORT MAP ( + cnv_clk => clk49_152MHz, + cnv_rstn => rstn, + cnv => ADC_smpclk, + clk => clk25MHz, + rstn => rstn, + ADC_data => ADC_data, + ADC_nOE => ADC_OEB_bar_CH, + sample => sample, + sample_val => sample_val); + ----------------------------------------------------------------------------- + + + all_sample : FOR I IN 7 DOWNTO 0 GENERATE + sample_s(I) <= sample(I) & '0' & '0'; + END GENERATE all_sample; + ----------------------------------------------------------------------------- + + lpp_lfr_1 : lpp_lfr + GENERIC MAP ( + Mem_use => use_CEL, -- use_RAM + nb_data_by_buffer_size => 32, + nb_word_by_buffer_size => 30, + nb_snapshot_param_size => 32, + delta_vector_size => 32, + delta_vector_size_f0_2 => 32, + pindex => INDEX_LFR, + paddr => ADDR_LFR, + pmask => 16#fff#, + pirq_ms => 6, + pirq_wfp => 14, + hindex => 0, + top_lfr_version => X"000001") + PORT MAP ( + clk => clk25MHz, + rstn => rstn, + sample_B => sample_s(2 DOWNTO 0), + sample_E => sample_s(7 DOWNTO 3), + sample_val => sample_val, + apbi => apbi, + apbo => apbo(15), + ahbi => ahbmi, + ahbo => ahbmo(0), + coarse_time => coarse_time, + fine_time => fine_time, + data_shaping_BW => bias_fail_bw); + + ----------------------------------------------------------------------------- + --- AHB CONTROLLER ------------------------------------------------- + ahb0 : ahbctrl -- AHB arbiter/multiplexer + GENERIC MAP (defmast => 0, split => 0, + rrobin => 1, ioaddr => 16#FFF#, + ioen => 0, nahbm => 2, nahbs => 1) + PORT MAP (rstn, clk25MHz, ahbmi, ahbmo, ahbsi, ahbso); + + + + --- AHB RAM ---------------------------------------------------------- + --ahbram0 : ahbram + -- GENERIC MAP (hindex => 0, haddr => AHB_RAM_ADDR_0, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(0)); + --ahbram1 : ahbram + -- GENERIC MAP (hindex => 1, haddr => AHB_RAM_ADDR_1, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(1)); + --ahbram2 : ahbram + -- GENERIC MAP (hindex => 2, haddr => AHB_RAM_ADDR_2, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(2)); + --ahbram3 : ahbram + -- GENERIC MAP (hindex => 3, haddr => AHB_RAM_ADDR_3, tech => inferred, kbytes => 1, pipe => 0) + -- PORT MAP (rstn, clk25MHz, ahbsi, ahbso(3)); + + ----------------------------------------------------------------------------- + ---------------------------------------------------------------------- + --- Memory controllers --------------------------------------------- + ---------------------------------------------------------------------- + memctrlr : mctrl GENERIC MAP ( + hindex => 0, + pindex => 0, + paddr => 0, + srbanks => 1 + ) + PORT MAP (rstn, clk25MHz, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); + + memi.brdyn <= '1'; + memi.bexcn <= '1'; + memi.writen <= '1'; + memi.wrn <= "1111"; + memi.bwidth <= "10"; + + bdr : FOR i IN 0 TO 3 GENERATE + data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) + PORT MAP ( + data(31-i*8 DOWNTO 24-i*8), + memo.data(31-i*8 DOWNTO 24-i*8), + memo.bdrive(i), + memi.data(31-i*8 DOWNTO 24-i*8)); + END GENERATE; + + addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) + PORT MAP (address, memo.address(21 DOWNTO 2)); + + not_ramsn_0 <= NOT(memo.ramsn(0)); + + rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, not_ramsn_0); + oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); + nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); + nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); + nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); + nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); + nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); + + async_1Mx16_0 : CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => true, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE1, + BLE_b => nSRAM_BE0, + A => address, + DQ => data(15 DOWNTO 0)); + + async_1Mx16_1 : CY7C1061DV33 + GENERIC MAP ( + ADDR_BITS => 20, + DATA_BITS => 16, + depth => 1048576, + MEM_ARRAY_DEBUG => 32, + TimingInfo => true, + TimingChecks => '1') + PORT MAP ( + CE1_b => '0', + CE2 => nSRAM_CE, + WE_b => nSRAM_WE, + OE_b => nSRAM_OE, + BHE_b => nSRAM_BE3, + BLE_b => nSRAM_BE2, + A => address, + DQ => data(31 DOWNTO 16)); + + + ----------------------------------------------------------------------------- + + WaveGen_Proc : PROCESS + BEGIN + + -- insert signal assignments here + WAIT UNTIL clk25MHz = '1'; + rstn <= '0'; + apbi.psel(15) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + fine_time <= (OTHERS => '0'); + coarse_time <= (OTHERS => '0'); + WAIT UNTIL clk25MHz = '1'; +-- ahbmi.HGRANT(2) <= '1'; +-- ahbmi.HREADY <= '1'; +-- ahbmi.HRESP <= HRESP_OKAY; + + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + rstn <= '1'; + WAIT UNTIL clk25MHz = '1'; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_0 , X"40000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F0_1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F1_0 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_ADDR_MATRIX_F2_0 , X"40060000"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_CONFIG, X"00000007"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_SPECTRAL_MATRIX_STATUS, X"00000000"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000020"); --"00000020" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000019"); --"00000019" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007"); --"00000007" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000019"); --"00000019" + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001"); --"00000001" + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010" + -- + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000010"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"00000022"); + + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000080"); + WAIT UNTIL clk25MHz = '1'; + --------------------------------------------------------------------------- + -- CONFIGURATION STEP + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F0 , X"40000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F1 , X"40020000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000"); + + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + + + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000097"); + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + WAIT FOR 1 us; + coarse_time <= X"00000001"; + --------------------------------------------------------------------------- + -- RUN STEP + WAIT FOR 200 ms; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_START_DATE, X"00000010"); + WAIT FOR 10 us; + WAIT UNTIL clk25MHz = '1'; + WAIT UNTIL clk25MHz = '1'; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000FF"); + WAIT UNTIL clk25MHz = '1'; + coarse_time <= X"00000010"; + WAIT FOR 100 ms; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"00000000"); + WAIT FOR 10 us; + APB_WRITE(clk25MHz, INDEX_LFR, apbi, ADDR_WAVEFORM_PICKER_CONTROL, X"000000AF"); + WAIT FOR 200 ms; + REPORT "*** END simulation ***" SEVERITY failure; + + + WAIT; + + END PROCESS WaveGen_Proc; + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- IRQ + ----------------------------------------------------------------------------- + PROCESS (clk25MHz, rstn) + BEGIN -- PROCESS + IF rstn = '0' THEN -- asynchronous reset (active low) + + ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge + + END IF; + END PROCESS; + ----------------------------------------------------------------------------- + +END beh; + diff --git a/designs/Validation_LFR/run.do b/designs/Validation_LFR/run.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR/run.do @@ -0,0 +1,3 @@ +log -R * +do wave.do +run -all \ No newline at end of file diff --git a/designs/Validation_LFR/testbench_package.vhd b/designs/Validation_LFR/testbench_package.vhd new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR/testbench_package.vhd @@ -0,0 +1,136 @@ + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +LIBRARY grlib; +USE grlib.amba.ALL; +USE grlib.stdlib.ALL; +--LIBRARY gaisler; +--USE gaisler.libdcom.ALL; +--USE gaisler.sim.ALL; +--USE gaisler.jtagtst.ALL; +--LIBRARY techmap; +--USE techmap.gencomp.ALL; + + +PACKAGE testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ); + +END testbench_package; + +PACKAGE BODY testbench_package IS + + PROCEDURE APB_WRITE ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '1'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + apbi.pwdata <= pwdata; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + apbi.pwdata <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + + END APB_WRITE; + + PROCEDURE APB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT pindex : IN INTEGER; + SIGNAL apbi : OUT apb_slv_in_type; + SIGNAL apbo : IN apb_slv_out_type; + CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + apbi.psel(pindex) <= '1'; + apbi.pwrite <= '0'; + apbi.penable <= '1'; + apbi.paddr <= paddr; + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + apbi.psel(pindex) <= '0'; + apbi.pwrite <= '0'; + apbi.penable <= '0'; + apbi.paddr <= (OTHERS => '0'); + WAIT UNTIL clk = '0'; + WAIT UNTIL clk = '1'; + prdata <= apbo.prdata; + END APB_READ; + + PROCEDURE AHB_READ ( + SIGNAL clk : IN STD_LOGIC; + CONSTANT hindex : IN INTEGER; + SIGNAL ahbmi : IN ahb_mst_in_type; + SIGNAL ahbmo : OUT ahb_mst_out_type; + CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) + ) IS + BEGIN + WAIT UNTIL clk = '1'; + ahbmo.HADDR <= haddr; + ahbmo.HPROT <= "0011"; + ahbmo.HIRQ <= (OTHERS => '0'); + ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0')); + ahbmo.HINDEX <= hindex; + ahbmo.HBUSREQ <= '1'; + ahbmo.HLOCK <= '1'; + ahbmo.HSIZE <= HSIZE_WORD; + ahbmo.HBURST <= HBURST_SINGLE; + ahbmo.HTRANS <= HTRANS_NONSEQ; + ahbmo.HWRITE <= '0'; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HBUSREQ <= '0'; + ahbmo.HLOCK <= '0'; + ahbmo.HTRANS <= HTRANS_IDLE; + WHILE ahbmi.HREADY = '0' LOOP + WAIT UNTIL clk = '1'; + END LOOP; + WAIT UNTIL clk = '1'; + hrdata <= ahbmi.HRDATA; + --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1'; + ahbmo.HLOCK <= '0'; + WAIT UNTIL clk = '1'; + + END AHB_READ; + +END testbench_package; diff --git a/designs/Validation_LFR/wave.do b/designs/Validation_LFR/wave.do new file mode 100644 --- /dev/null +++ b/designs/Validation_LFR/wave.do @@ -0,0 +1,69 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val +add wave -noupdate -expand -group FILTER_OUTPUT /tb/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/enable +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/burst_enable +add wave -noupdate -expand -group SNAPSHOT_F0 /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_f0/start_snapshot +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/state_on +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on_s +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0_pre +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_decount +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/first_init +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_snapshot +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/counter_delta_f0 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/send_start_snapshot_f0 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f0_valid +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/data_f2_valid +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f0 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f1 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/start_snapshot_f2 +add wave -noupdate /tb/lpp_lfr_1/lpp_waveform_1/lpp_waveform_snapshot_controler_1/wfp_on +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_in +add wave -noupdate -expand -subitemconfig {/tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.haddr {-height 15 -radix hexadecimal} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out.hwdata {-height 15 -radix hexadecimal}} /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ahb_master_out +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/send +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/valid_burst +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/done +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/ren +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/address +add wave -noupdate -radix hexadecimal /tb/lpp_lfr_1/lpp_dma_singleorburst_1/data +add wave -noupdate /tb/lpp_lfr_1/lpp_dma_singleorburst_1/debug_dmaout_okay +add wave -noupdate /tb/async_1mx16_0/ce1_b +add wave -noupdate /tb/async_1mx16_0/ce2 +add wave -noupdate /tb/async_1mx16_0/we_b +add wave -noupdate /tb/async_1mx16_0/oe_b +add wave -noupdate /tb/async_1mx16_0/bhe_b +add wave -noupdate /tb/async_1mx16_0/ble_b +add wave -noupdate /tb/async_1mx16_0/a +add wave -noupdate /tb/async_1mx16_0/dq +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_0(31) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(30) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(29) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(28) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(27) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(26) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(25) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(24) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(23) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(22) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(21) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(20) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(19) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(18) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(17) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(16) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(15) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(14) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(13) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(12) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(11) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(10) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(9) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(8) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(7) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(6) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(5) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(4) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(3) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(2) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(1) {-height 15 -radix hexadecimal} /tb/async_1mx16_0/mem_array_0(0) {-height 15 -radix hexadecimal}} /tb/async_1mx16_0/mem_array_0 +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/async_1mx16_0/mem_array_1(31) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(30) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(29) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(28) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(27) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(26) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(25) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(24) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(23) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(22) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(21) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(20) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(19) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(18) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(17) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(16) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(15) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(14) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(13) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(12) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(11) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(10) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(9) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(8) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(7) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(6) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(5) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(4) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(3) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(2) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(1) {-radix hexadecimal} /tb/async_1mx16_0/mem_array_1(0) {-radix hexadecimal}} /tb/async_1mx16_0/mem_array_1 +add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_2 +add wave -noupdate -radix hexadecimal /tb/async_1mx16_0/mem_array_3 +add wave -noupdate -format Analog-Step -height 70 -max 256.0 -radix unsigned -subitemconfig {/tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(7) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(6) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(5) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(4) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(3) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(2) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(1) {-radix unsigned} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect(0) {-radix unsigned}} /tb/lpp_lfr_1/lpp_lfr_ms_1/lppfifoxn_f0_b/fifos(0)/lpp_fifo_1/waddr_vect +add wave -noupdate -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(0) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(1) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(2) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(3) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(4) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(5) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(6) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(7) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(8) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(9) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(10) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(11) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(12) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(13) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(14) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(15) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(16) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(17) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(18) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(19) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(20) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(21) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(22) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(23) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(24) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(25) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(26) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(27) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(28) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(29) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(30) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(31) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(32) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(33) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(34) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(35) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(36) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(37) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(38) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(39) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(40) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(41) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(42) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(43) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(44) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(45) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(46) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(47) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(48) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(49) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(50) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(51) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(52) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(53) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(54) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(55) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(56) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(57) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(58) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(59) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(60) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(61) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(62) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(63) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(64) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(65) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(66) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(67) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(68) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(69) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(70) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(71) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(72) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(73) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(74) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(75) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(76) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(77) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(78) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(79) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(80) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(81) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(82) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(83) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(84) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(85) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(86) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(87) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(88) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(89) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(90) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(91) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(92) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(93) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(94) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(95) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(96) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(97) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(98) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(99) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(100) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(101) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(102) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(103) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(104) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(105) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(106) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(107) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(108) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(109) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(110) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(111) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(112) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(113) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(114) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(115) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(116) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(117) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(118) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(119) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(120) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(121) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(122) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(123) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(124) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(125) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(126) {-radix hexadecimal} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd(127) {-radix hexadecimal}} /tb/lpp_lfr_1/lpp_waveform_1/lpp_fifo_4_shared_1/sram/inf/x0/rfd +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {44999193701 ps} 0} {{Cursor 3} {209437155 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {27526990683 ps} 0} +configure wave -namecolwidth 618 +configure wave -valuecolwidth 472 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {91678875750 ps} +bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0 +bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0