##// END OF EJS Templates
EQm-debug
pellion -
r565:c4b93187bfff JC
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@@ -45,6 +45,9 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 library proasic3e;
49 use proasic3e.clkint;
50
48 51 ENTITY LFR_EQM IS
49 52
50 53 PORT (
@@ -156,6 +159,10 ARCHITECTURE beh OF LFR_EQM IS
156 159
157 160 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
158 161
162 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163
164 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
165
159 166 BEGIN -- beh
160 167
161 168 -----------------------------------------------------------------------------
@@ -164,9 +171,11 BEGIN -- beh
164 171 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
165 172 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
166 173
167 PROCESS(clk50MHz)
174 clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
175
176 PROCESS(clk50MHz_int)
168 177 BEGIN
169 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
178 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
170 179 clk_25 <= NOT clk_25;
171 180 END IF;
172 181 END PROCESS;
@@ -285,9 +294,9 BEGIN -- beh
285 294 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
286 295 ------------------------------------------------------------------------------
287 296
288 spw_clk <= clk50MHz;
289 spw_rxtxclk <= spw_clk;
290 spw_rxclkn <= NOT spw_rxtxclk;
297 --spw_clk <= clk50MHz;
298 --spw_rxtxclk <= spw_clk;
299 --spw_rxclkn <= NOT spw_rxtxclk;
291 300
292 301 -- PADS for SPW1
293 302 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
@@ -353,7 +362,10 BEGIN -- beh
353 362 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
354 363 )
355 364 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
356 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
365 spw_rxclk(1),
366 clk50MHz_int,
367 clk50MHz_int,
368 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
357 369 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
358 370 swni, swno);
359 371
@@ -388,7 +400,7 BEGIN -- beh
388 400 -- AA : BOARD NUMBER
389 401 -- 0 => MINI_LFR
390 402 -- 1 => EM
391 -- 1 => EQM (with A3PE3000)
403 -- 2 => EQM (with A3PE3000)
392 404 PORT MAP (
393 405 clk => clk_25,
394 406 rstn => LFR_rstn,
@@ -439,7 +451,7 BEGIN -- beh
439 451 ADC_smpclk <= ADC_smpclk_s;
440 452 HK_smpclk <= ADC_smpclk_s;
441 453
442 TAG8 <= ADC_smpclk_s;
454 TAG8 <='0';
443 455
444 456 -----------------------------------------------------------------------------
445 457 -- HK
@@ -17,7 +17,8 VHDLSYNFILES=LFR-EQM.vhd
17 17 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21 22
22 23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 24 CLEAN=soft-clean
@@ -32,6 +32,7 ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 36 SIGNAL cnv_sync : STD_LOGIC;
36 37 SIGNAL cnv_sync_pre : STD_LOGIC;
37 38
@@ -80,6 +81,15 BEGIN
80 81
81 82 cnv <= cnv_s;
82 83
84 PROCESS (cnv_clk, cnv_rstn)
85 BEGIN -- PROCESS
86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 cnv_s_reg <= '0';
88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 cnv_s_reg <= cnv_s;
90 END IF;
91 END PROCESS;
92
83 93
84 94 -----------------------------------------------------------------------------
85 95 -- SYNC CNV
@@ -91,7 +101,7 BEGIN
91 101 PORT MAP (
92 102 clk => clk,
93 103 rstn => rstn,
94 A => cnv_s,
104 A => cnv_s_reg,
95 105 A_sync => cnv_sync);
96 106
97 107
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