# HG changeset patch
# User pellion
# Date 2015-03-25 08:49:49
# Node ID c4b93187bfff4812147c9a299ae16657408d358a
# Parent  1a281572c0f320fb8b05b30777f15c0cad54bad5

EQm-debug

diff --git a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd
--- a/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd
+++ b/designs/LFR-EQM-WFP_MS/LFR-EQM.vhd
@@ -45,6 +45,9 @@ USE lpp.general_purpose.ALL;
 USE lpp.lpp_lfr_management.ALL;
 USE lpp.lpp_leon3_soc_pkg.ALL;
 
+library proasic3e;
+use proasic3e.clkint;
+
 ENTITY LFR_EQM IS
   
   PORT (
@@ -156,6 +159,10 @@ ARCHITECTURE beh OF LFR_EQM IS
 
   SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
   
+  SIGNAL clk50MHz_int : STD_LOGIC := '0';
+
+  component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
+  
 BEGIN  -- beh
 
   -----------------------------------------------------------------------------
@@ -164,9 +171,11 @@ BEGIN  -- beh
   rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
   rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
 
-  PROCESS(clk50MHz)
+  clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int ); 
+
+  PROCESS(clk50MHz_int)
   BEGIN
-    IF clk50MHz'EVENT AND clk50MHz = '1' THEN
+    IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
       clk_25 <= NOT clk_25;
     END IF;
   END PROCESS;
@@ -285,9 +294,9 @@ BEGIN  -- beh
   -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
   ------------------------------------------------------------------------------
   
-  spw_clk     <= clk50MHz;
-  spw_rxtxclk <= spw_clk;
-  spw_rxclkn  <= NOT spw_rxtxclk;
+  --spw_clk     <= clk50MHz;
+  --spw_rxtxclk <= spw_clk;
+  --spw_rxclkn  <= NOT spw_rxtxclk;
 
   -- PADS for SPW1
   spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
@@ -353,7 +362,10 @@ BEGIN  -- beh
     --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
     )
     PORT MAP(rstn_25, clk_25, spw_rxclk(0),
-             spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
+             spw_rxclk(1),
+             clk50MHz_int,
+             clk50MHz_int,
+--             spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
              ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
              swni, swno);
 
@@ -388,7 +400,7 @@ BEGIN  -- beh
                                             -- AA : BOARD NUMBER
                                             --      0 => MINI_LFR
                                             --      1 => EM
-                                            --      1 => EQM (with A3PE3000)
+                                            --      2 => EQM (with A3PE3000)
     PORT MAP (
       clk             => clk_25,
       rstn            => LFR_rstn,
@@ -439,7 +451,7 @@ BEGIN  -- beh
   ADC_smpclk <= ADC_smpclk_s;
   HK_smpclk  <= ADC_smpclk_s;
 
-  TAG8 <= ADC_smpclk_s;
+  TAG8 <='0';
 
   -----------------------------------------------------------------------------
   -- HK
diff --git a/designs/LFR-EQM-WFP_MS/Makefile b/designs/LFR-EQM-WFP_MS/Makefile
--- a/designs/LFR-EQM-WFP_MS/Makefile
+++ b/designs/LFR-EQM-WFP_MS/Makefile
@@ -17,7 +17,8 @@ VHDLSYNFILES=LFR-EQM.vhd
 VHDLSIMFILES=testbench.vhd
 #SIMTOP=testbench
 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
-SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
+SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
+SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
 
 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
 CLEAN=soft-clean
diff --git a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
--- a/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
+++ b/lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
@@ -32,8 +32,9 @@ ARCHITECTURE ar_top_ad_conv_RHF1401 OF t
   
   SIGNAL cnv_cycle_counter : INTEGER;
   SIGNAL cnv_s             : STD_LOGIC;
+  SIGNAL cnv_s_reg         : STD_LOGIC;
   SIGNAL cnv_sync          : STD_LOGIC;
-  SIGNAL cnv_sync_pre          : STD_LOGIC;
+  SIGNAL cnv_sync_pre      : STD_LOGIC;
 
   SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
   SIGNAL enable_ADC : STD_LOGIC;
@@ -79,6 +80,15 @@ BEGIN
   END PROCESS;
 
   cnv <= cnv_s;
+  
+  PROCESS (cnv_clk, cnv_rstn)
+  BEGIN  -- PROCESS
+    IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+      cnv_s_reg             <= '0';
+    ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+      cnv_s_reg             <= cnv_s;
+    END IF;
+  END PROCESS;
 
 
   -----------------------------------------------------------------------------
@@ -91,7 +101,7 @@ BEGIN
     PORT MAP (
       clk    => clk,
       rstn   => rstn,
-      A      => cnv_s,
+      A      => cnv_s_reg,
       A_sync => cnv_sync);