HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib Commit - r565:c4b93187bfff

EQm-debug

pellion -

r565:c4b93187bfff JC

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r565:c4b93187bfff

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designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +20 -8

             USE lpp.lpp_lfr_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
+            library proasic3e;
+            use proasic3e.clkint;
             ENTITY LFR_EQM IS
               PORT (
               SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
+              SIGNAL clk50MHz_int : STD_LOGIC := '0';
+              component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
               rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
-              PROCESS(clk50MHz)
+              clk_pad : clkint  port map (A => clk50MHz, Y => clk50MHz_int );
+              PROCESS(clk50MHz_int)
               BEGIN
-                IF clk50MHz'EVENT AND clk50MHz = '1' THEN
+                IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
               ------------------------------------------------------------------------------
-              spw_clk     <= clk50MHz;
+              --spw_clk     <= clk50MHz;
-              spw_rxtxclk <= spw_clk;
+              --spw_rxtxclk <= spw_clk;
-              spw_rxclkn  <= NOT spw_rxtxclk;
+              --spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
-                         spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
+                         spw_rxclk(1),
+                         clk50MHz_int,
+                         clk50MHz_int,
+            --             spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
-                                                        --      1 => EQM (with A3PE3000)
+                                                        --      2 => EQM (with A3PE3000)
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
               ADC_smpclk <= ADC_smpclk_s;
               HK_smpclk  <= ADC_smpclk_s;
-              TAG8 <= ADC_smpclk_s;
+              TAG8 <='0';
               -----------------------------------------------------------------------------
               -- HK

designs/LFR-EQM-WFP_MS/Makefile +2 -1

             VHDLSIMFILES=testbench.vhd
             #SIMTOP=testbench
             PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
-            SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
+            SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
+            SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
             CLEAN=soft-clean

lib/lpp/lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd +12 -2

               SIGNAL cnv_cycle_counter : INTEGER;
               SIGNAL cnv_s             : STD_LOGIC;
+              SIGNAL cnv_s_reg         : STD_LOGIC;
               SIGNAL cnv_sync          : STD_LOGIC;
-              SIGNAL cnv_sync_pre          : STD_LOGIC;
+              SIGNAL cnv_sync_pre      : STD_LOGIC;
               SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
               SIGNAL enable_ADC : STD_LOGIC;
               END PROCESS;
               cnv <= cnv_s;
+              PROCESS (cnv_clk, cnv_rstn)
+              BEGIN  -- PROCESS
+                IF cnv_rstn = '0' THEN              -- asynchronous reset (active low)
+                  cnv_s_reg             <= '0';
+                ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN  -- rising clock edge
+                  cnv_s_reg             <= cnv_s;
+                END IF;
+              END PROCESS;
               -----------------------------------------------------------------------------
                 PORT MAP (
                   clk    => clk,
                   rstn   => rstn,
-                  A      => cnv_s,
+                  A      => cnv_s_reg,
                   A_sync => cnv_sync);

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