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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 library proasic3e;
49 use proasic3e.clkint;
50
48 51 ENTITY LFR_EQM IS
49 52
50 53 PORT (
51 54 clk50MHz : IN STD_ULOGIC;
52 55 clk49_152MHz : IN STD_ULOGIC;
53 56 reset : IN STD_ULOGIC;
54 57
55 58 -- TAG --------------------------------------------------------------------
56 59 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 60 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 61 -- UART APB ---------------------------------------------------------------
59 62 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 63 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 64 -- RAM --------------------------------------------------------------------
62 65 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
63 66 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 67
65 68 nSRAM_MBE : INOUT STD_LOGIC; -- new
66 69 nSRAM_E1 : OUT STD_LOGIC; -- new
67 70 nSRAM_E2 : OUT STD_LOGIC; -- new
68 71 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
69 72 nSRAM_W : OUT STD_LOGIC; -- new
70 73 nSRAM_G : OUT STD_LOGIC; -- new
71 74 nSRAM_BUSY : IN STD_LOGIC; -- new
72 75 -- SPW --------------------------------------------------------------------
73 76 spw1_en : OUT STD_LOGIC; -- new
74 77 spw1_din : IN STD_LOGIC;
75 78 spw1_sin : IN STD_LOGIC;
76 79 spw1_dout : OUT STD_LOGIC;
77 80 spw1_sout : OUT STD_LOGIC;
78 81 spw2_en : OUT STD_LOGIC; -- new
79 82 spw2_din : IN STD_LOGIC;
80 83 spw2_sin : IN STD_LOGIC;
81 84 spw2_dout : OUT STD_LOGIC;
82 85 spw2_sout : OUT STD_LOGIC;
83 86 -- ADC --------------------------------------------------------------------
84 87 bias_fail_sw : OUT STD_LOGIC;
85 88 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
86 89 ADC_smpclk : OUT STD_LOGIC;
87 90 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
88 91 -- DAC --------------------------------------------------------------------
89 92 DAC_SDO : OUT STD_LOGIC;
90 93 DAC_SCK : OUT STD_LOGIC;
91 94 DAC_SYNC : OUT STD_LOGIC;
92 95 DAC_CAL_EN : OUT STD_LOGIC;
93 96 -- HK ---------------------------------------------------------------------
94 97 HK_smpclk : OUT STD_LOGIC;
95 98 ADC_OEB_bar_HK : OUT STD_LOGIC;
96 99 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
97 100 ---------------------------------------------------------------------------
98 101 TAG8 : OUT STD_LOGIC
99 102 );
100 103
101 104 END LFR_EQM;
102 105
103 106
104 107 ARCHITECTURE beh OF LFR_EQM IS
105 108
106 109 SIGNAL clk_25 : STD_LOGIC := '0';
107 110 SIGNAL clk_24 : STD_LOGIC := '0';
108 111 -----------------------------------------------------------------------------
109 112 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 113 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
111 114
112 115 -- CONSTANTS
113 116 CONSTANT CFG_PADTECH : INTEGER := inferred;
114 117 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
115 118 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
116 119 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
117 120
118 121 SIGNAL apbi_ext : apb_slv_in_type;
119 122 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
120 123 SIGNAL ahbi_s_ext : ahb_slv_in_type;
121 124 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
122 125 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
123 126 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
124 127
125 128 -- Spacewire signals
126 129 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 130 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 131 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 132 SIGNAL spw_rxtxclk : STD_ULOGIC;
130 133 SIGNAL spw_rxclkn : STD_ULOGIC;
131 134 SIGNAL spw_clk : STD_LOGIC;
132 135 SIGNAL swni : grspw_in_type;
133 136 SIGNAL swno : grspw_out_type;
134 137
135 138 --GPIO
136 139 SIGNAL gpioi : gpio_in_type;
137 140 SIGNAL gpioo : gpio_out_type;
138 141
139 142 -- AD Converter ADS7886
140 143 SIGNAL sample : Samples14v(8 DOWNTO 0);
141 144 SIGNAL sample_s : Samples(8 DOWNTO 0);
142 145 SIGNAL sample_val : STD_LOGIC;
143 146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
144 147
145 148 -----------------------------------------------------------------------------
146 149 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 150
148 151 -----------------------------------------------------------------------------
149 152 SIGNAL rstn_25 : STD_LOGIC;
150 153 SIGNAL rstn_24 : STD_LOGIC;
151 154
152 155 SIGNAL LFR_soft_rstn : STD_LOGIC;
153 156 SIGNAL LFR_rstn : STD_LOGIC;
154 157
155 158 SIGNAL ADC_smpclk_s : STD_LOGIC;
156 159
157 160 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
158 161
162 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163
164 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
165
159 166 BEGIN -- beh
160 167
161 168 -----------------------------------------------------------------------------
162 169 -- CLK
163 170 -----------------------------------------------------------------------------
164 171 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
165 172 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
166 173
167 PROCESS(clk50MHz)
174 clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
175
176 PROCESS(clk50MHz_int)
168 177 BEGIN
169 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
178 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
170 179 clk_25 <= NOT clk_25;
171 180 END IF;
172 181 END PROCESS;
173 182
174 183 PROCESS(clk49_152MHz)
175 184 BEGIN
176 185 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
177 186 clk_24 <= NOT clk_24;
178 187 END IF;
179 188 END PROCESS;
180 189
181 190 -----------------------------------------------------------------------------
182 191 --
183 192 leon3_soc_1 : leon3_soc
184 193 GENERIC MAP (
185 194 fabtech => apa3e,
186 195 memtech => apa3e,
187 196 padtech => inferred,
188 197 clktech => inferred,
189 198 disas => 0,
190 199 dbguart => 0,
191 200 pclow => 2,
192 201 clk_freq => 25000,
193 202 IS_RADHARD => 0,
194 203 NB_CPU => 1,
195 204 ENABLE_FPU => 1,
196 205 FPU_NETLIST => 0,
197 206 ENABLE_DSU => 1,
198 207 ENABLE_AHB_UART => 1,
199 208 ENABLE_APB_UART => 1,
200 209 ENABLE_IRQMP => 1,
201 210 ENABLE_GPT => 1,
202 211 NB_AHB_MASTER => NB_AHB_MASTER,
203 212 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 213 NB_APB_SLAVE => NB_APB_SLAVE,
205 214 ADDRESS_SIZE => 19,
206 215 USES_IAP_MEMCTRLR => 1)
207 216 PORT MAP (
208 217 clk => clk_25,
209 218 reset => rstn_25,
210 219 errorn => OPEN,
211 220
212 221 ahbrxd => TAG1,
213 222 ahbtxd => TAG3,
214 223 urxd1 => TAG2,
215 224 utxd1 => TAG4,
216 225
217 226 address => address,
218 227 data => data,
219 228 nSRAM_BE0 => OPEN,
220 229 nSRAM_BE1 => OPEN,
221 230 nSRAM_BE2 => OPEN,
222 231 nSRAM_BE3 => OPEN,
223 232 nSRAM_WE => nSRAM_W,
224 233 nSRAM_CE => nSRAM_CE,
225 234 nSRAM_OE => nSRAM_G,
226 235 nSRAM_READY => nSRAM_BUSY,
227 236 SRAM_MBE => nSRAM_MBE,
228 237
229 238 apbi_ext => apbi_ext,
230 239 apbo_ext => apbo_ext,
231 240 ahbi_s_ext => ahbi_s_ext,
232 241 ahbo_s_ext => ahbo_s_ext,
233 242 ahbi_m_ext => ahbi_m_ext,
234 243 ahbo_m_ext => ahbo_m_ext);
235 244
236 245
237 246 nSRAM_E1 <= nSRAM_CE(0);
238 247 nSRAM_E2 <= nSRAM_CE(1);
239 248
240 249 -------------------------------------------------------------------------------
241 250 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
242 251 -------------------------------------------------------------------------------
243 252 apb_lfr_management_1 : apb_lfr_management
244 253 GENERIC MAP (
245 254 tech => apa3e,
246 255 pindex => 6,
247 256 paddr => 6,
248 257 pmask => 16#fff#,
249 258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
250 259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
251 260 PORT MAP (
252 261 clk25MHz => clk_25,
253 262 resetn_25MHz => rstn_25, -- TODO
254 263 clk24_576MHz => clk_24, -- 49.152MHz/2
255 264 resetn_24_576MHz => rstn_24, -- TODO
256 265
257 266 grspw_tick => swno.tickout,
258 267 apbi => apbi_ext,
259 268 apbo => apbo_ext(6),
260 269
261 270 HK_sample => sample_s(8),
262 271 HK_val => sample_val,
263 272 HK_sel => HK_SEL,
264 273
265 274 DAC_SDO => DAC_SDO,
266 275 DAC_SCK => DAC_SCK,
267 276 DAC_SYNC => DAC_SYNC,
268 277 DAC_CAL_EN => DAC_CAL_EN,
269 278
270 279 coarse_time => coarse_time,
271 280 fine_time => fine_time,
272 281 LFR_soft_rstn => LFR_soft_rstn
273 282 );
274 283
275 284 -----------------------------------------------------------------------
276 285 --- SpaceWire --------------------------------------------------------
277 286 -----------------------------------------------------------------------
278 287
279 288 ------------------------------------------------------------------------------
280 289 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
281 290 ------------------------------------------------------------------------------
282 291 spw1_en <= '1';
283 292 spw2_en <= '1';
284 293 ------------------------------------------------------------------------------
285 294 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
286 295 ------------------------------------------------------------------------------
287 296
288 spw_clk <= clk50MHz;
289 spw_rxtxclk <= spw_clk;
290 spw_rxclkn <= NOT spw_rxtxclk;
297 --spw_clk <= clk50MHz;
298 --spw_rxtxclk <= spw_clk;
299 --spw_rxclkn <= NOT spw_rxtxclk;
291 300
292 301 -- PADS for SPW1
293 302 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
294 303 PORT MAP (spw1_din, dtmp(0));
295 304 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
296 305 PORT MAP (spw1_sin, stmp(0));
297 306 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
298 307 PORT MAP (spw1_dout, swno.d(0));
299 308 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
300 309 PORT MAP (spw1_sout, swno.s(0));
301 310 -- PADS FOR SPW2
302 311 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
303 312 PORT MAP (spw2_din, dtmp(1));
304 313 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
305 314 PORT MAP (spw2_sin, stmp(1));
306 315 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
307 316 PORT MAP (spw2_dout, swno.d(1));
308 317 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
309 318 PORT MAP (spw2_sout, swno.s(1));
310 319
311 320 -- GRSPW PHY
312 321 --spw1_input: if CFG_SPW_GRSPW = 1 generate
313 322 spw_inputloop : FOR j IN 0 TO 1 GENERATE
314 323 spw_phy0 : grspw_phy
315 324 GENERIC MAP(
316 325 tech => apa3e,
317 326 rxclkbuftype => 1,
318 327 scantest => 0)
319 328 PORT MAP(
320 329 rxrst => swno.rxrst,
321 330 di => dtmp(j),
322 331 si => stmp(j),
323 332 rxclko => spw_rxclk(j),
324 333 do => swni.d(j),
325 334 ndo => swni.nd(j*5+4 DOWNTO j*5),
326 335 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
327 336 END GENERATE spw_inputloop;
328 337
329 338 -- SPW core
330 339 sw0 : grspwm GENERIC MAP(
331 340 tech => apa3e,
332 341 hindex => 1,
333 342 pindex => 5,
334 343 paddr => 5,
335 344 pirq => 11,
336 345 sysfreq => 25000, -- CPU_FREQ
337 346 rmap => 1,
338 347 rmapcrc => 1,
339 348 fifosize1 => 16,
340 349 fifosize2 => 16,
341 350 rxclkbuftype => 1,
342 351 rxunaligned => 0,
343 352 rmapbufs => 4,
344 353 ft => 0,
345 354 netlist => 0,
346 355 ports => 2,
347 356 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
348 357 memtech => apa3e,
349 358 destkey => 2,
350 359 spwcore => 1
351 360 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
352 361 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
353 362 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
354 363 )
355 364 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
356 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
365 spw_rxclk(1),
366 clk50MHz_int,
367 clk50MHz_int,
368 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
357 369 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
358 370 swni, swno);
359 371
360 372 swni.tickin <= '0';
361 373 swni.rmapen <= '1';
362 374 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
363 375 swni.tickinraw <= '0';
364 376 swni.timein <= (OTHERS => '0');
365 377 swni.dcrstval <= (OTHERS => '0');
366 378 swni.timerrstval <= (OTHERS => '0');
367 379
368 380 -------------------------------------------------------------------------------
369 381 -- LFR ------------------------------------------------------------------------
370 382 -------------------------------------------------------------------------------
371 383 LFR_rstn <= LFR_soft_rstn AND rstn_25;
372 384
373 385 lpp_lfr_1 : lpp_lfr
374 386 GENERIC MAP (
375 387 Mem_use => use_RAM,
376 388 nb_data_by_buffer_size => 32,
377 389 --nb_word_by_buffer_size => 30,
378 390 nb_snapshot_param_size => 32,
379 391 delta_vector_size => 32,
380 392 delta_vector_size_f0_2 => 7, -- log2(96)
381 393 pindex => 15,
382 394 paddr => 15,
383 395 pmask => 16#fff#,
384 396 pirq_ms => 6,
385 397 pirq_wfp => 14,
386 398 hindex => 2,
387 399 top_lfr_version => X"020144") -- aa.bb.cc version
388 400 -- AA : BOARD NUMBER
389 401 -- 0 => MINI_LFR
390 402 -- 1 => EM
391 -- 1 => EQM (with A3PE3000)
403 -- 2 => EQM (with A3PE3000)
392 404 PORT MAP (
393 405 clk => clk_25,
394 406 rstn => LFR_rstn,
395 407 sample_B => sample_s(2 DOWNTO 0),
396 408 sample_E => sample_s(7 DOWNTO 3),
397 409 sample_val => sample_val,
398 410 apbi => apbi_ext,
399 411 apbo => apbo_ext(15),
400 412 ahbi => ahbi_m_ext,
401 413 ahbo => ahbo_m_ext(2),
402 414 coarse_time => coarse_time,
403 415 fine_time => fine_time,
404 416 data_shaping_BW => bias_fail_sw,
405 417 debug_vector => OPEN,
406 418 debug_vector_ms => OPEN); --,
407 419 --observation_vector_0 => OPEN,
408 420 --observation_vector_1 => OPEN,
409 421 --observation_reg => observation_reg);
410 422
411 423
412 424 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
413 425 sample_s(I) <= sample(I) & '0' & '0';
414 426 END GENERATE all_sample;
415 427 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
416 428
417 429 -----------------------------------------------------------------------------
418 430 --
419 431 -----------------------------------------------------------------------------
420 432 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
421 433 GENERIC MAP (
422 434 ChanelCount => 9,
423 435 ncycle_cnv_high => 13,
424 436 ncycle_cnv => 25,
425 437 FILTER_ENABLED => 16#FF#)
426 438 PORT MAP (
427 439 cnv_clk => clk_24,
428 440 cnv_rstn => rstn_24,
429 441 cnv => ADC_smpclk_s,
430 442 clk => clk_25,
431 443 rstn => rstn_25,
432 444 ADC_data => ADC_data,
433 445 ADC_nOE => ADC_OEB_bar_CH_s,
434 446 sample => sample,
435 447 sample_val => sample_val);
436 448
437 449 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
438 450
439 451 ADC_smpclk <= ADC_smpclk_s;
440 452 HK_smpclk <= ADC_smpclk_s;
441 453
442 TAG8 <= ADC_smpclk_s;
454 TAG8 <='0';
443 455
444 456 -----------------------------------------------------------------------------
445 457 -- HK
446 458 -----------------------------------------------------------------------------
447 459 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
448 460
449 461 END beh;
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@@ -1,54 +1,55
1 1 #GRLIB=../..
2 2 VHDLIB=../..
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=LFR_EQM
6 6 BOARD=LFR-EQM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 16 VHDLSYNFILES=LFR-EQM.vhd
17 17 VHDLSIMFILES=testbench.vhd
18 18 #SIMTOP=testbench
19 19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21 22
22 23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 24 CLEAN=soft-clean
24 25
25 26 TECHLIBS = proasic3e
26 27
27 28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 29 tmtc openchip hynix ihp gleichmann micron usbhc
29 30
30 31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 33 ./amba_lcd_16x2_ctrlr \
33 34 ./general_purpose/lpp_AMR \
34 35 ./general_purpose/lpp_balise \
35 36 ./general_purpose/lpp_delay \
36 37 ./lpp_bootloader \
37 38 ./dsp/lpp_fft_rtax \
38 39 ./lpp_uart \
39 40 ./lpp_usb \
40 41 ./lpp_sim/CY7C1061DV33 \
41 42
42 43 FILESKIP = i2cmst.vhd \
43 44 APB_MULTI_DIODE.vhd \
44 45 APB_MULTI_DIODE.vhd \
45 46 Top_MatrixSpec.vhd \
46 47 APB_FFT.vhd\
47 48 CoreFFT_simu.vhd \
48 49 lpp_lfr_apbreg_simu.vhd
49 50
50 51 include $(GRLIB)/bin/Makefile
51 52 include $(GRLIB)/software/leon3/Makefile
52 53
53 54 ################## project specific targets ##########################
54 55
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@@ -1,218 +1,228
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 12 ncycle_cnv_high : INTEGER := 13;
13 13 ncycle_cnv : INTEGER := 25;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync_pre : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
37 38
38 39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
39 40 SIGNAL enable_ADC : STD_LOGIC;
40 41
41 42
42 43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
43 44
44 45 SIGNAL channel_counter : INTEGER;
45 46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
46 47
47 48 SIGNAL ADC_data_selected : Samples14;
48 49 SIGNAL ADC_data_result : Samples15;
49 50
50 51 SIGNAL sample_counter : INTEGER;
51 52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52 53
53 54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
54 55
55 56 BEGIN
56 57
57 58
58 59 -----------------------------------------------------------------------------
59 60 -- CNV GEN
60 61 -----------------------------------------------------------------------------
61 62 PROCESS (cnv_clk, cnv_rstn)
62 63 BEGIN -- PROCESS
63 64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
64 65 cnv_cycle_counter <= 0;
65 66 cnv_s <= '0';
66 67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
67 68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
68 69 cnv_cycle_counter <= cnv_cycle_counter + 1;
69 70 IF cnv_cycle_counter < ncycle_cnv_high THEN
70 71 cnv_s <= '1';
71 72 ELSE
72 73 cnv_s <= '0';
73 74 END IF;
74 75 ELSE
75 76 cnv_s <= '1';
76 77 cnv_cycle_counter <= 0;
77 78 END IF;
78 79 END IF;
79 80 END PROCESS;
80 81
81 82 cnv <= cnv_s;
83
84 PROCESS (cnv_clk, cnv_rstn)
85 BEGIN -- PROCESS
86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 cnv_s_reg <= '0';
88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 cnv_s_reg <= cnv_s;
90 END IF;
91 END PROCESS;
82 92
83 93
84 94 -----------------------------------------------------------------------------
85 95 -- SYNC CNV
86 96 -----------------------------------------------------------------------------
87 97
88 98 SYNC_FF_cnv : SYNC_FF
89 99 GENERIC MAP (
90 100 NB_FF_OF_SYNC => 2)
91 101 PORT MAP (
92 102 clk => clk,
93 103 rstn => rstn,
94 A => cnv_s,
104 A => cnv_s_reg,
95 105 A_sync => cnv_sync);
96 106
97 107
98 108 -----------------------------------------------------------------------------
99 109 -- DATA GEN Output Enable
100 110 -----------------------------------------------------------------------------
101 111 PROCESS (clk, rstn)
102 112 BEGIN -- PROCESS
103 113 IF rstn = '0' THEN -- asynchronous reset (active low)
104 114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
105 115 cnv_sync_pre <= '0';
106 116 enable_ADC <= '0';
107 117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
108 118 cnv_sync_pre <= cnv_sync;
109 119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
110 120 enable_ADC <= '1';
111 121 ADC_nOE_reg(0) <= '0';
112 122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
113 123 ELSE
114 124 enable_ADC <= NOT enable_ADC;
115 125 IF enable_ADC = '0' THEN
116 126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
117 127 END IF;
118 128 END IF;
119 129
120 130 END IF;
121 131 END PROCESS;
122 132
123 133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
124 134
125 135 -----------------------------------------------------------------------------
126 136 -- ADC READ DATA
127 137 -----------------------------------------------------------------------------
128 138 PROCESS (clk, rstn)
129 139 BEGIN -- PROCESS
130 140 IF rstn = '0' THEN -- asynchronous reset (active low)
131 141 channel_counter <= MAX_COUNTER;
132 142
133 143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
134 144 sample_reg(I) <= (OTHERS => '0');
135 145 END LOOP all_sample_reg_init;
136 146
137 147 sample_val <= '0';
138 148 sample_counter <= 0;
139 149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
140 150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
141 151 channel_counter <= 0;
142 152 ELSE
143 153 IF channel_counter < MAX_COUNTER THEN
144 154 channel_counter <= channel_counter + 1;
145 155 END IF;
146 156 END IF;
147 157 sample_val <= '0';
148 158
149 159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
150 160 IF channel_counter = I*2 THEN
151 161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
152 162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
153 163 ELSE
154 164 sample_reg(I) <= ADC_data;
155 165 END IF;
156 166 END IF;
157 167 END LOOP all_sample_reg;
158 168
159 169 IF channel_counter = (ChanelCount-1)*2 THEN
160 170
161 171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
162 172 sample_counter <= 0 ;
163 173 sample_val <= '1';
164 174 ELSE
165 175 sample_counter <= sample_counter +1;
166 176 END IF;
167 177
168 178 END IF;
169 179 END IF;
170 180 END PROCESS;
171 181
172 182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
173 183 -- BEGIN -- PROCESS mux_adc
174 184 -- CASE channel_counter IS
175 185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
176 186 -- END CASE;
177 187 -- END PROCESS mux_adc;
178 188
179 189
180 190 -----------------------------------------------------------------------------
181 191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
182 192 -----------------------------------------------------------------------------
183 193
184 194 WITH channel_counter SELECT
185 195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
186 196 sample_reg(1) WHEN 1*2,
187 197 sample_reg(2) WHEN 2*2,
188 198 sample_reg(3) WHEN 3*2,
189 199 sample_reg(4) WHEN 4*2,
190 200 sample_reg(5) WHEN 5*2,
191 201 sample_reg(6) WHEN 6*2,
192 202 sample_reg(7) WHEN 7*2,
193 203 sample_reg(8) WHEN OTHERS ;
194 204
195 205 -----------------------------------------------------------------------------
196 206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
197 207 -----------------------------------------------------------------------------
198 208
199 209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
200 210
201 211 sample <= sample_reg;
202 212
203 213 END ar_top_ad_conv_RHF1401;
204 214
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