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GPMC_interface almost working
Jeandet Alexis -
r281:c293782dc1e1 alexis
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@@ -142,8 +142,6 resetn_pad : inpad generic map (tech =>
142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
142 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
143
143
144
144
145
146
147 DAC0 : entity work.beagleSigGen
145 DAC0 : entity work.beagleSigGen
148 generic map(
146 generic map(
149 memtech,
147 memtech,
@@ -159,15 +157,16 DAC0 : entity work.beagleSigGen
159 address => GPMC_SLAVE_ADDRESS(3 downto 1),
157 address => GPMC_SLAVE_ADDRESS(3 downto 1),
160 DATA => GPMC_SLAVE_DATA,
158 DATA => GPMC_SLAVE_DATA,
161 WEN => GPMC_SLAVE_WEN,
159 WEN => GPMC_SLAVE_WEN,
162 REN_debug => LED(1),
160 REN_debug => open,
163 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
161 FIFO_FULL => GPMC_SLAVE_STATUS(7 downto 0),
164 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
162 FIFO_EMPTY => GPMC_SLAVE_STATUS(15 downto 8)
165 );
163 );
166
164
167
165
168
166
169 LED(0) <= GPMC_SLAVE_WEN;
167 --LED(0) <= GPMC_SLAVE_ADDRESS(1);
170 LED(2) <= GPMC_WEN;
168 --LED(1) <= GPMC_SLAVE_ADDRESS(2);
169 LED(2) <= GPMC_SLAVE_WEN;
171
170
172 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
171 gpmc_clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (GPMC_CLK_MUX0, gpmc_clk);
173 GPMCS0: entity work.GPMC_SLAVE
172 GPMCS0: entity work.GPMC_SLAVE
@@ -179,6 +178,8 GPMCS0: entity work.GPMC_SLAVE
179 DATA => GPMC_SLAVE_DATA,
178 DATA => GPMC_SLAVE_DATA,
180 ADDRESS => GPMC_SLAVE_ADDRESS,
179 ADDRESS => GPMC_SLAVE_ADDRESS,
181 WEN => GPMC_SLAVE_WEN,
180 WEN => GPMC_SLAVE_WEN,
181 SMP_CKL => LED(0),
182 SMP_WEN => LED(1),
182 GPMC_AD => GPMC_AD,
183 GPMC_AD => GPMC_AD,
183 GPMC_A => GPMC_A,
184 GPMC_A => GPMC_A,
184 GPMC_CLK => gpmc_clk,
185 GPMC_CLK => gpmc_clk,
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@@ -39,6 +39,8 entity GPMC_SLAVE is
39 DATA : out STD_LOGIC_VECTOR(15 downto 0);
39 DATA : out STD_LOGIC_VECTOR(15 downto 0);
40 ADDRESS : out std_logic_vector(19 downto 0);
40 ADDRESS : out std_logic_vector(19 downto 0);
41 WEN : out STD_LOGIC;
41 WEN : out STD_LOGIC;
42 SMP_CKL : out STD_LOGIC;
43 SMP_WEN : out STD_LOGIC;
42 GPMC_AD : inout std_logic_vector(15 downto 0);
44 GPMC_AD : inout std_logic_vector(15 downto 0);
43 GPMC_A : in std_logic_vector(19 downto 0);
45 GPMC_A : in std_logic_vector(19 downto 0);
44 GPMC_CLK : in std_logic;
46 GPMC_CLK : in std_logic;
@@ -55,12 +57,20 end GPMC_SLAVE;
55
57
56 architecture Behavioral of GPMC_SLAVE is
58 architecture Behavioral of GPMC_SLAVE is
57
59
58 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
60 signal data_out : std_logic_vector(15 downto 0) := (others => '0');
59 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
61 signal data_in : std_logic_vector(15 downto 0) := (others => '0');
62 signal data_in_reg0 : std_logic_vector(15 downto 0) := (others => '0');
63 signal data_in_reg1 : std_logic_vector(15 downto 0) := (others => '0');
64 signal data_in_reg2 : std_logic_vector(15 downto 0) := (others => '0');
65 signal address_reg0 : std_logic_vector(19 downto 0) := (others => '0');
66 signal address_reg1 : std_logic_vector(19 downto 0) := (others => '0');
67 signal address_reg2 : std_logic_vector(19 downto 0) := (others => '0');
68 signal ADVN_ALE_reg : std_logic_vector(3 downto 0) := (others => '0');
69
60
70
61 signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0');
71 signal GPMC_CLK_reg : std_logic_vector(3 downto 0) := (others => '0');
62 signal data_r : std_logic_vector(15 downto 0) := (others => '0');
72 signal data_r : std_logic_vector(15 downto 0) := (others => '0');
63
73 signal GPMC_WEN_reg : std_logic_vector(3 downto 0) := (others => '0');
64
74
65 signal outen : std_logic := '0';
75 signal outen : std_logic := '0';
66
76
@@ -79,29 +89,59 port map (
79 );
89 );
80
90
81 GPMC_WAIT0 <= '1';
91 GPMC_WAIT0 <= '1';
92 SMP_CKL <= GPMC_CLK_reg(0);
93 SMP_WEN <= GPMC_WEN_reg(2);
82
94
95 process(reset,clk)
96 begin
97 if reset = '0' then
98 GPMC_CLK_reg <= "0000";
99 ADDRESS <= (others => '0');
100 ADVN_ALE_reg <= (others => '0');
101 address_reg0 <= (others => '0');
102 address_reg1 <= (others => '0');
103 address_reg2 <= (others => '0');
104 elsif clk'event and clk = '1' then
105 GPMC_CLK_reg(0) <= GPMC_CLK;
106 GPMC_CLK_reg(1) <= GPMC_CLK_reg(0);
107 GPMC_CLK_reg(2) <= GPMC_CLK_reg(1);
108 ADVN_ALE_reg(0) <= GPMC_ADVN_ALE;
109 ADVN_ALE_reg(1) <= ADVN_ALE_reg(0);
110 ADVN_ALE_reg(2) <= ADVN_ALE_reg(1);
111 address_reg0 <= GPMC_A;
112 address_reg1 <= address_reg0;
113 address_reg2 <= address_reg1;
114 if GPMC_CLK_reg(1) = '1' and GPMC_CLK_reg(2) = '0' then
115 if ADVN_ALE_reg(2) = '0' then
116 ADDRESS <= address_reg2;
117 end if;
118 end if;
119
120 end if;
121 end process;
83
122
84
123
85 process(reset,clk)
124 process(reset,clk)
86 begin
125 begin
87 if reset = '0' then
126 if reset = '0' then
88 WEN <= '1';
127 WEN <= '1';
89 GPMC_CLK_reg <= "0000";
128 GPMC_WEN_reg <= "0000";
90 ADDRESS <= (others => '0');
129 data_in_reg0 <= (others => '0');
130 data_in_reg1 <= (others => '0');
131 data_in_reg2 <= (others => '0');
91 elsif clk'event and clk = '1' then
132 elsif clk'event and clk = '1' then
92 GPMC_CLK_reg(0) <= GPMC_CLK;
133 GPMC_WEN_reg(0) <= GPMC_WEN;
93 if GPMC_CLK = '0' and GPMC_CLK_reg(0) = '1' then
134 GPMC_WEN_reg(1) <= GPMC_WEN_reg(0);
94 if GPMC_WEN = '0' then
135 GPMC_WEN_reg(2) <= GPMC_WEN_reg(1);
95 WEN <= '0';
136 data_in_reg0 <= data_in;
96 DATA <= data_in;
137 data_in_reg1 <= data_in_reg0;
97 end if;
138 data_in_reg2 <= data_in_reg1;
98 if GPMC_ADVN_ALE = '0' then
139 if GPMC_WEN_reg(2) = '1' and GPMC_WEN_reg(1) = '0' then
99 ADDRESS <= GPMC_A;
140 WEN <= '0';
100 end if;
141 DATA <= data_in_reg2;
101 else
142 else
102 WEN <= '1';
143 WEN <= '1';
103 end if;
144 end if;
104
105 end if;
145 end if;
106 end process;
146 end process;
107
147
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@@ -75,174 +75,174 begin
75 FIFO_FULL <= FIFO_FULL_net;
75 FIFO_FULL <= FIFO_FULL_net;
76 FIFO_EMPTY <= FIFO_EMPTY_net;
76 FIFO_EMPTY <= FIFO_EMPTY_net;
77
77
78 --fron_fifo1: lpp_fifo
78 fron_fifo1: lpp_fifo
79 -- generic map(
79 generic map(
80 -- tech => memtech,
80 tech => memtech,
81 -- Mem_use => 1, --use RAM not CELS
81 Mem_use => 1, --use RAM not CELS
82 -- DataSz => 16,
82 DataSz => 16,
83 -- AddrSz => 8
83 AddrSz => 8
84 -- )
84 )
85 -- port map(
85 port map(
86 -- rstn => rstn,
86 rstn => rstn,
87 -- ReUse => '0',
87 ReUse => '0',
88 -- rclk => clk,
88 rclk => clk,
89 -- ren => FIFO_REN,
89 ren => FIFO_REN,
90 -- rdata => FIFO_out(0),
90 rdata => FIFO_out(0),
91 -- empty => FIFO_EMPTY_net(0),
91 empty => FIFO_EMPTY_net(0),
92 -- raddr => open,
92 raddr => open,
93 -- wclk => clk,
93 wclk => clk,
94 -- wen => FIFO_WEN(0),
94 wen => FIFO_WEN(0),
95 -- wdata => DATA_reg,
95 wdata => DATA_reg,
96 -- full => FIFO_FULL_net(0),
96 full => FIFO_FULL_net(0),
97 -- waddr => open
97 waddr => open
98 -- );
98 );
99 --fron_fifo2: lpp_fifo
99 fron_fifo2: lpp_fifo
100 -- generic map(
100 generic map(
101 -- tech => memtech,
101 tech => memtech,
102 -- Mem_use => 1, --use RAM not CELS
102 Mem_use => 1, --use RAM not CELS
103 -- DataSz => 16,
103 DataSz => 16,
104 -- AddrSz => 8
104 AddrSz => 8
105 -- )
105 )
106 -- port map(
106 port map(
107 -- rstn => rstn,
107 rstn => rstn,
108 -- ReUse => '0',
108 ReUse => '0',
109 -- rclk => clk,
109 rclk => clk,
110 -- ren => FIFO_REN,
110 ren => FIFO_REN,
111 -- rdata => FIFO_out(1),
111 rdata => FIFO_out(1),
112 -- empty => FIFO_EMPTY_net(1),
112 empty => FIFO_EMPTY_net(1),
113 -- raddr => open,
113 raddr => open,
114 -- wclk => clk,
114 wclk => clk,
115 -- wen => FIFO_WEN(1),
115 wen => FIFO_WEN(1),
116 -- wdata => DATA_reg,
116 wdata => DATA_reg,
117 -- full => FIFO_FULL_net(1),
117 full => FIFO_FULL_net(1),
118 -- waddr => open
118 waddr => open
119 -- );
119 );
120 --fron_fifo3: lpp_fifo
120 fron_fifo3: lpp_fifo
121 -- generic map(
121 generic map(
122 -- tech => memtech,
122 tech => memtech,
123 -- Mem_use => 1, --use RAM not CELS
123 Mem_use => 1, --use RAM not CELS
124 -- DataSz => 16,
124 DataSz => 16,
125 -- AddrSz => 8
125 AddrSz => 8
126 -- )
126 )
127 -- port map(
127 port map(
128 -- rstn => rstn,
128 rstn => rstn,
129 -- ReUse => '0',
129 ReUse => '0',
130 -- rclk => clk,
130 rclk => clk,
131 -- ren => FIFO_REN,
131 ren => FIFO_REN,
132 -- rdata => FIFO_out(2),
132 rdata => FIFO_out(2),
133 -- empty => FIFO_EMPTY_net(2),
133 empty => FIFO_EMPTY_net(2),
134 -- raddr => open,
134 raddr => open,
135 -- wclk => clk,
135 wclk => clk,
136 -- wen => FIFO_WEN(2),
136 wen => FIFO_WEN(2),
137 -- wdata => DATA_reg,
137 wdata => DATA_reg,
138 -- full => FIFO_FULL_net(2),
138 full => FIFO_FULL_net(2),
139 -- waddr => open
139 waddr => open
140 -- );
140 );
141 --fron_fifo4: lpp_fifo
141 fron_fifo4: lpp_fifo
142 -- generic map(
142 generic map(
143 -- tech => memtech,
143 tech => memtech,
144 -- Mem_use => 1, --use RAM not CELS
144 Mem_use => 1, --use RAM not CELS
145 -- DataSz => 16,
145 DataSz => 16,
146 -- AddrSz => 8
146 AddrSz => 8
147 -- )
147 )
148 -- port map(
148 port map(
149 -- rstn => rstn,
149 rstn => rstn,
150 -- ReUse => '0',
150 ReUse => '0',
151 -- rclk => clk,
151 rclk => clk,
152 -- ren => FIFO_REN,
152 ren => FIFO_REN,
153 -- rdata => FIFO_out(3),
153 rdata => FIFO_out(3),
154 -- empty => FIFO_EMPTY_net(3),
154 empty => FIFO_EMPTY_net(3),
155 -- raddr => open,
155 raddr => open,
156 -- wclk => clk,
156 wclk => clk,
157 -- wen => FIFO_WEN(3),
157 wen => FIFO_WEN(3),
158 -- wdata => DATA_reg,
158 wdata => DATA_reg,
159 -- full => FIFO_FULL_net(3),
159 full => FIFO_FULL_net(3),
160 -- waddr => open
160 waddr => open
161 -- );
161 );
162 --fron_fifo5: lpp_fifo
162 fron_fifo5: lpp_fifo
163 -- generic map(
163 generic map(
164 -- tech => memtech,
164 tech => memtech,
165 -- Mem_use => 1, --use RAM not CELS
165 Mem_use => 1, --use RAM not CELS
166 -- DataSz => 16,
166 DataSz => 16,
167 -- AddrSz => 8
167 AddrSz => 8
168 -- )
168 )
169 -- port map(
169 port map(
170 -- rstn => rstn,
170 rstn => rstn,
171 -- ReUse => '0',
171 ReUse => '0',
172 -- rclk => clk,
172 rclk => clk,
173 -- ren => FIFO_REN,
173 ren => FIFO_REN,
174 -- rdata => FIFO_out(4),
174 rdata => FIFO_out(4),
175 -- empty => FIFO_EMPTY_net(4),
175 empty => FIFO_EMPTY_net(4),
176 -- raddr => open,
176 raddr => open,
177 -- wclk => clk,
177 wclk => clk,
178 -- wen => FIFO_WEN(4),
178 wen => FIFO_WEN(4),
179 -- wdata => DATA_reg,
179 wdata => DATA_reg,
180 -- full => FIFO_FULL_net(4),
180 full => FIFO_FULL_net(4),
181 -- waddr => open
181 waddr => open
182 -- );
182 );
183 --fron_fifo6: lpp_fifo
183 fron_fifo6: lpp_fifo
184 -- generic map(
184 generic map(
185 -- tech => memtech,
185 tech => memtech,
186 -- Mem_use => 1, --use RAM not CELS
186 Mem_use => 1, --use RAM not CELS
187 -- DataSz => 16,
187 DataSz => 16,
188 -- AddrSz => 8
188 AddrSz => 8
189 -- )
189 )
190 -- port map(
190 port map(
191 -- rstn => rstn,
191 rstn => rstn,
192 -- ReUse => '0',
192 ReUse => '0',
193 -- rclk => clk,
193 rclk => clk,
194 -- ren => FIFO_REN,
194 ren => FIFO_REN,
195 -- rdata => FIFO_out(5),
195 rdata => FIFO_out(5),
196 -- empty => FIFO_EMPTY_net(5),
196 empty => FIFO_EMPTY_net(5),
197 -- raddr => open,
197 raddr => open,
198 -- wclk => clk,
198 wclk => clk,
199 -- wen => FIFO_WEN(5),
199 wen => FIFO_WEN(5),
200 -- wdata => DATA_reg,
200 wdata => DATA_reg,
201 -- full => FIFO_FULL_net(5),
201 full => FIFO_FULL_net(5),
202 -- waddr => open
202 waddr => open
203 -- );
203 );
204 --fron_fifo7: lpp_fifo
204 fron_fifo7: lpp_fifo
205 -- generic map(
205 generic map(
206 -- tech => memtech,
206 tech => memtech,
207 -- Mem_use => 1, --use RAM not CELS
207 Mem_use => 1, --use RAM not CELS
208 -- DataSz => 16,
208 DataSz => 16,
209 -- AddrSz => 8
209 AddrSz => 8
210 -- )
210 )
211 -- port map(
211 port map(
212 -- rstn => rstn,
212 rstn => rstn,
213 -- ReUse => '0',
213 ReUse => '0',
214 -- rclk => clk,
214 rclk => clk,
215 -- ren => FIFO_REN,
215 ren => FIFO_REN,
216 -- rdata => FIFO_out(6),
216 rdata => FIFO_out(6),
217 -- empty => FIFO_EMPTY_net(6),
217 empty => FIFO_EMPTY_net(6),
218 -- raddr => open,
218 raddr => open,
219 -- wclk => clk,
219 wclk => clk,
220 -- wen => FIFO_WEN(6),
220 wen => FIFO_WEN(6),
221 -- wdata => DATA_reg,
221 wdata => DATA_reg,
222 -- full => FIFO_FULL_net(6),
222 full => FIFO_FULL_net(6),
223 -- waddr => open
223 waddr => open
224 -- );
224 );
225 --fron_fifo8: lpp_fifo
225 fron_fifo8: lpp_fifo
226 -- generic map(
226 generic map(
227 -- tech => memtech,
227 tech => memtech,
228 -- Mem_use => 1, --use RAM not CELS
228 Mem_use => 1, --use RAM not CELS
229 -- DataSz => 16,
229 DataSz => 16,
230 -- AddrSz => 8
230 AddrSz => 8
231 -- )
231 )
232 -- port map(
232 port map(
233 -- rstn => rstn,
233 rstn => rstn,
234 -- ReUse => '0',
234 ReUse => '0',
235 -- rclk => clk,
235 rclk => clk,
236 -- ren => FIFO_REN,
236 ren => FIFO_REN,
237 -- rdata => FIFO_out(7),
237 rdata => FIFO_out(7),
238 -- empty => FIFO_EMPTY_net(7),
238 empty => FIFO_EMPTY_net(7),
239 -- raddr => open,
239 raddr => open,
240 -- wclk => clk,
240 wclk => clk,
241 -- wen => FIFO_WEN(7),
241 wen => FIFO_WEN(7),
242 -- wdata => DATA_reg,
242 wdata => DATA_reg,
243 -- full => FIFO_FULL_net(7),
243 full => FIFO_FULL_net(7),
244 -- waddr => open
244 waddr => open
245 -- );
245 );
246
246
247 REN_debug <= FIFO_REN;
247 REN_debug <= FIFO_REN;
248
248
@@ -257,28 +257,20 begin
257 case address is
257 case address is
258 when "000"=>
258 when "000"=>
259 FIFO_WEN <= "11111110";
259 FIFO_WEN <= "11111110";
260 FIFO_out(0) <= DATA;
261 when "001"=>
260 when "001"=>
262 FIFO_WEN <= "11111101";
261 FIFO_WEN <= "11111101";
263 FIFO_out(1) <= DATA;
264 when "010"=>
262 when "010"=>
265 FIFO_WEN <= "11111011";
263 FIFO_WEN <= "11111011";
266 FIFO_out(2) <= DATA;
267 when "011"=>
264 when "011"=>
268 FIFO_WEN <= "11110111";
265 FIFO_WEN <= "11110111";
269 FIFO_out(3) <= DATA;
270 when "100"=>
266 when "100"=>
271 FIFO_WEN <= "11101111";
267 FIFO_WEN <= "11101111";
272 FIFO_out(4) <= DATA;
273 when "101"=>
268 when "101"=>
274 FIFO_WEN <= "11011111";
269 FIFO_WEN <= "11011111";
275 FIFO_out(5) <= DATA;
276 when "110"=>
270 when "110"=>
277 FIFO_WEN <= "10111111";
271 FIFO_WEN <= "10111111";
278 FIFO_out(6) <= DATA;
279 when "111"=>
272 when "111"=>
280 FIFO_WEN <= "01111111";
273 FIFO_WEN <= "01111111";
281 FIFO_out(7) <= DATA;
282 when others =>
274 when others =>
283 FIFO_WEN <= "11111111";
275 FIFO_WEN <= "11111111";
284 end case;
276 end case;
@@ -326,7 +318,7 DAC0 : DAC8581
326
318
327 smpclk0: Clk_divider
319 smpclk0: Clk_divider
328 GENERIC map(OSC_freqHz => 150000000,
320 GENERIC map(OSC_freqHz => 150000000,
329 TargetFreq_Hz => 32000)
321 TargetFreq_Hz => 256000)
330 PORT map(
322 PORT map(
331 clk => clk,
323 clk => clk,
332 reset => rstn,
324 reset => rstn,
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