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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.numeric_std.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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use techmap.allclkgen.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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library esa;
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use esa.memoryctrl.all;
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--use gaisler.sim.all;
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library lpp;
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use lpp.lpp_ad_conv.all;
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use lpp.lpp_amba.all;
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use lpp.apb_devices_list.all;
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use lpp.general_purpose.all;
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use lpp.lpp_cna.all;
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use lpp.lpp_memory.all;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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use work.config.all;
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entity beagleSigGen is
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generic (
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH
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);
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Port (
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clk : in STD_LOGIC;
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rstn : in STD_LOGIC;
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CAL_IN_SCK : out std_ulogic;
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DAC_nCS : out std_ulogic;
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DAC_SDI : out std_logic_vector(7 downto 0);
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address : in std_logic_vector(2 downto 0);
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DATA : in std_logic_vector(15 downto 0);
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REN_debug : out std_logic;
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WEN : in std_logic;
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FIFO_FULL : out std_logic_vector(7 downto 0);
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FIFO_EMPTY : out std_logic_vector(7 downto 0)
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);
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end beagleSigGen;
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architecture Behavioral of beagleSigGen is
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signal FIFO_FULL_net : std_logic_vector(7 downto 0);
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signal FIFO_EMPTY_net : std_logic_vector(7 downto 0);
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signal FIFO_WEN : std_logic_vector(7 downto 0);
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signal FIFO_REN : std_logic;
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subtype TAB16 is std_logic_vector(15 downto 0);
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type FIFOout_t is array(7 downto 0) of TAB16;
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signal FIFO_out : FIFOout_t;
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signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0);
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signal smpclk : std_logic;
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signal smpclk_reg : std_logic;
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signal DAC_SDO : std_logic;
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signal DATA_reg : std_logic_vector(15 downto 0);
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begin
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FIFO_FULL <= FIFO_FULL_net;
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FIFO_EMPTY <= FIFO_EMPTY_net;
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fron_fifo1: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(0),
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empty => FIFO_EMPTY_net(0),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(0),
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wdata => DATA_reg,
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full => FIFO_FULL_net(0),
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waddr => open
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);
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fron_fifo2: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(1),
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empty => FIFO_EMPTY_net(1),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(1),
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wdata => DATA_reg,
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full => FIFO_FULL_net(1),
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waddr => open
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);
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fron_fifo3: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(2),
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empty => FIFO_EMPTY_net(2),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(2),
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wdata => DATA_reg,
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full => FIFO_FULL_net(2),
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waddr => open
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);
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fron_fifo4: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(3),
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empty => FIFO_EMPTY_net(3),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(3),
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wdata => DATA_reg,
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full => FIFO_FULL_net(3),
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waddr => open
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);
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fron_fifo5: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(4),
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empty => FIFO_EMPTY_net(4),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(4),
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wdata => DATA_reg,
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full => FIFO_FULL_net(4),
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waddr => open
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);
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fron_fifo6: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(5),
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empty => FIFO_EMPTY_net(5),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(5),
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wdata => DATA_reg,
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full => FIFO_FULL_net(5),
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waddr => open
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);
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fron_fifo7: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(6),
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empty => FIFO_EMPTY_net(6),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(6),
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wdata => DATA_reg,
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full => FIFO_FULL_net(6),
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waddr => open
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);
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fron_fifo8: lpp_fifo
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generic map(
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tech => memtech,
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Mem_use => 1, --use RAM not CELS
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DataSz => 16,
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AddrSz => 8
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)
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port map(
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rstn => rstn,
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ReUse => '0',
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rclk => clk,
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ren => FIFO_REN,
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rdata => FIFO_out(7),
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empty => FIFO_EMPTY_net(7),
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raddr => open,
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wclk => clk,
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wen => FIFO_WEN(7),
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wdata => DATA_reg,
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full => FIFO_FULL_net(7),
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waddr => open
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);
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REN_debug <= FIFO_REN;
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process(clk,rstn)
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begin
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if rstn = '0' then
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DATA_reg <= (others => '0');
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FIFO_WEN <= (others => '0');
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elsif clk'event and clk = '1' then
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if WEN = '0' then
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DATA_reg <= DATA;
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case address is
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when "000"=>
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FIFO_WEN <= "11111110";
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when "001"=>
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FIFO_WEN <= "11111101";
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when "010"=>
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FIFO_WEN <= "11111011";
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when "011"=>
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FIFO_WEN <= "11110111";
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when "100"=>
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FIFO_WEN <= "11101111";
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when "101"=>
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FIFO_WEN <= "11011111";
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when "110"=>
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FIFO_WEN <= "10111111";
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when "111"=>
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FIFO_WEN <= "01111111";
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when others =>
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FIFO_WEN <= "11111111";
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end case;
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end if;
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end if;
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end process;
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all_bits: FOR I in 15 downto 0 GENERATE
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all_chans: FOR J in 7 downto 0 GENERATE
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DAC_DATA(J,I) <= FIFO_out(J)(I);
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end GENERATE;
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end GENERATE;
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process(clk,rstn)
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begin
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if rstn = '0' then
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FIFO_REN <= '1';
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smpclk_reg <= '0';
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elsif clk'event and clk = '1' then
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smpclk_reg <= smpclk;
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if smpclk = '1' and smpclk_reg = '0' then
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FIFO_REN <= '0';
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else
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FIFO_REN <= '1';
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end if;
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end if;
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end process;
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DAC0 : DAC8581
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generic map(150,8)
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Port map(
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clk => clk,
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rstn => rstn,
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smpclk => smpclk,
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sclk => CAL_IN_SCK,
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csn => DAC_nCS,
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sdo => DAC_SDI,
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smp_in => DAC_DATA
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);
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smpclk0: Clk_divider
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GENERIC map(OSC_freqHz => 150000000,
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TargetFreq_Hz => 256000)
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PORT map(
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clk => clk,
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reset => rstn,
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clk_divided => smpclk
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);
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end Behavioral;
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