library ieee; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; library grlib, techmap; use grlib.amba.all; use grlib.amba.all; use grlib.stdlib.all; use techmap.gencomp.all; use techmap.allclkgen.all; library gaisler; use gaisler.memctrl.all; use gaisler.leon3.all; use gaisler.uart.all; use gaisler.misc.all; library esa; use esa.memoryctrl.all; --use gaisler.sim.all; library lpp; use lpp.lpp_ad_conv.all; use lpp.lpp_amba.all; use lpp.apb_devices_list.all; use lpp.general_purpose.all; use lpp.lpp_cna.all; use lpp.lpp_memory.all; Library UNISIM; use UNISIM.vcomponents.all; use work.config.all; entity beagleSigGen is generic ( memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH ); Port ( clk : in STD_LOGIC; rstn : in STD_LOGIC; CAL_IN_SCK : out std_ulogic; DAC_nCS : out std_ulogic; DAC_SDI : out std_logic_vector(7 downto 0); address : in std_logic_vector(2 downto 0); DATA : in std_logic_vector(15 downto 0); REN_debug : out std_logic; WEN : in std_logic; FIFO_FULL : out std_logic_vector(7 downto 0); FIFO_EMPTY : out std_logic_vector(7 downto 0) ); end beagleSigGen; architecture Behavioral of beagleSigGen is signal FIFO_FULL_net : std_logic_vector(7 downto 0); signal FIFO_EMPTY_net : std_logic_vector(7 downto 0); signal FIFO_WEN : std_logic_vector(7 downto 0); signal FIFO_REN : std_logic; subtype TAB16 is std_logic_vector(15 downto 0); type FIFOout_t is array(7 downto 0) of TAB16; signal FIFO_out : FIFOout_t; signal DAC_DATA : CNA_16bit_T(7 downto 0,15 downto 0); signal smpclk : std_logic; signal smpclk_reg : std_logic; signal DAC_SDO : std_logic; signal DATA_reg : std_logic_vector(15 downto 0); begin FIFO_FULL <= FIFO_FULL_net; FIFO_EMPTY <= FIFO_EMPTY_net; fron_fifo1: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(0), empty => FIFO_EMPTY_net(0), raddr => open, wclk => clk, wen => FIFO_WEN(0), wdata => DATA_reg, full => FIFO_FULL_net(0), waddr => open ); fron_fifo2: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(1), empty => FIFO_EMPTY_net(1), raddr => open, wclk => clk, wen => FIFO_WEN(1), wdata => DATA_reg, full => FIFO_FULL_net(1), waddr => open ); fron_fifo3: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(2), empty => FIFO_EMPTY_net(2), raddr => open, wclk => clk, wen => FIFO_WEN(2), wdata => DATA_reg, full => FIFO_FULL_net(2), waddr => open ); fron_fifo4: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(3), empty => FIFO_EMPTY_net(3), raddr => open, wclk => clk, wen => FIFO_WEN(3), wdata => DATA_reg, full => FIFO_FULL_net(3), waddr => open ); fron_fifo5: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(4), empty => FIFO_EMPTY_net(4), raddr => open, wclk => clk, wen => FIFO_WEN(4), wdata => DATA_reg, full => FIFO_FULL_net(4), waddr => open ); fron_fifo6: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(5), empty => FIFO_EMPTY_net(5), raddr => open, wclk => clk, wen => FIFO_WEN(5), wdata => DATA_reg, full => FIFO_FULL_net(5), waddr => open ); fron_fifo7: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(6), empty => FIFO_EMPTY_net(6), raddr => open, wclk => clk, wen => FIFO_WEN(6), wdata => DATA_reg, full => FIFO_FULL_net(6), waddr => open ); fron_fifo8: lpp_fifo generic map( tech => memtech, Mem_use => 1, --use RAM not CELS DataSz => 16, AddrSz => 8 ) port map( rstn => rstn, ReUse => '0', rclk => clk, ren => FIFO_REN, rdata => FIFO_out(7), empty => FIFO_EMPTY_net(7), raddr => open, wclk => clk, wen => FIFO_WEN(7), wdata => DATA_reg, full => FIFO_FULL_net(7), waddr => open ); REN_debug <= FIFO_REN; process(clk,rstn) begin if rstn = '0' then DATA_reg <= (others => '0'); FIFO_WEN <= (others => '0'); elsif clk'event and clk = '1' then if WEN = '0' then DATA_reg <= DATA; case address is when "000"=> FIFO_WEN <= "11111110"; when "001"=> FIFO_WEN <= "11111101"; when "010"=> FIFO_WEN <= "11111011"; when "011"=> FIFO_WEN <= "11110111"; when "100"=> FIFO_WEN <= "11101111"; when "101"=> FIFO_WEN <= "11011111"; when "110"=> FIFO_WEN <= "10111111"; when "111"=> FIFO_WEN <= "01111111"; when others => FIFO_WEN <= "11111111"; end case; end if; end if; end process; all_bits: FOR I in 15 downto 0 GENERATE all_chans: FOR J in 7 downto 0 GENERATE DAC_DATA(J,I) <= FIFO_out(J)(I); end GENERATE; end GENERATE; process(clk,rstn) begin if rstn = '0' then FIFO_REN <= '1'; smpclk_reg <= '0'; elsif clk'event and clk = '1' then smpclk_reg <= smpclk; if smpclk = '1' and smpclk_reg = '0' then FIFO_REN <= '0'; else FIFO_REN <= '1'; end if; end if; end process; DAC0 : DAC8581 generic map(150,8) Port map( clk => clk, rstn => rstn, smpclk => smpclk, sclk => CAL_IN_SCK, csn => DAC_nCS, sdo => DAC_SDI, smp_in => DAC_DATA ); smpclk0: Clk_divider GENERIC map(OSC_freqHz => 150000000, TargetFreq_Hz => 256000) PORT map( clk => clk, reset => rstn, clk_divided => smpclk ); end Behavioral;