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1
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
7
8
9 library ieee;
10 use ieee.std_logic_1164.all;
11 library grlib;
12 use grlib.amba.all;
13 use std.textio.all;
14
15
16 package apb_devices_list is
17
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_BALISE : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
36 constant LPP_DELAY : amba_device_type := 16#16#;
37 constant LPP_DMA_TYPE : amba_device_type := 16#17#;
38 constant LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39
40
41 end;
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1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 LIBRARY grlib;
5
6 LIBRARY lpp;
7 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.FILTERcfg.ALL;
10 USE lpp.lpp_memory.ALL;
11 LIBRARY techmap;
12 USE techmap.gencomp.ALL;
13
14 PACKAGE lpp_top_lfr_pkg IS
15
16 COMPONENT lpp_top_acq
17 GENERIC (
18 tech : integer);
19 PORT (
20 cnv_run : IN STD_LOGIC;
21 cnv : OUT STD_LOGIC;
22 sck : OUT STD_LOGIC;
23 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
24 cnv_clk : IN STD_LOGIC;
25 cnv_rstn : IN STD_LOGIC;
26 clk : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
37 END COMPONENT;
38
39 COMPONENT lpp_top_apbreg
40 GENERIC (
41 pindex : INTEGER;
42 paddr : INTEGER;
43 pmask : INTEGER;
44 pirq : INTEGER);
45 PORT (
46 HCLK : IN STD_ULOGIC;
47 HRESETn : IN STD_ULOGIC;
48 apbi : IN apb_slv_in_type;
49 apbo : OUT apb_slv_out_type;
50 ready_matrix_f0_0 : IN STD_LOGIC;
51 ready_matrix_f0_1 : IN STD_LOGIC;
52 ready_matrix_f1 : IN STD_LOGIC;
53 ready_matrix_f2 : IN STD_LOGIC;
54 error_anticipating_empty_fifo : IN STD_LOGIC;
55 error_bad_component_error : IN STD_LOGIC;
56 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 status_ready_matrix_f0_0 : OUT STD_LOGIC;
58 status_ready_matrix_f0_1 : OUT STD_LOGIC;
59 status_ready_matrix_f1 : OUT STD_LOGIC;
60 status_ready_matrix_f2 : OUT STD_LOGIC;
61 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
62 status_error_bad_component_error : OUT STD_LOGIC;
63 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
64 config_active_interruption_onError : OUT STD_LOGIC;
65 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
67 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
69 END COMPONENT;
70
71 END lpp_top_lfr_pkg; No newline at end of file
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1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5
5 USE lpp.lpp_top_lfr_pkg.ALL;
6 -------------------------------------------------------------------------------
6
7
7 -------------------------------------------------------------------------------
8 ENTITY TB_Data_Acquisition IS
8
9
9 ENTITY TB_Data_Acquisition IS
10 END TB_Data_Acquisition;
10
11
11 END TB_Data_Acquisition;
12 -------------------------------------------------------------------------------
12
13
13 -------------------------------------------------------------------------------
14 ARCHITECTURE tb OF TB_Data_Acquisition IS
14
15
15 ARCHITECTURE tb OF TB_Data_Acquisition IS
16 COMPONENT TestModule_ADS7886
16
17 GENERIC (
17 COMPONENT TestModule_ADS7886
18 freq : INTEGER;
18 GENERIC (
19 amplitude : INTEGER;
19 freq : INTEGER;
20 impulsion : INTEGER);
20 amplitude : INTEGER;
21 PORT (
21 impulsion : INTEGER);
22 cnv_run : IN STD_LOGIC;
22 PORT (
23 cnv : IN STD_LOGIC;
23 cnv_run : IN STD_LOGIC;
24 sck : IN STD_LOGIC;
24 cnv : IN STD_LOGIC;
25 sdo : OUT STD_LOGIC);
25 sck : IN STD_LOGIC;
26 END COMPONENT;
26 sdo : OUT STD_LOGIC);
27
27 END COMPONENT;
28 COMPONENT Top_Data_Acquisition
28
29 PORT (
29 -- component ports
30 cnv_run : IN STD_LOGIC;
30 SIGNAL cnv_rstn : STD_LOGIC;
31 cnv : OUT STD_LOGIC;
31 SIGNAL cnv : STD_LOGIC;
32 sck : OUT STD_LOGIC;
32 SIGNAL rstn : STD_LOGIC;
33 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
33 SIGNAL sck : STD_LOGIC;
34 cnv_clk : IN STD_LOGIC;
34 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
35 cnv_rstn : IN STD_LOGIC;
35 SIGNAL run_cnv : STD_LOGIC;
36 clk : IN STD_LOGIC;
36
37 rstn : IN STD_LOGIC;
37
38 --
38 -- clock
39 sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 signal Clk : STD_LOGIC := '1';
40 sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
40 SIGNAL cnv_clk : STD_LOGIC := '1';
41 sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41
42 sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 -----------------------------------------------------------------------------
43 --
43 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
45 -----------------------------------------------------------------------------
46 sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --
48 -----------------------------------------------------------------------------
49 sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
49 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
50 sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
50 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
51 sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
51 -----------------------------------------------------------------------------
52 sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
52 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
53 --
53 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
54 sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
55 sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
55 BEGIN -- tb
56 sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
56
57 sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
57 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
58 END COMPONENT;
58 TestModule_ADS7886_u: TestModule_ADS7886
59
59 GENERIC MAP (
60 -- component ports
60 freq => 24*(I+1),
61 SIGNAL cnv_rstn : STD_LOGIC;
61 amplitude => 30000/(I+1),
62 SIGNAL cnv : STD_LOGIC;
62 impulsion => 0)
63 SIGNAL rstn : STD_LOGIC;
63 PORT MAP (
64 SIGNAL sck : STD_LOGIC;
64 cnv_run => run_cnv,
65 SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
65 cnv => cnv,
66 SIGNAL run_cnv : STD_LOGIC;
66 sck => sck,
67
67 sdo => sdo(I));
68
68 END GENERATE MODULE_ADS7886;
69 -- clock
69
70 signal Clk : STD_LOGIC := '1';
70 TestModule_ADS7886_u: TestModule_ADS7886
71 SIGNAL cnv_clk : STD_LOGIC := '1';
71 GENERIC MAP (
72
72 freq => 0,
73 -----------------------------------------------------------------------------
73 amplitude => 30000,
74 SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
74 impulsion => 1)
75 SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
75 PORT MAP (
76 SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
76 cnv_run => run_cnv,
77 SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
77 cnv => cnv,
78 -----------------------------------------------------------------------------
78 sck => sck,
79 SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 sdo => sdo(7));
80 SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
80
81 SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
81
82 SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 -- clock generation
83 -----------------------------------------------------------------------------
83 Clk <= not Clk after 20 ns; -- 25 Mhz
84 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
85 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
85
86 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 -- waveform generation
87 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 WaveGen_Proc: process
88 -----------------------------------------------------------------------------
88 begin
89 SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 -- insert signal assignments here
90 SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
90 wait until Clk = '1';
91 SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 rstn <= '0';
92 SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 cnv_rstn <= '0';
93
93 run_cnv <= '0';
94
94 wait until Clk = '1';
95 BEGIN -- tb
95 wait until Clk = '1';
96
96 wait until Clk = '1';
97 MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
97 rstn <= '1';
98 TestModule_ADS7886_u: TestModule_ADS7886
98 cnv_rstn <= '1';
99 GENERIC MAP (
99 wait until Clk = '1';
100 freq => 24*(I+1),
100 wait until Clk = '1';
101 amplitude => 30000/(I+1),
101 wait until Clk = '1';
102 impulsion => 0)
102 wait until Clk = '1';
103 PORT MAP (
103 wait until Clk = '1';
104 cnv_run => run_cnv,
104 wait until Clk = '1';
105 cnv => cnv,
105 run_cnv <= '1';
106 sck => sck,
106 wait;
107 sdo => sdo(I));
107
108 END GENERATE MODULE_ADS7886;
108 end process WaveGen_Proc;
109
109
110 TestModule_ADS7886_u: TestModule_ADS7886
110 -----------------------------------------------------------------------------
111 GENERIC MAP (
111
112 freq => 0,
112 Top_Data_Acquisition_1: lpp_top_acq
113 amplitude => 30000,
113 PORT MAP (
114 impulsion => 1)
114 cnv_run => run_cnv,
115 PORT MAP (
115 cnv => cnv,
116 cnv_run => run_cnv,
116 sck => sck,
117 cnv => cnv,
117 sdo => sdo,
118 sck => sck,
118 cnv_clk => cnv_clk,
119 sdo => sdo(7));
119 cnv_rstn => cnv_rstn,
120
120 clk => clk,
121
121 rstn => rstn,
122 -- clock generation
122 --
123 Clk <= not Clk after 20 ns; -- 25 Mhz
123 sample_f0_wen => sample_f0_wen,
124 cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
124 sample_f0_wdata => sample_f0_wdata,
125
125 --
126 -- waveform generation
126 sample_f1_wen => sample_f1_wen,
127 WaveGen_Proc: process
127 sample_f1_wdata => sample_f1_wdata,
128 begin
128 --
129 -- insert signal assignments here
129 sample_f2_wen => sample_f2_wen,
130 wait until Clk = '1';
130 sample_f2_wdata => sample_f2_wdata,
131 rstn <= '0';
131 --
132 cnv_rstn <= '0';
132 sample_f3_wen => sample_f3_wen,
133 run_cnv <= '0';
133 sample_f3_wdata => sample_f3_wdata
134 wait until Clk = '1';
134 );
135 wait until Clk = '1';
135
136 wait until Clk = '1';
136
137 rstn <= '1';
137
138 cnv_rstn <= '1';
138
139 wait until Clk = '1';
139
140 wait until Clk = '1';
140 END tb;
141 wait until Clk = '1';
142 wait until Clk = '1';
143 wait until Clk = '1';
144 wait until Clk = '1';
145 run_cnv <= '1';
146 wait;
147
148 end process WaveGen_Proc;
149
150 -----------------------------------------------------------------------------
151
152 Top_Data_Acquisition_1: Top_Data_Acquisition
153 PORT MAP (
154 cnv_run => run_cnv,
155 cnv => cnv,
156 sck => sck,
157 sdo => sdo,
158 cnv_clk => cnv_clk,
159 cnv_rstn => cnv_rstn,
160 clk => clk,
161 rstn => rstn,
162 --
163 sample_f0_0_ren => sample_f0_0_ren,
164 sample_f0_0_rdata => sample_f0_0_rdata,
165 sample_f0_0_full => sample_f0_0_full,
166 sample_f0_0_empty => sample_f0_0_empty,
167 --
168 sample_f0_1_ren => sample_f0_1_ren,
169 sample_f0_1_rdata => sample_f0_1_rdata,
170 sample_f0_1_full => sample_f0_1_full,
171 sample_f0_1_empty => sample_f0_1_empty,
172 --
173 sample_f1_ren => sample_f1_ren,
174 sample_f1_rdata => sample_f1_rdata,
175 sample_f1_full => sample_f1_full,
176 sample_f1_empty => sample_f1_empty,
177 --
178 sample_f3_ren => sample_f3_ren,
179 sample_f3_rdata => sample_f3_rdata,
180 sample_f3_full => sample_f3_full,
181 sample_f3_empty => sample_f3_empty
182 );
183 sample_f0_0_ren <= (OTHERS => '1');
184 sample_f0_1_ren <= (OTHERS => '1');
185 sample_f1_ren <= (OTHERS => '1');
186 sample_f3_ren <= (OTHERS => '1');
187
188 END tb;
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1
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/general_purpose.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/SYNC_FF.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUXN.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MUX2.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/REG.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_CONTROLER.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_REG.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MAC_MUX2.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/Shifter.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
13 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/MULTIPLIER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
14 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDER.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
15 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ALU.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
16 vcom -quiet -93 -work lpp ../../lib/lpp/general_purpose/ADDRcntr.vhd
17
17
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
18 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/iir_filter.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
19 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/FILTERcfg.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
20 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
21 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CEL_N.vhd
22 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
22 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR2.vhd
23
23 #vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR.vhd
24 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
24
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
25 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/RAM_CTRLR_v2.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
26 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
27 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
28
28 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
29 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
29
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
30 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_memory.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
31 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lpp_FIFO.vhd
32
32 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_memory/lppFIFOxN.vhd
33 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
33
34
34 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/lpp_downsampling/Downsampling.vhd
35 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
35
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
36 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
37
37 vcom -quiet -93 -work lpp e:/opt/tortoiseHG_vhdlib/lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
38 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
38
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/ADS7886_drvr.vhd
39 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_conv.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
40 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/AD7688_drvr.vhd
41
41 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/TestModule_ADS7886.vhd
42 vcom -quiet -93 -work work Top_Data_Acquisition.vhd
42
43 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
43
44
44 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
45 #vsim work.TB_Data_Acquisition
45 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_acq.vhd
46
46 #vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr.vhd
47 #log -r *
47
48 #do wave_data_acquisition.do
48 vcom -quiet -93 -work work TB_Data_Acquisition.vhd
49
50 vsim work.TB_Data_Acquisition
51
52 #log -r *
53 #do wave_data_acquisition.do
49 #run 5 ms No newline at end of file
54 #run 5 ms
Show file before | Show file after | Hide comments
@@ -1,231 +1,38
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/chanelcount
3 add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample
4 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv_high
4 add wave -noupdate -expand -group {Data Acq & Filter} -expand -group DIGITAL_ACQ /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val
5 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/ncycle_cnv
5 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
6 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_clk
6 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
7 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_rstn
7 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
8 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run
8 add wave -noupdate -expand -group {Data Acq & Filter} -group FILTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
9 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv
9 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in_val
10 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/clk
10 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_in
11 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/rstn
11 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out_val
12 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sck
12 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f0} /tb_data_acquisition/top_data_acquisition_1/downsampling_f0/sample_out
13 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sdo
13 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in_val
14 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample
14 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_in
15 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_val
15 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out_val
16 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_cycle_counter
16 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f1} /tb_data_acquisition/top_data_acquisition_1/downsampling_f1/sample_out
17 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_s
17 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in_val
18 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync
18 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_in
19 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_sync_r
19 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out_val
20 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_done
20 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f2} /tb_data_acquisition/top_data_acquisition_1/downsampling_f2/sample_out
21 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/sample_bit_counter
21 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in_val
22 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/shift_reg
22 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_in
23 add wave -noupdate -group {CONVERSION - A/D} /tb_data_acquisition/top_data_acquisition_1/digital_acquisition/cnv_run_sync
23 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out_val
24 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/tech
24 add wave -noupdate -expand -group {Data Acq & Filter} -group {Down f3} /tb_data_acquisition/top_data_acquisition_1/downsampling_f3/sample_out
25 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_sz
25 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wen
26 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/chanelscount
26 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f0_wdata
27 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coef_sz
27 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wen
28 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefcntpercel
28 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f1_wdata
29 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/cels_count
29 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wen
30 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/mem_use
30 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f2_wdata
31 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/reset
31 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wen
32 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/clk
32 add wave -noupdate -expand -group {OUTPUT to FIFO} /tb_data_acquisition/top_data_acquisition_1/sample_f3_wdata
33 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_clk
34 add wave -noupdate -group FILTER -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_in(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_in
35 add wave -noupdate -group FILTER -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/filter/sample_out(7) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(6) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(5) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(4) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(3) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(2) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(1) {-height 15 -radix unsigned} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out(0) {-height 15 -radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/filter/sample_out
36 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/virg_pos
37 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/gotest
38 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefs
39 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/smpl_clk_old
40 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/wd_sel
41 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/read
42 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/svg_addr
43 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/count
44 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/write
45 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/waddr_sel
46 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/go_0
47 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in
48 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_in_bk
49 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/ram_sample_out
50 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_ctrl
51 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_sample_in
52 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_coef_in
53 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/alu_out
54 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentcel
55 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/curentchan
56 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_in_buff
57 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/sample_out_buff
58 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/coefsreg
59 add wave -noupdate -group FILTER /tb_data_acquisition/top_data_acquisition_1/filter/iir_cel_state
60 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_run
61 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv
62 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sck
63 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sdo
64 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_clk
65 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/cnv_rstn
66 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/clk
67 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/rstn
68 add wave -noupdate -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/sample(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/sample(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/sample
69 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_val
70 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/coefs
71 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_in
72 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/sample_filter_out
73 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
74 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/alu_selected_coeff
75 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing
76 add wave -noupdate /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing
77 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/clk
78 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/reset
79 add wave -noupdate -expand -group ALU /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/ctrl
80 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op1
81 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/op2
82 add wave -noupdate -expand -group ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/res
83 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
84 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
85 add wave -noupdate -group ALU_MUX_INPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
86 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/rstn
87 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/clk
88 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/virg_pos
89 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/coefs
90 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src
91 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata
92 add wave -noupdate -group DATA_FLOW -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input
93 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write
94 add wave -noupdate -group DATA_FLOW -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read
95 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst
96 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1
97 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous
98 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
99 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff
100 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl
101 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in
102 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
103 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
104 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
105 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
106 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample
107 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s
108 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff
109 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s
110 add wave -noupdate -group DATA_FLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
111 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/rstn
112 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/clk
113 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/virg_pos
114 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/coefs
115 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
116 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
117 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
118 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
119 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/in_sel_src
120 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_sel_wdata
121 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_write
122 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/ram_read
123 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_rst
124 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/raddr_add1
125 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/waddr_previous
126 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_input
127 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_sel_coeff
128 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/alu_ctrl
129 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_buf
130 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_rotate
131 add wave -noupdate -group IIR_CEL_FILTER_v2 /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_s
132 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s
133 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2
134 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s
135 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(17) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(16) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(15) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(14) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(13) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(12) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(11) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(10) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(9) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(8) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s
136 add wave -noupdate -group IIR_CEL_FILTER_v2 -radix unsigned -expand -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(7) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(6) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(5) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(4) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(3) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(2) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(1) {-radix unsigned} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2(0) {-radix unsigned}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2
137 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/in_sel_src
138 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
139 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
140 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_in
141 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_INPUT_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
142 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/waddr_previous
143 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_write
144 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix hexadecimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_sel_wdata
145 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
146 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
147 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
148 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_RAM -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_input
149 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_read
150 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_rst
151 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/raddr_add1
152 add wave -noupdate -group DATAFLOW -group DATAFLOW_OUTPUT_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
153 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/arraycoeff
154 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef_s
155 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
156 add wave -noupdate -group DATAFLOW -group DATAFLOW_SELECT_COEFF -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_coeff
157 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sel_input
158 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/reg_sample_in
159 add wave -noupdate -group DATAFLOW -group DATAFLOW_INPUT_ALU_MUX -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_output
160 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_ctrl
161 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_coef
162 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_sample
163 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output_s
164 add wave -noupdate -group DATAFLOW -expand -group DATAFLOW_ALU -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_output
165 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
166 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/chanel_ongoing
167 add wave -noupdate -group DATAFLOW /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/cel_ongoing
168 add wave -noupdate -group DATAFLOW -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
169 add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rstn
170 add wave -noupdate -group DATAFLOW_RAM /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/clk
171 add wave -noupdate -group DATAFLOW_RAM -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(0) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(8) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(9) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(10) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(11) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(12) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(13) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(14) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(15) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(16) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(17) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(18) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(19) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(20) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(21) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(22) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(23) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(24) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(25) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(26) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(27) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(28) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(29) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(30) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(31) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(32) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(33) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(34) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(35) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(36) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(37) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(38) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(39) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(40) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(41) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(42) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(43) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(44) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(45) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(46) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(47) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(48) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(49) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(50) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(51) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(52) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(53) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(54) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(55) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(56) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(57) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(58) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(59) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(60) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(61) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(62) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(63) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(64) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(65) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(66) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(67) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(68) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(69) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(70) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(71) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(72) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(73) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(74) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(75) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(76) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(77) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(78) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(79) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(80) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(81) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(82) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(83) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(84) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(85) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(86) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(87) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(88) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(89) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(90) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(91) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(92) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(93) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(94) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(95) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(96) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(97) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(98) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(99) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(100) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(101) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(102) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(103) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(104) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(105) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(106) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(107) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(108) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(109) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(110) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(111) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(112) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(113) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(114) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(115) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(116) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(117) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(118) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(119) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(120) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(121) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(122) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(123) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(124) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(125) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(126) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(127) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(128) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(129) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(130) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(131) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(132) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(133) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(134) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(135) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(136) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(137) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(138) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(139) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(140) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(141) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(142) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(143) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(144) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(145) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(146) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(147) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(148) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(149) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(150) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(151) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(152) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(153) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(154) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(155) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(156) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(157) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(158) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(159) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(160) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(161) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(162) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(163) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(164) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(165) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(166) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(167) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(168) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(169) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(170) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(171) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(172) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(173) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(174) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(175) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(176) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(177) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(178) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(179) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(180) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(181) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(182) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(183) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(184) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(185) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(186) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(187) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(188) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(189) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(190) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(191) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(192) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(193) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(194) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(195) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(196) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(197) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(198) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(199) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(200) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(201) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(202) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(203) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(204) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(205) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(206) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(207) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(208) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(209) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(210) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(211) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(212) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(213) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(214) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(215) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(216) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(217) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(218) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(219) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(220) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(221) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(222) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(223) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(224) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(225) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(226) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(227) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(228) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(229) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(230) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(231) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(232) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(233) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(234) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(235) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(236) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(237) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(238) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(239) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(240) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(241) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(242) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(243) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(244) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(245) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(246) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(247) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(248) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(249) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(250) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(251) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(252) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(253) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(254) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray(255) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/memcel/ramblk/ramarray
172 add wave -noupdate -group DATAFLOW_RAM -group COUNTER -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/counter
173 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_rst
174 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr_add1
175 add wave -noupdate -group DATAFLOW_RAM -group COUNTER /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr_previous
176 add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_write
177 add wave -noupdate -group DATAFLOW_RAM -group WRITE /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wen
178 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/waddr
179 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/wd
180 add wave -noupdate -group DATAFLOW_RAM -group WRITE -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_in
181 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ram_read
182 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/ren
183 add wave -noupdate -group DATAFLOW_RAM -group READ -radix unsigned /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/raddr
184 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/rd
185 add wave -noupdate -group DATAFLOW_RAM -group READ /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/ram_ctrlr_v2_1/sample_out
186 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in_val
187 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_in
188 add wave -noupdate -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val
189 add wave -noupdate -radix decimal -subitemconfig {/tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(7) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(6) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(5) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(3) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(2) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(1) {-height 15 -radix decimal} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(0) {-height 15 -radix decimal}} /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out
190 add wave -noupdate -height 15 -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out(4)
191 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clk
192 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/reset
193 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac
194 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mac_mul_add
195 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1
196 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2
197 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/res
198 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add
199 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/mult
200 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout
201 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderina
202 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderinb
203 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/adderout
204 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel
205 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d_resz
206 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d_resz
207 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel
208 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/add_d
209 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op1_d
210 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/op2_d
211 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/multout_d
212 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmuxsel_d
213 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d
214 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/macmux2sel_d_d
215 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d
216 add wave -noupdate -group MAC -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/alu_1/arith/macinst/clr_mac_d_d
217 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_val
218 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/sample_out_rot
219 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_control_1/iir_cel_state
220 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/iir_cel_ctrlr_v2_dataflow_1/sample_out
221 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s
222 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_val_s2
223 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_rot_s
224 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s
225 add wave -noupdate -expand -group OUTPUT -radix decimal /tb_data_acquisition/top_data_acquisition_1/iir_cel_ctrlr_v2_1/sample_out_s2
226 TreeUpdate [SetDefaultTree]
33 TreeUpdate [SetDefaultTree]
227 WaveRestoreCursors {{Cursor 1} {4520000 ps} 0}
34 WaveRestoreCursors {{Cursor 1} {0 ps} 0}
228 configure wave -namecolwidth 677
35 configure wave -namecolwidth 430
229 configure wave -valuecolwidth 100
36 configure wave -valuecolwidth 100
230 configure wave -justifyvalue left
37 configure wave -justifyvalue left
231 configure wave -signalnamewidth 0
38 configure wave -signalnamewidth 0
@@ -239,4 +46,4 configure wave -griddelta 40
239 configure wave -timeline 0
46 configure wave -timeline 0
240 configure wave -timelineunits ns
47 configure wave -timelineunits ns
241 update
48 update
242 WaveRestoreZoom {2722930 ps} {6210191 ps}
49 WaveRestoreZoom {0 ps} {754717 ps}
Show file before | Show file after | Hide comments
@@ -1,212 +1,213
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 use ieee.numeric_std.all;
24 use ieee.numeric_std.all;
25 library grlib;
25 library grlib;
26 use grlib.amba.all;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
28 use grlib.devices.all;
29 library lpp;
29 library lpp;
30 use lpp.iir_filter.all;
30 use lpp.iir_filter.all;
31 use lpp.general_purpose.all;
31 use lpp.general_purpose.all;
32 use lpp.lpp_amba.all;
32 use lpp.lpp_amba.all;
33 use lpp.apb_devices_list.all;
33 use lpp.apb_devices_list.all;
34
34
35 entity APB_IIR_CEL is
35 entity APB_IIR_CEL is
36 generic (
36 generic (
37 tech : integer := 0;
37 tech : integer := 0;
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Sample_SZ : integer := 16;
43 Sample_SZ : integer := 16;
44 ChanelsCount : integer := 1;
44 ChanelsCount : integer := 1;
45 Coef_SZ : integer := 9;
45 Coef_SZ : integer := 9;
46 CoefCntPerCel: integer := 6;
46 CoefCntPerCel: integer := 6;
47 Cels_count : integer := 5;
47 Cels_count : integer := 5;
48 virgPos : integer := 3;
48 virgPos : integer := 3;
49 Mem_use : integer := use_RAM
49 Mem_use : integer := use_RAM
50 );
50 );
51 port (
51 port (
52 rst : in std_logic;
52 rst : in std_logic;
53 clk : in std_logic;
53 clk : in std_logic;
54 apbi : in apb_slv_in_type;
54 apbi : in apb_slv_in_type;
55 apbo : out apb_slv_out_type;
55 apbo : out apb_slv_out_type;
56 sample_clk : in std_logic;
56 sample_clk : in std_logic;
57 sample_clk_out : out std_logic;
57 sample_clk_out : out std_logic;
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
58 sample_in : in samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
59 sample_out : out samplT(ChanelsCount-1 downto 0,Sample_SZ-1 downto 0);
60 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
60 CoefsInitVal : in std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (others => '1')
61 );
61 );
62 end;
62 end;
63
63
64
64
65 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
65 architecture AR_APB_IIR_CEL of APB_IIR_CEL is
66
66
67 constant REVISION : integer := 1;
67 constant REVISION : integer := 1;
68
68
69 constant pconfig : apb_config_type := (
69 constant pconfig : apb_config_type := (
70 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
70 0 => ahb_device_reg (VENDOR_LPP, LPP_IIR_CEL_FILTER, 0, REVISION, 0),
71 1 => apb_iobar(paddr, pmask));
71 1 => apb_iobar(paddr, pmask));
72
72
73
73
74
74
75 type FILTERreg is record
75 type FILTERreg is record
76 regin : in_IIR_CEL_reg;
76 regin : in_IIR_CEL_reg;
77 regout : out_IIR_CEL_reg;
77 regout : out_IIR_CEL_reg;
78 end record;
78 end record;
79
79
80 signal Rdata : std_logic_vector(31 downto 0);
80 signal Rdata : std_logic_vector(31 downto 0);
81 signal r : FILTERreg;
81 signal r : FILTERreg;
82 signal filter_reset : std_logic:='0';
82 signal filter_reset : std_logic:='0';
83 signal smp_cnt : integer :=0;
83 signal smp_cnt : integer :=0;
84 signal sample_clk_out_R : std_logic;
84 signal sample_clk_out_R : std_logic;
85 signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
85 signal RawCoefs : std_logic_vector(((Coef_SZ*CoefCntPerCel*Cels_count)-1) downto 0);
86
86
87 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
87 type CoefCelT is array(0 to (CoefCntPerCel/2)-1) of std_logic_vector(Coef_SZ-1 downto 0);
88 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
88 type CoefTblT is array(0 to Cels_count-1) of CoefCelT;
89
89
90 type CoefsRegT is record
90 type CoefsRegT is record
91 numCoefs : CoefTblT;
91 numCoefs : CoefTblT;
92 denCoefs : CoefTblT;
92 denCoefs : CoefTblT;
93 end record;
93 end record;
94
94
95 signal CoefsReg : CoefsRegT;
95 signal CoefsReg : CoefsRegT;
96 signal CoefsReg_d : CoefsRegT;
96 signal CoefsReg_d : CoefsRegT;
97
97
98
98
99 begin
99 begin
100
100
101 filter_reset <= rst and r.regin.config(0);
101 filter_reset <= rst and r.regin.config(0);
102 sample_clk_out <= sample_clk_out_R;
102 sample_clk_out <= sample_clk_out_R;
103 --
103 --
104 filter : IIR_CEL_FILTER
104 filter : IIR_CEL_FILTER
105 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
105 generic map(tech,Sample_SZ,ChanelsCount,Coef_SZ,CoefCntPerCel,Cels_count,Mem_use)
106 port map(
106 port map(
107 reset => filter_reset,
107 reset => filter_reset,
108 clk => clk,
108 clk => clk,
109 sample_clk => sample_clk,
109 sample_clk => sample_clk,
110 regs_in => r.regin,
110 regs_in => r.regin,
111 regs_out => r.regout,
111 regs_out => r.regout,
112 sample_in => sample_in,
112 sample_in => sample_in,
113 sample_out => sample_out,
113 sample_out => sample_out,
114 coefs => RawCoefs
114 coefs => RawCoefs
115 );
115 );
116
116
117 process(rst,sample_clk)
117 process(rst,sample_clk)
118 begin
118 begin
119 if rst = '0' then
119 if rst = '0' then
120 smp_cnt <= 0;
120 smp_cnt <= 0;
121 sample_clk_out_R <= '0';
121 sample_clk_out_R <= '0';
122 elsif sample_clk'event and sample_clk = '1' then
122 elsif sample_clk'event and sample_clk = '1' then
123 if smp_cnt = 1 then
123 if smp_cnt = 1 then
124 smp_cnt <= 0;
124 smp_cnt <= 0;
125 sample_clk_out_R <= not sample_clk_out_R;
125 sample_clk_out_R <= not sample_clk_out_R;
126 else
126 else
127 smp_cnt <= smp_cnt +1;
127 smp_cnt <= smp_cnt +1;
128 end if;
128 end if;
129 end if;
129 end if;
130 end process;
130 end process;
131
131
132
132
133 coefsConnectL0: for z in 0 to Cels_count-1 generate
133 coefsConnectL0: for z in 0 to Cels_count-1 generate
134 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
134 coefsConnectL1: for y in 0 to (CoefCntPerCel/2)-1 generate
135 RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
135 RawCoefs(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) ) <= CoefsReg_d.numCoefs(z)(y)(Coef_SZ-1 downto 0);
136 RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
136 RawCoefs(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ)) <= CoefsReg_d.denCoefs(z)(y)(Coef_SZ-1 downto 0);
137 end generate;
137 end generate;
138 end generate;
138 end generate;
139
139
140
140
141 process(rst,clk)
141 process(rst,clk)
142 begin
142 begin
143 if rst = '0' then
143 if rst = '0' then
144 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
144 r.regin.virgPos <= std_logic_vector(to_unsigned(virgPos,5));
145 coefsRstL0: for z in 0 to Cels_count-1 loop
145 coefsRstL0: for z in 0 to Cels_count-1 loop
146 coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
146 coefsRstL1: for y in 0 to (CoefCntPerCel/2)-1 loop
147 CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
147 CoefsReg.numCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y)+1)*Coef_SZ)-1) downto (((z*CoefCntPerCel+y))*Coef_SZ) );
148 CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
148 CoefsReg.denCoefs(z)(y) <= CoefsInitVal(((((z*CoefCntPerCel+y+(CoefCntPerCel/2))+1)*Coef_SZ)-1) downto ((z*CoefCntPerCel+y+(CoefCntPerCel/2))*Coef_SZ));
149 end loop;
149 end loop;
150 end loop;
150 end loop;
151 elsif clk'event and clk = '1' then
151 elsif clk'event and clk = '1' then
152 CoefsReg_d <= CoefsReg;
152 CoefsReg_d <= CoefsReg;
153
153
154 --APB Write OP
154 --APB Write OP
155 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
155 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
156 if apbi.paddr(7 downto 2) = "000000" then
156 if apbi.paddr(7 downto 2) = "000000" then
157 r.regin.config(0) <= apbi.pwdata(0);
157 r.regin.config(0) <= apbi.pwdata(0);
158 elsif apbi.paddr(7 downto 2) = "000001" then
158 elsif apbi.paddr(7 downto 2) = "000001" then
159 r.regin.virgPos <= apbi.pwdata(4 downto 0);
159 r.regin.virgPos <= apbi.pwdata(4 downto 0);
160 else
160 else
161 for i in 0 to Cels_count-1 loop
161 for i in 0 to Cels_count-1 loop
162 for j in 0 to (CoefCntPerCel/2) - 1 loop
162 for j in 0 to (CoefCntPerCel/2) - 1 loop
163 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
163 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
164 CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
164 CoefsReg.numCoefs(i)(j) <= apbi.pwdata(Coef_SZ-1 downto 0);
165 CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
165 CoefsReg.denCoefs(i)(j) <= apbi.pwdata((Coef_SZ+15) downto 16);
166 end if;
166 end if;
167 end loop;
167 end loop;
168 end loop;
168 end loop;
169 end if;
169 end if;
170 end if;
170 end if;
171
171
172 --APB READ OP
172 --APB READ OP
173 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
173 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
174 if apbi.paddr(7 downto 2) = "000000" then
174 if apbi.paddr(7 downto 2) = "000000" then
175 Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
175 Rdata(7 downto 0) <= std_logic_vector(TO_UNSIGNED(ChanelsCount,8));
176 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
176 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Sample_SZ,8));
177 Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
177 Rdata(23 downto 16) <= std_logic_vector(TO_UNSIGNED(CoefCntPerCel,8));
178 Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
178 Rdata(31 downto 24) <= std_logic_vector(TO_UNSIGNED(Cels_count,8));
179 elsif apbi.paddr(7 downto 2) = "000001" then
179 elsif apbi.paddr(7 downto 2) = "000001" then
180 Rdata(4 downto 0) <= r.regin.virgPos;
180 Rdata(4 downto 0) <= r.regin.virgPos;
181 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
181 Rdata(15 downto 8) <= std_logic_vector(TO_UNSIGNED(Coef_SZ,8));
182 Rdata(7 downto 5) <= (others => '0');
182 Rdata(7 downto 5) <= (others => '0');
183 Rdata(31 downto 16) <= (others => '0');
183 Rdata(31 downto 16) <= (others => '0');
184 else
184 else
185 for i in 0 to Cels_count-1 loop
185 for i in 0 to Cels_count-1 loop
186 for j in 0 to (CoefCntPerCel/2) - 1 loop
186 for j in 0 to (CoefCntPerCel/2) - 1 loop
187 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
187 if apbi.paddr(9 downto 2) = std_logic_vector(TO_UNSIGNED((2+ (i*(CoefCntPerCel/2))+j),8)) then
188 Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
188 Rdata(Coef_SZ-1 downto 0) <= CoefsReg_d.numCoefs(i)(j);
189 Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
189 Rdata((Coef_SZ+15) downto 16) <= CoefsReg_d.denCoefs(i)(j);
190 end if;
190 end if;
191 end loop;
191 end loop;
192 end loop;
192 end loop;
193 end if;
193 end if;
194 end if;
194 end if;
195 end if;
195 end if;
196 apbo.pconfig <= pconfig;
196 apbo.pconfig <= pconfig;
197 end process;
197 end process;
198
198
199 apbo.prdata <= Rdata when apbi.penable = '1' ;
199 apbo.prdata <= Rdata when apbi.penable = '1' ;
200
200
201 -- pragma translate_off
201 -- pragma translate_off
202 bootmsg : report_version
202 bootmsg : report_version
203 generic map ("apb IIR filter" & tost(pindex) &
203 generic map ("apb IIR filter" & tost(pindex) &
204 ": IIR filter rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
204 ": IIR filter rev " & tost(REVISION)&
205 ", irq " & tost(pirq));
205 --", fifo " & tost(fifosize) &
206 -- pragma translate_on
206 ", irq " & tost(pirq));
207
207 -- pragma translate_on
208
208
209
209
210
210
211 end ar_APB_IIR_CEL;
211
212
212 end ar_APB_IIR_CEL;
213
Show file before | Show file after | Hide comments
@@ -63,7 +63,7 begin
63 --==============================================================
63 --==============================================================
64 --=========================A L U================================
64 --=========================A L U================================
65 --==============================================================
65 --==============================================================
66 ALU1 : entity ALU
66 ALU1 : ALU
67 generic map(
67 generic map(
68 Arith_en => 1,
68 Arith_en => 1,
69 Logic_en => 0,
69 Logic_en => 0,
Show file before | Show file after | Hide comments
@@ -196,7 +196,8 BEGIN
196 GENERIC MAP (
196 GENERIC MAP (
197 Arith_en => 1,
197 Arith_en => 1,
198 Input_SZ_1 => Sample_SZ,
198 Input_SZ_1 => Sample_SZ,
199 Input_SZ_2 => Coef_SZ)
199 Input_SZ_2 => Coef_SZ,
200 COMP_EN => 1)
200 PORT MAP (
201 PORT MAP (
201 clk => clk,
202 clk => clk,
202 reset => rstn,
203 reset => rstn,
Show file before | Show file after | Hide comments
@@ -72,7 +72,7 BEGIN
72 memCEL : IF Mem_use = use_CEL GENERATE
72 memCEL : IF Mem_use = use_CEL GENERATE
73 WEN <= NOT ram_write;
73 WEN <= NOT ram_write;
74 REN <= NOT ram_read;
74 REN <= NOT ram_read;
75 RAMblk : RAM_CEL
75 RAMblk : RAM_CEL_N
76 GENERIC MAP(Input_SZ_1)
76 GENERIC MAP(Input_SZ_1)
77 PORT MAP(
77 PORT MAP(
78 WD => WD,
78 WD => WD,
Show file before | Show file after | Hide comments
@@ -216,6 +216,18 PACKAGE iir_filter IS
216 RWCLK, RESET : IN STD_LOGIC);
216 RWCLK, RESET : IN STD_LOGIC);
217 END COMPONENT;
217 END COMPONENT;
218
218
219 COMPONENT RAM_CEL_N
220 GENERIC (
221 size : INTEGER);
222 PORT (
223 WD : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
224 RD : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0);
225 WEN, REN : IN STD_LOGIC;
226 WADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
227 RADDR : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
228 RWCLK, RESET : IN STD_LOGIC);
229 END COMPONENT;
230
219 COMPONENT IIR_CEL_FILTER IS
231 COMPONENT IIR_CEL_FILTER IS
220 GENERIC(
232 GENERIC(
221 tech : INTEGER := 0;
233 tech : INTEGER := 0;
Show file before | Show file after | Hide comments
@@ -32,7 +32,9 generic(
32 Arith_en : integer := 1;
32 Arith_en : integer := 1;
33 Logic_en : integer := 1;
33 Logic_en : integer := 1;
34 Input_SZ_1 : integer := 16;
34 Input_SZ_1 : integer := 16;
35 Input_SZ_2 : integer := 16);
35 Input_SZ_2 : integer := 16;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
37 );
36 port(
38 port(
37 clk : in std_logic; --! Horloge du composant
39 clk : in std_logic; --! Horloge du composant
38 reset : in std_logic; --! Reset general du composant
40 reset : in std_logic; --! Reset general du composant
@@ -56,8 +58,8 begin
56
58
57 arith : if Arith_en = 1 generate
59 arith : if Arith_en = 1 generate
58 MACinst : MAC
60 MACinst : MAC
59 generic map(Input_SZ_1,Input_SZ_2)
61 generic map(Input_SZ_1,Input_SZ_2,COMP_EN)
60 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
62 port map(clk,reset,ctrl(2),ctrl(1 downto 0),comp,OP1,OP2,RES);
61 end generate;
63 end generate;
62
64
63 end architecture; No newline at end of file
65 end architecture;
Show file before | Show file after | Hide comments
@@ -32,7 +32,8 USE lpp.general_purpose.ALL;
32 ENTITY MAC IS
32 ENTITY MAC IS
33 GENERIC(
33 GENERIC(
34 Input_SZ_A : INTEGER := 8;
34 Input_SZ_A : INTEGER := 8;
35 Input_SZ_B : INTEGER := 8
35 Input_SZ_B : INTEGER := 8;
36 COMP_EN : INTEGER := 0 -- 1 => No Comp
36
37
37 );
38 );
38 PORT(
39 PORT(
@@ -52,35 +53,35 END MAC;
52
53
53 ARCHITECTURE ar_MAC OF MAC IS
54 ARCHITECTURE ar_MAC OF MAC IS
54
55
55 signal add,mult : std_logic;
56 SIGNAL add, mult : STD_LOGIC;
56 signal MULTout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
57 SIGNAL MULTout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
57
58
58 signal ADDERinA : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
59 SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
59 signal ADDERinB : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
60 SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
60 signal ADDERout : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
61 SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
61
62
62 signal MACMUXsel : std_logic;
63 SIGNAL MACMUXsel : STD_LOGIC;
63 signal OP1_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
64 SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
64 signal OP2_2C_D_Resz : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
65 SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
65
66
66 signal OP1_2C : std_logic_vector(Input_SZ_A-1 downto 0);
67 SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
67 signal OP2_2C : std_logic_vector(Input_SZ_B-1 downto 0);
68 SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
68
69
69 signal MACMUX2sel : std_logic;
70 SIGNAL MACMUX2sel : STD_LOGIC;
70
71
71 signal add_D : std_logic;
72 SIGNAL add_D : STD_LOGIC;
72 signal OP1_2C_D : std_logic_vector(Input_SZ_A-1 downto 0);
73 SIGNAL OP1_2C_D : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
73 signal OP2_2C_D : std_logic_vector(Input_SZ_B-1 downto 0);
74 SIGNAL OP2_2C_D : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
74 signal MULTout_D : std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0);
75 SIGNAL MULTout_D : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
75 signal MACMUXsel_D : std_logic;
76 SIGNAL MACMUXsel_D : STD_LOGIC;
76 signal MACMUX2sel_D : std_logic;
77 SIGNAL MACMUX2sel_D : STD_LOGIC;
77 signal MACMUX2sel_D_D : std_logic;
78 SIGNAL MACMUX2sel_D_D : STD_LOGIC;
78 signal clr_MAC_D : std_logic;
79 SIGNAL clr_MAC_D : STD_LOGIC;
79 signal clr_MAC_D_D : std_logic;
80 SIGNAL clr_MAC_D_D : STD_LOGIC;
80 signal MAC_MUL_ADD_2C_D : std_logic_vector(1 downto 0);
81 SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
81
82
82 SIGNAL load_mult_result : STD_LOGIC;
83 SIGNAL load_mult_result : STD_LOGIC;
83 SIGNAL load_mult_result_D : STD_LOGIC;
84 SIGNAL load_mult_result_D : STD_LOGIC;
84
85
85 BEGIN
86 BEGIN
86
87
@@ -113,25 +114,25 BEGIN
113 Input_SZ_A => Input_SZ_A,
114 Input_SZ_A => Input_SZ_A,
114 Input_SZ_B => Input_SZ_B
115 Input_SZ_B => Input_SZ_B
115 )
116 )
116 port map(
117 PORT MAP(
117 clk => clk,
118 clk => clk,
118 reset => reset,
119 reset => reset,
119 mult => mult,
120 mult => mult,
120 OP1 => OP1_2C,
121 OP1 => OP1_2C,
121 OP2 => OP2_2C,
122 OP2 => OP2_2C,
122 RES => MULTout
123 RES => MULTout
123 );
124 );
124 --==============================================================
125 --==============================================================
125
126
126 PROCESS (clk, reset)
127 PROCESS (clk, reset)
127 BEGIN -- PROCESS
128 BEGIN -- PROCESS
128 IF reset = '0' THEN -- asynchronous reset (active low)
129 IF reset = '0' THEN -- asynchronous reset (active low)
129 load_mult_result_D <= '0';
130 load_mult_result_D <= '0';
130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
131 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
131 load_mult_result_D <= load_mult_result;
132 load_mult_result_D <= load_mult_result;
132 END IF;
133 END IF;
133 END PROCESS;
134 END PROCESS;
134
135
135 --==============================================================
136 --==============================================================
136 --======================A D D E R ==============================
137 --======================A D D E R ==============================
137 --==============================================================
138 --==============================================================
@@ -154,32 +155,38 port map(
154 --==============================================================
155 --==============================================================
155 --===================TWO COMPLEMENTERS==========================
156 --===================TWO COMPLEMENTERS==========================
156 --==============================================================
157 --==============================================================
157 TWO_COMPLEMENTER1 : TwoComplementer
158 gen_comp : IF COMP_EN = 0 GENERATE
158 generic map(
159 TWO_COMPLEMENTER1 : TwoComplementer
159 Input_SZ => Input_SZ_A
160 GENERIC MAP(
160 )
161 Input_SZ => Input_SZ_A
161 port map(
162 )
162 clk => clk,
163 PORT MAP(
163 reset => reset,
164 clk => clk,
164 clr => clr_MAC,
165 reset => reset,
165 TwoComp => Comp_2C(0),
166 clr => clr_MAC,
166 OP => OP1,
167 TwoComp => Comp_2C(0),
167 RES => OP1_2C
168 OP => OP1,
168 );
169 RES => OP1_2C
170 );
169
171
170
172 TWO_COMPLEMENTER2 : TwoComplementer
171 TWO_COMPLEMENTER2 : TwoComplementer
173 GENERIC MAP(
172 generic map(
174 Input_SZ => Input_SZ_B
173 Input_SZ => Input_SZ_B
175 )
174 )
176 PORT MAP(
175 port map(
177 clk => clk,
176 clk => clk,
178 reset => reset,
177 reset => reset,
179 clr => clr_MAC,
178 clr => clr_MAC,
180 TwoComp => Comp_2C(1),
179 TwoComp => Comp_2C(1),
181 OP => OP2,
180 OP => OP2,
182 RES => OP2_2C
181 RES => OP2_2C
183 );
182 );
184 END GENERATE gen_comp;
185
186 no_gen_comp : IF COMP_EN = 1 GENERATE
187 OP2_2C <= OP2;
188 OP1_2C <= OP1;
189 END GENERATE no_gen_comp;
183 --==============================================================
190 --==============================================================
184
191
185 clr_MACREG1 : MAC_REG
192 clr_MACREG1 : MAC_REG
@@ -200,24 +207,24 port map(
200 Q(0) => add_D
207 Q(0) => add_D
201 );
208 );
202
209
203 OP1REG : MAC_REG
210 OP1REG : MAC_REG
204 generic map(size => Input_SZ_A)
211 GENERIC MAP(size => Input_SZ_A)
205 port map(
212 PORT MAP(
206 reset => reset,
213 reset => reset,
207 clk => clk,
214 clk => clk,
208 D => OP1_2C,
215 D => OP1_2C,
209 Q => OP1_2C_D
216 Q => OP1_2C_D
210 );
217 );
211
218
212
219
213 OP2REG : MAC_REG
220 OP2REG : MAC_REG
214 generic map(size => Input_SZ_B)
221 GENERIC MAP(size => Input_SZ_B)
215 port map(
222 PORT MAP(
216 reset => reset,
223 reset => reset,
217 clk => clk,
224 clk => clk,
218 D => OP2_2C,
225 D => OP2_2C,
219 Q => OP2_2C_D
226 Q => OP2_2C_D
220 );
227 );
221
228
222 MULToutREG : MAC_REG
229 MULToutREG : MAC_REG
223 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
230 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
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@@ -83,7 +83,8 PACKAGE general_purpose IS
83 Arith_en : INTEGER := 1;
83 Arith_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
84 Logic_en : INTEGER := 1;
85 Input_SZ_1 : INTEGER := 16;
85 Input_SZ_1 : INTEGER := 16;
86 Input_SZ_2 : INTEGER := 9
86 Input_SZ_2 : INTEGER := 9;
87 COMP_EN : INTEGER := 0 -- 1 => No Comp
87
88
88 );
89 );
89 PORT(
90 PORT(
@@ -110,7 +111,8 Constant ctrl_CLRMAC : std_logic_vector(
110 COMPONENT MAC IS
111 COMPONENT MAC IS
111 GENERIC(
112 GENERIC(
112 Input_SZ_A : INTEGER := 8;
113 Input_SZ_A : INTEGER := 8;
113 Input_SZ_B : INTEGER := 8
114 Input_SZ_B : INTEGER := 8;
115 COMP_EN : INTEGER := 0 -- 1 => No Comp
114 );
116 );
115 PORT(
117 PORT(
116 clk : IN STD_LOGIC;
118 clk : IN STD_LOGIC;
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@@ -18,97 +18,180
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 library IEEE;
22 -- MODIFIED by Jean-christophe PELLION
23 use IEEE.STD_LOGIC_1164.ALL;
23 -- jean-christophe.pellion@lpp.polytechnique.fr
24 library lpp;
24 -------------------------------------------------------------------------------
25 use lpp.lpp_ad_conv.all;
25 LIBRARY IEEE;
26 use lpp.general_purpose.Clk_divider;
26 USE IEEE.STD_LOGIC_1164.ALL;
27
27 LIBRARY lpp;
28 --! \brief AD7688 driver, generates all needed signal to drive this ADC.
28 USE lpp.lpp_ad_conv.ALL;
29 --!
29 USE lpp.general_purpose.SYNC_FF;
30 --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr
31
30
32 entity AD7688_drvr is
31 ENTITY AD7688_drvr IS
33 generic(
32 GENERIC(
34 ChanelCount :integer; --! Number of ADC you whant to drive
33 ChanelCount : INTEGER;
35 clkkHz :integer --! System clock frequency in kHz usefull to generate some pulses with good width.
34 ncycle_cnv_high : INTEGER := 79;
36 );
35 ncycle_cnv : INTEGER := 500);
37 Port(
36 PORT (
38 clk : in STD_LOGIC; --! System clock
37 -- CONV --
39 rstn : in STD_LOGIC; --! System reset
38 cnv_clk : IN STD_LOGIC;
40 enable : in std_logic; --! Negative enable
39 cnv_rstn : IN STD_LOGIC;
41 smplClk : in STD_LOGIC; --! Sampling clock
40 cnv_run : IN STD_LOGIC;
42 DataReady : out std_logic; --! New sample available
41 cnv : OUT STD_LOGIC;
43 smpout : out Samples_out(ChanelCount-1 downto 0); --! Samples
44 AD_in : in AD7688_in(ChanelCount-1 downto 0); --! Input signals for ADC see lpp.lpp_ad_conv
45 AD_out : out AD7688_out --! Output signals for ADC see lpp.lpp_ad_conv
46 );
47 end AD7688_drvr;
48
49 architecture ar_AD7688_drvr of AD7688_drvr is
50
51 constant convTrigger : integer:= clkkHz*16/10000; --tconv = 1.6µs
52
53 signal i : integer range 0 to convTrigger :=0;
54 signal clk_int : std_logic;
55 signal clk_int_inv : std_logic;
56 signal smplClk_reg : std_logic;
57 signal cnv_int : std_logic;
58 signal reset : std_logic;
59
42
60 begin
43 -- DATA --
61
44 clk : IN STD_LOGIC;
62 clkdiv: if clkkHz>=66000 generate
45 rstn : IN STD_LOGIC;
63 clkdivider: entity work.Clk_divider
46 sck : OUT STD_LOGIC;
64 generic map(clkkHz*1000,60000000)
47 sdo : IN STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
65 Port map( clk ,reset,clk_int);
66 end generate;
67
48
68 clknodiv: if clkkHz<66000 generate
49 sample : OUT Samples(ChanelCount-1 DOWNTO 0);
69 nodiv: clk_int <= clk;
50 sample_val : OUT STD_LOGIC
70 end generate;
51 );
71
52 END AD7688_drvr;
72 clk_int_inv <= not clk_int;
73
74 AD_out.CNV <= cnv_int;
75 AD_out.SCK <= clk_int;
76 reset <= rstn and enable;
77
53
78 sckgen: process(clk,reset)
54 ARCHITECTURE ar_AD7688_drvr OF AD7688_drvr IS
79 begin
55
80 if reset = '0' then
56 COMPONENT SYNC_FF
81 i <= 0;
57 GENERIC (
82 cnv_int <= '0';
58 NB_FF_OF_SYNC : INTEGER);
83 smplClk_reg <= '0';
59 PORT (
84 elsif clk'event and clk = '1' then
60 clk : IN STD_LOGIC;
85 if smplClk = '1' and smplClk_reg = '0' then
61 rstn : IN STD_LOGIC;
86 if i = convTrigger then
62 A : IN STD_LOGIC;
87 smplClk_reg <= '1';
63 A_sync : OUT STD_LOGIC);
88 i <= 0;
64 END COMPONENT;
89 cnv_int <= '0';
90 else
91 i <= i+1;
92 cnv_int <= '1';
93 end if;
94 elsif smplClk = '0' and smplClk_reg = '1' then
95 smplClk_reg <= '0';
96 end if;
97 end if;
98 end process;
99
65
100
66
67 SIGNAL cnv_cycle_counter : INTEGER;
68 SIGNAL cnv_s : STD_LOGIC;
69 SIGNAL cnv_sync : STD_LOGIC;
70 SIGNAL cnv_sync_r : STD_LOGIC;
71 SIGNAL cnv_done : STD_LOGIC;
72 SIGNAL sample_bit_counter : INTEGER;
73 SIGNAL shift_reg : Samples(ChanelCount-1 DOWNTO 0);
101
74
102 spidrvr: entity work.AD7688_spi_if
75 SIGNAL cnv_run_sync : STD_LOGIC;
103 generic map(ChanelCount)
76
104 Port map(clk_int_inv,reset,cnv_int,DataReady,AD_in,smpout);
77 BEGIN
78 -----------------------------------------------------------------------------
79 -- CONV
80 -----------------------------------------------------------------------------
81 PROCESS (cnv_clk, cnv_rstn)
82 BEGIN -- PROCESS
83 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
84 cnv_cycle_counter <= 0;
85 cnv_s <= '0';
86 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
87 IF cnv_run = '1' THEN
88 IF cnv_cycle_counter < ncycle_cnv THEN
89 cnv_cycle_counter <= cnv_cycle_counter +1;
90 IF cnv_cycle_counter < ncycle_cnv_high THEN
91 cnv_s <= '1';
92 ELSE
93 cnv_s <= '0';
94 END IF;
95 ELSE
96 cnv_s <= '1';
97 cnv_cycle_counter <= 0;
98 END IF;
99 ELSE
100 cnv_s <= '0';
101 cnv_cycle_counter <= 0;
102 END IF;
103 END IF;
104 END PROCESS;
105
105
106 cnv <= cnv_s;
107
108 -----------------------------------------------------------------------------
106
109
107
110
108 end ar_AD7688_drvr;
111 -----------------------------------------------------------------------------
112 -- SYNC CNV
113 -----------------------------------------------------------------------------
114
115 SYNC_FF_cnv : SYNC_FF
116 GENERIC MAP (
117 NB_FF_OF_SYNC => 2)
118 PORT MAP (
119 clk => clk,
120 rstn => rstn,
121 A => cnv_s,
122 A_sync => cnv_sync);
109
123
124 PROCESS (clk, rstn)
125 BEGIN
126 IF rstn = '0' THEN
127 cnv_sync_r <= '0';
128 cnv_done <= '0';
129 ELSIF clk'EVENT AND clk = '1' THEN
130 cnv_sync_r <= cnv_sync;
131 cnv_done <= (NOT cnv_sync) AND cnv_sync_r;
132 END IF;
133 END PROCESS;
134
135 -----------------------------------------------------------------------------
136
137 SYNC_FF_run : SYNC_FF
138 GENERIC MAP (
139 NB_FF_OF_SYNC => 2)
140 PORT MAP (
141 clk => clk,
142 rstn => rstn,
143 A => cnv_run,
144 A_sync => cnv_run_sync);
110
145
111
146
112
147
148 -----------------------------------------------------------------------------
149 -- DATA
150 -----------------------------------------------------------------------------
151 PROCESS (clk, rstn)
152 BEGIN -- PROCESS
153 IF rstn = '0' THEN
154 FOR l IN 0 TO ChanelCount-1 LOOP
155 shift_reg(l) <= (OTHERS => '0');
156 END LOOP;
157 sample_bit_counter <= 0;
158 sample_val <= '0';
159 SCK <= '1';
160 ELSIF clk'EVENT AND clk = '1' THEN
161
162 IF cnv_run_sync = '0' THEN
163 sample_bit_counter <= 0;
164 ELSIF cnv_done = '1' THEN
165 sample_bit_counter <= 1;
166 ELSIF sample_bit_counter > 0 AND sample_bit_counter < 32 THEN
167 sample_bit_counter <= sample_bit_counter + 1;
168 END IF;
113
169
170 IF (sample_bit_counter MOD 2) = 1 THEN
171 FOR l IN 0 TO ChanelCount-1 LOOP
172 --shift_reg(l)(15) <= sdo(l);
173 --shift_reg(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
174 shift_reg(l)(0) <= sdo(l);
175 shift_reg(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
176 END LOOP;
177 SCK <= '0';
178 ELSE
179 SCK <= '1';
180 END IF;
114
181
182 IF sample_bit_counter = 31 THEN
183 sample_val <= '1';
184 FOR l IN 0 TO ChanelCount-1 LOOP
185 --sample(l)(15) <= sdo(l);
186 --sample(l)(14 DOWNTO 0) <= shift_reg(l)(15 DOWNTO 1);
187 sample(l)(0) <= sdo(l);
188 sample(l)(15 DOWNTO 1) <= shift_reg(l)(14 DOWNTO 0);
189 END LOOP;
190 ELSE
191 sample_val <= '0';
192 END IF;
193 END IF;
194 END PROCESS;
195
196 END ar_AD7688_drvr;
197
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@@ -61,10 +61,10 BEGIN -- beh
61 reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
61 reg <= conv_std_logic_vector(integer(REAL(amplitude) * SIN(MATH_2_PI*REAL(n)/REAL(freq))) , 16);
62 END IF;
62 END IF;
63 ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
63 ELSIF sck'EVENT AND sck = '0' THEN -- rising clock edge
64 reg(15) <= 'X';
64 reg(0) <= 'X';
65 reg(14 DOWNTO 0) <= reg(15 DOWNTO 1);
65 reg(15 DOWNTO 1) <= reg(14 DOWNTO 0);
66 END IF;
66 END IF;
67 END PROCESS;
67 END PROCESS;
68 sdo <= reg(0);
68 sdo <= reg(15);
69
69
70 END beh;
70 END beh;
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@@ -50,7 +50,7 PACKAGE lpp_ad_conv IS
50
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
52
53 COMPONENT ADS7886_drvr
53 COMPONENT AD7688_drvr
54 GENERIC (
54 GENERIC (
55 ChanelCount : INTEGER;
55 ChanelCount : INTEGER;
56 ncycle_cnv_high : INTEGER := 79;
56 ncycle_cnv_high : INTEGER := 79;
@@ -162,26 +162,26 Type ADS127X_config is
162 MODE : ADS127X_MODE_Type;
162 MODE : ADS127X_MODE_Type;
163 end record;
163 end record;
164
164
165 COMPONENT ADS1274_DRIVER is
165 COMPONENT ADS1274_DRIVER is
166 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
166 generic(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
167 port(
167 port(
168 Clk : in std_logic;
168 Clk : in std_logic;
169 reset : in std_logic;
169 reset : in std_logic;
170 SpiClk : out std_logic;
170 SpiClk : out std_logic;
171 DIN : in std_logic_vector(3 downto 0);
171 DIN : in std_logic_vector(3 downto 0);
172 Ready : in std_logic;
172 Ready : in std_logic;
173 Format : out std_logic_vector(2 downto 0);
173 Format : out std_logic_vector(2 downto 0);
174 Mode : out std_logic_vector(1 downto 0);
174 Mode : out std_logic_vector(1 downto 0);
175 ClkDiv : out std_logic;
175 ClkDiv : out std_logic;
176 PWDOWN : out std_logic_vector(3 downto 0);
176 PWDOWN : out std_logic_vector(3 downto 0);
177 SmplClk : in std_logic;
177 SmplClk : in std_logic;
178 OUT0 : out std_logic_vector(23 downto 0);
178 OUT0 : out std_logic_vector(23 downto 0);
179 OUT1 : out std_logic_vector(23 downto 0);
179 OUT1 : out std_logic_vector(23 downto 0);
180 OUT2 : out std_logic_vector(23 downto 0);
180 OUT2 : out std_logic_vector(23 downto 0);
181 OUT3 : out std_logic_vector(23 downto 0);
181 OUT3 : out std_logic_vector(23 downto 0);
182 FSynch : out std_logic;
182 FSynch : out std_logic;
183 test : out std_logic
183 test : out std_logic
184 );
184 );
185 end COMPONENT;
185 end COMPONENT;
186
186
187
187
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@@ -1,7 +1,6
1 fifo_latency_correction.vhd
1 fifo_latency_correction.vhd
2 lpp_dma.vhd
2 lpp_dma.vhd
3 lpp_dma_apbreg.vhd
3 lpp_dma_apbreg.vhd
4 lpp_dma_fsm.vhd
5 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
6 lpp_dma_pkg.vhd
5 lpp_dma_pkg.vhd
7 lpp_dma_send_16word.vhd
6 lpp_dma_send_16word.vhd
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This diff has been collapsed as it changes many lines, (606 lines changed) Show them Hide them
@@ -1,303 +1,303
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 LIBRARY lpp;
3 LIBRARY lpp;
4 USE lpp.lpp_ad_conv.ALL;
4 USE lpp.lpp_ad_conv.ALL;
5 USE lpp.iir_filter.ALL;
5 USE lpp.iir_filter.ALL;
6 USE lpp.FILTERcfg.ALL;
6 USE lpp.FILTERcfg.ALL;
7 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_memory.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
8 USE lpp.lpp_top_lfr_pkg.ALL;
9 LIBRARY techmap;
9 LIBRARY techmap;
10 USE techmap.gencomp.ALL;
10 USE techmap.gencomp.ALL;
11
11
12 ENTITY lpp_top_acq IS
12 ENTITY lpp_top_acq IS
13 GENERIC(
13 GENERIC(
14 tech : INTEGER := 0
14 tech : INTEGER := 0
15 );
15 );
16 PORT (
16 PORT (
17 -- ADS7886
17 -- ADS7886
18 cnv_run : IN STD_LOGIC;
18 cnv_run : IN STD_LOGIC;
19 cnv : OUT STD_LOGIC;
19 cnv : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
20 sck : OUT STD_LOGIC;
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
21 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
22 --
22 --
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
23 cnv_clk : IN STD_LOGIC; -- 49 MHz
24 cnv_rstn : IN STD_LOGIC;
24 cnv_rstn : IN STD_LOGIC;
25 --
25 --
26 clk : IN STD_LOGIC; -- 25 MHz
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 --
31 --
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
39 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
40 );
40 );
41 END lpp_top_acq;
41 END lpp_top_acq;
42
42
43 ARCHITECTURE tb OF lpp_top_acq IS
43 ARCHITECTURE tb OF lpp_top_acq IS
44
44
45 COMPONENT Downsampling
45 COMPONENT Downsampling
46 GENERIC (
46 GENERIC (
47 ChanelCount : INTEGER;
47 ChanelCount : INTEGER;
48 SampleSize : INTEGER;
48 SampleSize : INTEGER;
49 DivideParam : INTEGER);
49 DivideParam : INTEGER);
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
53 sample_in_val : IN STD_LOGIC;
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
54 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
55 sample_out_val : OUT STD_LOGIC;
55 sample_out_val : OUT STD_LOGIC;
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
56 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
57 END COMPONENT;
57 END COMPONENT;
58
58
59 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
60 CONSTANT ChanelCount : INTEGER := 8;
60 CONSTANT ChanelCount : INTEGER := 8;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
61 CONSTANT ncycle_cnv_high : INTEGER := 79;
62 CONSTANT ncycle_cnv : INTEGER := 500;
62 CONSTANT ncycle_cnv : INTEGER := 500;
63
63
64 -----------------------------------------------------------------------------
64 -----------------------------------------------------------------------------
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
65 SIGNAL sample : Samples(ChanelCount-1 DOWNTO 0);
66 SIGNAL sample_val : STD_LOGIC;
66 SIGNAL sample_val : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
67 SIGNAL sample_val_delay : STD_LOGIC;
68 -----------------------------------------------------------------------------
68 -----------------------------------------------------------------------------
69 CONSTANT Coef_SZ : INTEGER := 9;
69 CONSTANT Coef_SZ : INTEGER := 9;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
70 CONSTANT CoefCntPerCel : INTEGER := 6;
71 CONSTANT CoefPerCel : INTEGER := 5;
71 CONSTANT CoefPerCel : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
72 CONSTANT Cels_count : INTEGER := 5;
73
73
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
74 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
75 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
76 --
76 --
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
77 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --
79 --
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
80 SIGNAL sample_filter_v2_out_r_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
81 SIGNAL sample_filter_v2_out_r : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
83 SIGNAL downsampling_cnt : STD_LOGIC_VECTOR(1 DOWNTO 0);
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
84 SIGNAL sample_downsampling_out_val : STD_LOGIC;
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
86 --
86 --
87 SIGNAL sample_f0_val : STD_LOGIC;
87 SIGNAL sample_f0_val : STD_LOGIC;
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
92 --
92 --
93 SIGNAL sample_f2_val : STD_LOGIC;
93 SIGNAL sample_f2_val : STD_LOGIC;
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
94 SIGNAL sample_f2 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
95 --
95 --
96 SIGNAL sample_f3_val : STD_LOGIC;
96 SIGNAL sample_f3_val : STD_LOGIC;
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
97 SIGNAL sample_f3 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
98
98
99 BEGIN
99 BEGIN
100
100
101 -- component instantiation
101 -- component instantiation
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 DIGITAL_acquisition : ADS7886_drvr
103 DIGITAL_acquisition : AD7688_drvr
104 GENERIC MAP (
104 GENERIC MAP (
105 ChanelCount => ChanelCount,
105 ChanelCount => ChanelCount,
106 ncycle_cnv_high => ncycle_cnv_high,
106 ncycle_cnv_high => ncycle_cnv_high,
107 ncycle_cnv => ncycle_cnv)
107 ncycle_cnv => ncycle_cnv)
108 PORT MAP (
108 PORT MAP (
109 cnv_clk => cnv_clk, --
109 cnv_clk => cnv_clk, --
110 cnv_rstn => cnv_rstn, --
110 cnv_rstn => cnv_rstn, --
111 cnv_run => cnv_run, --
111 cnv_run => cnv_run, --
112 cnv => cnv, --
112 cnv => cnv, --
113 clk => clk, --
113 clk => clk, --
114 rstn => rstn, --
114 rstn => rstn, --
115 sck => sck, --
115 sck => sck, --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
116 sdo => sdo(ChanelCount-1 DOWNTO 0), --
117 sample => sample,
117 sample => sample,
118 sample_val => sample_val);
118 sample_val => sample_val);
119
119
120 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
121
121
122 PROCESS (clk, rstn)
122 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
123 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
124 IF rstn = '0' THEN -- asynchronous reset (active low)
125 sample_val_delay <= '0';
125 sample_val_delay <= '0';
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
126 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
127 sample_val_delay <= sample_val;
127 sample_val_delay <= sample_val;
128 END IF;
128 END IF;
129 END PROCESS;
129 END PROCESS;
130
130
131 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
132 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
133 SampleLoop : FOR j IN 0 TO 15 GENERATE
134 sample_filter_in(i, j) <= sample(i)(j);
134 sample_filter_in(i, j) <= sample(i)(j);
135 END GENERATE;
135 END GENERATE;
136
136
137 sample_filter_in(i, 16) <= sample(i)(15);
137 sample_filter_in(i, 16) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
138 sample_filter_in(i, 17) <= sample(i)(15);
139 END GENERATE;
139 END GENERATE;
140
140
141 coefs_v2 <= CoefsInitValCst_v2;
141 coefs_v2 <= CoefsInitValCst_v2;
142
142
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
143 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
144 GENERIC MAP (
144 GENERIC MAP (
145 tech => 0,
145 tech => 0,
146 Mem_use => use_RAM,
146 Mem_use => use_CEL,
147 Sample_SZ => 18,
147 Sample_SZ => 18,
148 Coef_SZ => Coef_SZ,
148 Coef_SZ => Coef_SZ,
149 Coef_Nb => 25, -- TODO
149 Coef_Nb => 25, -- TODO
150 Coef_sel_SZ => 5, -- TODO
150 Coef_sel_SZ => 5, -- TODO
151 Cels_count => Cels_count,
151 Cels_count => Cels_count,
152 ChanelsCount => ChanelCount)
152 ChanelsCount => ChanelCount)
153 PORT MAP (
153 PORT MAP (
154 rstn => rstn,
154 rstn => rstn,
155 clk => clk,
155 clk => clk,
156 virg_pos => 7,
156 virg_pos => 7,
157 coefs => coefs_v2,
157 coefs => coefs_v2,
158 sample_in_val => sample_val_delay,
158 sample_in_val => sample_val_delay,
159 sample_in => sample_filter_in,
159 sample_in => sample_filter_in,
160 sample_out_val => sample_filter_v2_out_val,
160 sample_out_val => sample_filter_v2_out_val,
161 sample_out => sample_filter_v2_out);
161 sample_out => sample_filter_v2_out);
162
162
163 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
164 PROCESS (clk, rstn)
164 PROCESS (clk, rstn)
165 BEGIN -- PROCESS
165 BEGIN -- PROCESS
166 IF rstn = '0' THEN -- asynchronous reset (active low)
166 IF rstn = '0' THEN -- asynchronous reset (active low)
167 sample_filter_v2_out_r_val <= '0';
167 sample_filter_v2_out_r_val <= '0';
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
168 rst_all_chanel : FOR I IN ChanelCount-1 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
169 rst_all_bits : FOR J IN 17 DOWNTO 0 LOOP
170 sample_filter_v2_out_r(I, J) <= '0';
170 sample_filter_v2_out_r(I, J) <= '0';
171 END LOOP rst_all_bits;
171 END LOOP rst_all_bits;
172 END LOOP rst_all_chanel;
172 END LOOP rst_all_chanel;
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
174 sample_filter_v2_out_r_val <= sample_filter_v2_out_val;
175 IF sample_filter_v2_out_val = '1' THEN
175 IF sample_filter_v2_out_val = '1' THEN
176 sample_filter_v2_out_r <= sample_filter_v2_out;
176 sample_filter_v2_out_r <= sample_filter_v2_out;
177 END IF;
177 END IF;
178 END IF;
178 END IF;
179 END PROCESS;
179 END PROCESS;
180
180
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- F0 -- @24.576 kHz
182 -- F0 -- @24.576 kHz
183 -----------------------------------------------------------------------------
183 -----------------------------------------------------------------------------
184 Downsampling_f0 : Downsampling
184 Downsampling_f0 : Downsampling
185 GENERIC MAP (
185 GENERIC MAP (
186 ChanelCount => ChanelCount,
186 ChanelCount => ChanelCount,
187 SampleSize => 18,
187 SampleSize => 18,
188 DivideParam => 4)
188 DivideParam => 4)
189 PORT MAP (
189 PORT MAP (
190 clk => clk,
190 clk => clk,
191 rstn => rstn,
191 rstn => rstn,
192 sample_in_val => sample_filter_v2_out_val ,
192 sample_in_val => sample_filter_v2_out_val ,
193 sample_in => sample_filter_v2_out,
193 sample_in => sample_filter_v2_out,
194 sample_out_val => sample_f0_val,
194 sample_out_val => sample_f0_val,
195 sample_out => sample_f0);
195 sample_out => sample_f0);
196
196
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
197 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
198 sample_f0_wdata(I) <= sample_f0(0, I);
198 sample_f0_wdata(I) <= sample_f0(0, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
199 sample_f0_wdata(16*1+I) <= sample_f0(1, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
200 sample_f0_wdata(16*2+I) <= sample_f0(2, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
201 sample_f0_wdata(16*3+I) <= sample_f0(6, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
203 END GENERATE all_bit_sample_f0;
203 END GENERATE all_bit_sample_f0;
204
204
205 sample_f0_wen <= NOT(sample_f0_val) &
205 sample_f0_wen <= NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
206 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
207 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
208 NOT(sample_f0_val) &
209 NOT(sample_f0_val);
209 NOT(sample_f0_val);
210
210
211 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
212 -- F1 -- @4096 Hz
212 -- F1 -- @4096 Hz
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214 Downsampling_f1 : Downsampling
214 Downsampling_f1 : Downsampling
215 GENERIC MAP (
215 GENERIC MAP (
216 ChanelCount => ChanelCount,
216 ChanelCount => ChanelCount,
217 SampleSize => 18,
217 SampleSize => 18,
218 DivideParam => 6)
218 DivideParam => 6)
219 PORT MAP (
219 PORT MAP (
220 clk => clk,
220 clk => clk,
221 rstn => rstn,
221 rstn => rstn,
222 sample_in_val => sample_f0_val ,
222 sample_in_val => sample_f0_val ,
223 sample_in => sample_f0,
223 sample_in => sample_f0,
224 sample_out_val => sample_f1_val,
224 sample_out_val => sample_f1_val,
225 sample_out => sample_f1);
225 sample_out => sample_f1);
226
226
227 sample_f1_wen <= NOT(sample_f1_val) &
227 sample_f1_wen <= NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
228 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
229 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
230 NOT(sample_f1_val) &
231 NOT(sample_f1_val);
231 NOT(sample_f1_val);
232
232
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
233 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
234 sample_f1_wdata(I) <= sample_f1(0, I);
234 sample_f1_wdata(I) <= sample_f1(0, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
235 sample_f1_wdata(16*1+I) <= sample_f1(1, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
236 sample_f1_wdata(16*2+I) <= sample_f1(2, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
237 sample_f1_wdata(16*3+I) <= sample_f1(6, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
238 sample_f1_wdata(16*4+I) <= sample_f1(7, I);
239 END GENERATE all_bit_sample_f1;
239 END GENERATE all_bit_sample_f1;
240
240
241 -----------------------------------------------------------------------------
241 -----------------------------------------------------------------------------
242 -- F2 -- @16 Hz
242 -- F2 -- @16 Hz
243 -----------------------------------------------------------------------------
243 -----------------------------------------------------------------------------
244 Downsampling_f2 : Downsampling
244 Downsampling_f2 : Downsampling
245 GENERIC MAP (
245 GENERIC MAP (
246 ChanelCount => ChanelCount,
246 ChanelCount => ChanelCount,
247 SampleSize => 18,
247 SampleSize => 18,
248 DivideParam => 256)
248 DivideParam => 256)
249 PORT MAP (
249 PORT MAP (
250 clk => clk,
250 clk => clk,
251 rstn => rstn,
251 rstn => rstn,
252 sample_in_val => sample_f1_val ,
252 sample_in_val => sample_f1_val ,
253 sample_in => sample_f1,
253 sample_in => sample_f1,
254 sample_out_val => sample_f2_val,
254 sample_out_val => sample_f2_val,
255 sample_out => sample_f2);
255 sample_out => sample_f2);
256
256
257 sample_f2_wen <= NOT(sample_f2_val) &
257 sample_f2_wen <= NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
258 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
259 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
260 NOT(sample_f2_val) &
261 NOT(sample_f2_val);
261 NOT(sample_f2_val);
262
262
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
263 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
264 sample_f2_wdata(I) <= sample_f2(0, I);
264 sample_f2_wdata(I) <= sample_f2(0, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
265 sample_f2_wdata(16*1+I) <= sample_f2(1, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
266 sample_f2_wdata(16*2+I) <= sample_f2(2, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
267 sample_f2_wdata(16*3+I) <= sample_f2(6, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
268 sample_f2_wdata(16*4+I) <= sample_f2(7, I);
269 END GENERATE all_bit_sample_f2;
269 END GENERATE all_bit_sample_f2;
270
270
271 -----------------------------------------------------------------------------
271 -----------------------------------------------------------------------------
272 -- F3 -- @256 Hz
272 -- F3 -- @256 Hz
273 -----------------------------------------------------------------------------
273 -----------------------------------------------------------------------------
274 Downsampling_f3 : Downsampling
274 Downsampling_f3 : Downsampling
275 GENERIC MAP (
275 GENERIC MAP (
276 ChanelCount => ChanelCount,
276 ChanelCount => ChanelCount,
277 SampleSize => 18,
277 SampleSize => 18,
278 DivideParam => 96)
278 DivideParam => 96)
279 PORT MAP (
279 PORT MAP (
280 clk => clk,
280 clk => clk,
281 rstn => rstn,
281 rstn => rstn,
282 sample_in_val => sample_f0_val ,
282 sample_in_val => sample_f0_val ,
283 sample_in => sample_f0,
283 sample_in => sample_f0,
284 sample_out_val => sample_f3_val,
284 sample_out_val => sample_f3_val,
285 sample_out => sample_f3);
285 sample_out => sample_f3);
286
286
287 sample_f3_wen <= (NOT sample_f3_val) &
287 sample_f3_wen <= (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
288 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
289 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
290 (NOT sample_f3_val) &
291 (NOT sample_f3_val);
291 (NOT sample_f3_val);
292
292
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
293 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
294 sample_f3_wdata(I) <= sample_f3(0, I);
294 sample_f3_wdata(I) <= sample_f3(0, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
295 sample_f3_wdata(16*1+I) <= sample_f3(1, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
296 sample_f3_wdata(16*2+I) <= sample_f3(2, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
297 sample_f3_wdata(16*3+I) <= sample_f3(6, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
298 sample_f3_wdata(16*4+I) <= sample_f3(7, I);
299 END GENERATE all_bit_sample_f3;
299 END GENERATE all_bit_sample_f3;
300
300
301
301
302
302
303 END tb;
303 END tb;
Show file before | Show file after | Hide comments
@@ -136,6 +136,9 BEGIN -- beh
136 reg.addr_matrix_f1 <= (OTHERS => '0');
136 reg.addr_matrix_f1 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
137 reg.addr_matrix_f2 <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
138 prdata <= (OTHERS => '0');
139
140 apbo.pirq <= (OTHERS => '0');
141
139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
142 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
140
143
141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
144 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
@@ -186,10 +189,21 BEGIN -- beh
186 END CASE;
189 END CASE;
187 END IF;
190 END IF;
188 END IF;
191 END IF;
192
193 apbo.pirq(pirq) <= ( reg.config_active_interruption_onNewMatrix AND ( ready_matrix_f0_0 OR
194 ready_matrix_f0_1 OR
195 ready_matrix_f1 OR
196 ready_matrix_f2)
197 )
198 OR
199 ( reg.config_active_interruption_onError AND ( error_anticipating_empty_fifo OR
200 error_bad_component_error)
201 );
202
203
189 END IF;
204 END IF;
190 END PROCESS lpp_top_apbreg;
205 END PROCESS lpp_top_apbreg;
191
206
192 apbo.pirq <= (OTHERS => '0');
193 apbo.pindex <= pindex;
207 apbo.pindex <= pindex;
194 apbo.pconfig <= pconfig;
208 apbo.pconfig <= pconfig;
195 apbo.prdata <= prdata;
209 apbo.prdata <= prdata;
Show file before | Show file after | Hide comments
@@ -401,8 +401,11 BEGIN
401 addr_matrix_f2 => addr_matrix_f2);
401 addr_matrix_f2 => addr_matrix_f2);
402
402
403
403
404 --TODO : add the irq alert for DMA matrix transfert ending
404 --DONE : add the irq alert for DMA matrix transfert ending
405
405 --TODO : add 5 bit register into APB to control the DATA SHIPING
406 --TODO : add 5 bit register into APB to control the DATA SHIPING
407 --TODO : data shiping
408
406 --TODO : add Spectral Matrix (FFT + SP)
409 --TODO : add Spectral Matrix (FFT + SP)
407 --TODO : add DMA for WaveForms Picker
410 --TODO : add DMA for WaveForms Picker
408 --TODO : add APB Reg to control WaveForms Picker
411 --TODO : add APB Reg to control WaveForms Picker
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