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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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LIBRARY lpp;
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USE lpp.lpp_ad_conv.ALL;
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-------------------------------------------------------------------------------
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ENTITY TB_Data_Acquisition IS
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END TB_Data_Acquisition;
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-------------------------------------------------------------------------------
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ARCHITECTURE tb OF TB_Data_Acquisition IS
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COMPONENT TestModule_ADS7886
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GENERIC (
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freq : INTEGER;
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amplitude : INTEGER;
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impulsion : INTEGER);
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PORT (
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cnv_run : IN STD_LOGIC;
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cnv : IN STD_LOGIC;
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sck : IN STD_LOGIC;
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sdo : OUT STD_LOGIC);
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END COMPONENT;
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COMPONENT Top_Data_Acquisition
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PORT (
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cnv_run : IN STD_LOGIC;
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cnv : OUT STD_LOGIC;
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sck : OUT STD_LOGIC;
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sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
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cnv_clk : IN STD_LOGIC;
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cnv_rstn : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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rstn : IN STD_LOGIC;
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--
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sample_f0_0_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_0_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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sample_f0_0_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_0_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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sample_f0_1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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sample_f0_1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f0_1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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sample_f1_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f1_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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sample_f1_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f1_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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--
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sample_f3_ren : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f3_rdata : OUT STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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sample_f3_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
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sample_f3_empty : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
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END COMPONENT;
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-- component ports
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SIGNAL cnv_rstn : STD_LOGIC;
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SIGNAL cnv : STD_LOGIC;
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SIGNAL rstn : STD_LOGIC;
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SIGNAL sck : STD_LOGIC;
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SIGNAL sdo : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL run_cnv : STD_LOGIC;
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-- clock
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signal Clk : STD_LOGIC := '1';
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SIGNAL cnv_clk : STD_LOGIC := '1';
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_0_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_0_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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SIGNAL sample_f0_0_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_0_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f0_1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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SIGNAL sample_f0_1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f0_1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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-----------------------------------------------------------------------------
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SIGNAL sample_f3_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_rdata : STD_LOGIC_VECTOR((5*18)-1 DOWNTO 0);
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SIGNAL sample_f3_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
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SIGNAL sample_f3_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
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BEGIN -- tb
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MODULE_ADS7886: FOR I IN 0 TO 6 GENERATE
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TestModule_ADS7886_u: TestModule_ADS7886
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GENERIC MAP (
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freq => 24*(I+1),
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amplitude => 30000/(I+1),
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impulsion => 0)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(I));
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END GENERATE MODULE_ADS7886;
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TestModule_ADS7886_u: TestModule_ADS7886
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GENERIC MAP (
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freq => 0,
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amplitude => 30000,
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impulsion => 1)
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo(7));
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-- clock generation
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Clk <= not Clk after 20 ns; -- 25 Mhz
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cnv_clk <= not cnv_clk after 10173 ps; -- 49.152 MHz
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-- waveform generation
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WaveGen_Proc: process
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begin
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-- insert signal assignments here
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wait until Clk = '1';
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rstn <= '0';
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cnv_rstn <= '0';
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run_cnv <= '0';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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rstn <= '1';
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cnv_rstn <= '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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wait until Clk = '1';
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run_cnv <= '1';
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wait;
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end process WaveGen_Proc;
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-----------------------------------------------------------------------------
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Top_Data_Acquisition_1: Top_Data_Acquisition
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PORT MAP (
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cnv_run => run_cnv,
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cnv => cnv,
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sck => sck,
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sdo => sdo,
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cnv_clk => cnv_clk,
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cnv_rstn => cnv_rstn,
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clk => clk,
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rstn => rstn,
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--
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sample_f0_0_ren => sample_f0_0_ren,
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sample_f0_0_rdata => sample_f0_0_rdata,
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sample_f0_0_full => sample_f0_0_full,
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sample_f0_0_empty => sample_f0_0_empty,
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--
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sample_f0_1_ren => sample_f0_1_ren,
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sample_f0_1_rdata => sample_f0_1_rdata,
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sample_f0_1_full => sample_f0_1_full,
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sample_f0_1_empty => sample_f0_1_empty,
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--
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sample_f1_ren => sample_f1_ren,
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sample_f1_rdata => sample_f1_rdata,
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sample_f1_full => sample_f1_full,
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sample_f1_empty => sample_f1_empty,
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--
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sample_f3_ren => sample_f3_ren,
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sample_f3_rdata => sample_f3_rdata,
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sample_f3_full => sample_f3_full,
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sample_f3_empty => sample_f3_empty
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);
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sample_f0_0_ren <= (OTHERS => '1');
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sample_f0_1_ren <= (OTHERS => '1');
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sample_f1_ren <= (OTHERS => '1');
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sample_f3_ren <= (OTHERS => '1');
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END tb;
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