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1 | AMBA_Peripherals.vhd | |||
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2 | apb_lfr_time_managment/lpp_lfr_time_management.vhd | |||
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3 | apb_lfr_time_managment/apb_lfr_time_management.vhd | |||
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4 | apb_lfr_time_managment/lfr_time_management.vhd | |||
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5 | apb_lfr_time_managment/lpp_counter.vhd |
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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | -- jean-christophe.pellion@easii-ic.com | |||
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22 | ------------------------------------------------------------------------------- | |||
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23 | ||||
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24 | LIBRARY IEEE; | |||
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25 | USE IEEE.STD_LOGIC_1164.ALL; | |||
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26 | ||||
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27 | ENTITY lpp_front_detection_LPP_JCP IS | |||
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28 | ||||
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29 | PORT ( | |||
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30 | clk : IN STD_LOGIC; | |||
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31 | rstn : IN STD_LOGIC; | |||
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32 | sin : IN STD_LOGIC; | |||
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33 | sout : OUT STD_LOGIC); | |||
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34 | ||||
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35 | END lpp_front_detection_LPP_JCP; | |||
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36 | ||||
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37 | ARCHITECTURE beh OF lpp_front_detection_LPP_JCP IS | |||
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38 | ||||
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39 | SIGNAL reg : STD_LOGIC; | |||
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40 | SIGNAL sout_reg : STD_LOGIC; | |||
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41 | ||||
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42 | BEGIN -- beh | |||
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43 | ||||
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44 | PROCESS (clk, rstn) | |||
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45 | BEGIN -- PROCESS | |||
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46 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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47 | reg <= '0'; | |||
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48 | sout_reg <= '0'; | |||
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49 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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50 | reg <= sin; | |||
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51 | IF sin = NOT reg THEN | |||
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52 | sout_reg <= '1'; | |||
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53 | ELSE | |||
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54 | sout_reg <= '0'; | |||
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55 | END IF; | |||
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56 | END IF; | |||
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57 | END PROCESS; | |||
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58 | ||||
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59 | sout <= sout_reg; | |||
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60 | ||||
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61 | END beh; |
@@ -0,0 +1,59 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ------------------------------------------------------------------------------- | |||
|
23 | ||||
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24 | LIBRARY IEEE; | |||
|
25 | USE IEEE.STD_LOGIC_1164.ALL; | |||
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26 | ||||
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27 | ENTITY lpp_front_to_level_LPP_JCP IS | |||
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28 | ||||
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29 | PORT ( | |||
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30 | clk : IN STD_LOGIC; | |||
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31 | rstn : IN STD_LOGIC; | |||
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32 | sin : IN STD_LOGIC; | |||
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33 | sout : OUT STD_LOGIC); | |||
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34 | ||||
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35 | END lpp_front_to_level_LPP_JCP; | |||
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36 | ||||
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37 | ARCHITECTURE beh OF lpp_front_to_level_LPP_JCP IS | |||
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38 | ||||
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39 | SIGNAL reg : STD_LOGIC; | |||
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40 | ||||
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41 | SIGNAL sout_reg : STD_LOGIC; | |||
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42 | BEGIN -- beh | |||
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43 | ||||
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44 | PROCESS (clk, rstn) | |||
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45 | BEGIN -- PROCESS | |||
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46 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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47 | reg <= '0'; | |||
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48 | sout_reg <= '0'; | |||
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49 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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50 | reg <= sin; | |||
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51 | IF sin = '1' AND reg = '0' THEN | |||
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52 | sout_reg <= NOT sout_reg; | |||
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53 | END IF; | |||
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54 | END IF; | |||
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55 | END PROCESS; | |||
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56 | ||||
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57 | sout <= sout_reg; | |||
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58 | ||||
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59 | END beh; |
@@ -0,0 +1,59 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ------------------------------------------------------------------------------- | |||
|
23 | ||||
|
24 | LIBRARY IEEE; | |||
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25 | USE IEEE.numeric_std.ALL; | |||
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26 | USE IEEE.std_logic_1164.ALL; | |||
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27 | ||||
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28 | ENTITY SYNC_FF_LPP_JCP IS | |||
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29 | ||||
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30 | GENERIC ( | |||
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31 | NB_FF_OF_SYNC : INTEGER := 2); | |||
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32 | ||||
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33 | PORT ( | |||
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34 | clk : IN STD_LOGIC; | |||
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35 | rstn : IN STD_LOGIC; | |||
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36 | A : IN STD_LOGIC; | |||
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37 | A_sync : OUT STD_LOGIC); | |||
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38 | ||||
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39 | END SYNC_FF_LPP_JCP; | |||
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40 | ||||
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41 | ARCHITECTURE beh OF SYNC_FF_LPP_JCP IS | |||
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42 | SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0); | |||
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43 | BEGIN -- beh | |||
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44 | ||||
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45 | sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE | |||
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46 | PROCESS (clk, rstn) | |||
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47 | BEGIN -- PROCESS | |||
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48 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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49 | A_temp(I) <= '0'; | |||
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50 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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51 | A_temp(I) <= A_temp(I+1); | |||
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52 | END IF; | |||
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53 | END PROCESS; | |||
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54 | END GENERATE sync_loop; | |||
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55 | ||||
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56 | A_temp(NB_FF_OF_SYNC) <= A; | |||
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57 | A_sync <= A_temp(0); | |||
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58 | ||||
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59 | END beh; |
@@ -0,0 +1,70 | |||||
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1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe Pellion | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | -- jean-christophe.pellion@easii-ic.com | |||
|
22 | ------------------------------------------------------------------------------- | |||
|
23 | ||||
|
24 | LIBRARY IEEE; | |||
|
25 | USE IEEE.numeric_std.ALL; | |||
|
26 | USE IEEE.std_logic_1164.ALL; | |||
|
27 | ||||
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28 | LIBRARY staging; | |||
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29 | USE staging.general_purpose_LPP_JCP.ALL; | |||
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30 | ||||
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31 | ENTITY SYNC_VALID_BIT_LPP_JCP IS | |||
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32 | GENERIC ( | |||
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33 | NB_FF_OF_SYNC : INTEGER := 2); | |||
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34 | PORT ( | |||
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35 | clk_in : IN STD_LOGIC; | |||
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36 | clk_out : IN STD_LOGIC; | |||
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37 | rstn : IN STD_LOGIC; | |||
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38 | sin : IN STD_LOGIC; | |||
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39 | sout : OUT STD_LOGIC); | |||
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40 | END SYNC_VALID_BIT_LPP_JCP; | |||
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41 | ||||
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42 | ARCHITECTURE beh OF SYNC_VALID_BIT_LPP_JCP IS | |||
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43 | SIGNAL s_1 : STD_LOGIC; | |||
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44 | SIGNAL s_2 : STD_LOGIC; | |||
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45 | BEGIN -- beh | |||
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46 | ||||
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47 | lpp_front_to_level_1: lpp_front_to_level_LPP_JCP | |||
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48 | PORT MAP ( | |||
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49 | clk => clk_in, | |||
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50 | rstn => rstn, | |||
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51 | sin => sin, | |||
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52 | sout => s_1); | |||
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53 | ||||
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54 | SYNC_FF_1: SYNC_FF_LPP_JCP | |||
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55 | GENERIC MAP ( | |||
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56 | NB_FF_OF_SYNC => NB_FF_OF_SYNC) | |||
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57 | PORT MAP ( | |||
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58 | clk => clk_out, | |||
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59 | rstn => rstn, | |||
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60 | A => s_1, | |||
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61 | A_sync => s_2); | |||
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62 | ||||
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63 | lpp_front_detection_1: lpp_front_detection_LPP_JCP | |||
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64 | PORT MAP ( | |||
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65 | clk => clk_out, | |||
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66 | rstn => rstn, | |||
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67 | sin => s_2, | |||
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68 | sout => sout); | |||
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69 | ||||
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70 | END beh; |
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