##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » USERS » PELLION » VHD_Lib
RSS

Clone from http://pc-instru.lpp.polytechnique.fr:5000/VHD_Lib

add apb_lfr_time_managment
pellion -
r311:bf3115c7b73f next
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,5
1 AMBA_Peripherals.vhd
2 apb_lfr_time_managment/lpp_lfr_time_management.vhd
3 apb_lfr_time_managment/apb_lfr_time_management.vhd
4 apb_lfr_time_managment/lfr_time_management.vhd
5 apb_lfr_time_managment/lpp_counter.vhd
Show file before | Show file after | Hide comments
@@ -0,0 +1,61
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26
27 ENTITY lpp_front_detection_LPP_JCP IS
28
29 PORT (
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32 sin : IN STD_LOGIC;
33 sout : OUT STD_LOGIC);
34
35 END lpp_front_detection_LPP_JCP;
36
37 ARCHITECTURE beh OF lpp_front_detection_LPP_JCP IS
38
39 SIGNAL reg : STD_LOGIC;
40 SIGNAL sout_reg : STD_LOGIC;
41
42 BEGIN -- beh
43
44 PROCESS (clk, rstn)
45 BEGIN -- PROCESS
46 IF rstn = '0' THEN -- asynchronous reset (active low)
47 reg <= '0';
48 sout_reg <= '0';
49 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
50 reg <= sin;
51 IF sin = NOT reg THEN
52 sout_reg <= '1';
53 ELSE
54 sout_reg <= '0';
55 END IF;
56 END IF;
57 END PROCESS;
58
59 sout <= sout_reg;
60
61 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,59
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.STD_LOGIC_1164.ALL;
26
27 ENTITY lpp_front_to_level_LPP_JCP IS
28
29 PORT (
30 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
32 sin : IN STD_LOGIC;
33 sout : OUT STD_LOGIC);
34
35 END lpp_front_to_level_LPP_JCP;
36
37 ARCHITECTURE beh OF lpp_front_to_level_LPP_JCP IS
38
39 SIGNAL reg : STD_LOGIC;
40
41 SIGNAL sout_reg : STD_LOGIC;
42 BEGIN -- beh
43
44 PROCESS (clk, rstn)
45 BEGIN -- PROCESS
46 IF rstn = '0' THEN -- asynchronous reset (active low)
47 reg <= '0';
48 sout_reg <= '0';
49 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
50 reg <= sin;
51 IF sin = '1' AND reg = '0' THEN
52 sout_reg <= NOT sout_reg;
53 END IF;
54 END IF;
55 END PROCESS;
56
57 sout <= sout_reg;
58
59 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,59
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.numeric_std.ALL;
26 USE IEEE.std_logic_1164.ALL;
27
28 ENTITY SYNC_FF_LPP_JCP IS
29
30 GENERIC (
31 NB_FF_OF_SYNC : INTEGER := 2);
32
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 A : IN STD_LOGIC;
37 A_sync : OUT STD_LOGIC);
38
39 END SYNC_FF_LPP_JCP;
40
41 ARCHITECTURE beh OF SYNC_FF_LPP_JCP IS
42 SIGNAL A_temp : STD_LOGIC_VECTOR(NB_FF_OF_SYNC DOWNTO 0);
43 BEGIN -- beh
44
45 sync_loop : FOR I IN 0 TO NB_FF_OF_SYNC-1 GENERATE
46 PROCESS (clk, rstn)
47 BEGIN -- PROCESS
48 IF rstn = '0' THEN -- asynchronous reset (active low)
49 A_temp(I) <= '0';
50 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
51 A_temp(I) <= A_temp(I+1);
52 END IF;
53 END PROCESS;
54 END GENERATE sync_loop;
55
56 A_temp(NB_FF_OF_SYNC) <= A;
57 A_sync <= A_temp(0);
58
59 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,70
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.numeric_std.ALL;
26 USE IEEE.std_logic_1164.ALL;
27
28 LIBRARY staging;
29 USE staging.general_purpose_LPP_JCP.ALL;
30
31 ENTITY SYNC_VALID_BIT_LPP_JCP IS
32 GENERIC (
33 NB_FF_OF_SYNC : INTEGER := 2);
34 PORT (
35 clk_in : IN STD_LOGIC;
36 clk_out : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 sin : IN STD_LOGIC;
39 sout : OUT STD_LOGIC);
40 END SYNC_VALID_BIT_LPP_JCP;
41
42 ARCHITECTURE beh OF SYNC_VALID_BIT_LPP_JCP IS
43 SIGNAL s_1 : STD_LOGIC;
44 SIGNAL s_2 : STD_LOGIC;
45 BEGIN -- beh
46
47 lpp_front_to_level_1: lpp_front_to_level_LPP_JCP
48 PORT MAP (
49 clk => clk_in,
50 rstn => rstn,
51 sin => sin,
52 sout => s_1);
53
54 SYNC_FF_1: SYNC_FF_LPP_JCP
55 GENERIC MAP (
56 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
57 PORT MAP (
58 clk => clk_out,
59 rstn => rstn,
60 A => s_1,
61 A_sync => s_2);
62
63 lpp_front_detection_1: lpp_front_detection_LPP_JCP
64 PORT MAP (
65 clk => clk_out,
66 rstn => rstn,
67 sin => s_2,
68 sout => sout);
69
70 END beh;
Show file before | Show file after | Hide comments
@@ -0,0 +1,5
1 general_purpose.vhd
2 Synchronizer/SYNC_FF.vhd
3 Synchronizer/SYNC_VALID_BIT.vhd
4 FrontDetection/lpp_front_detection.vhd
5 FrontDetection/lpp_front_to_level.vhd
Show file before | Show file after | Hide comments
@@ -1,1 +1,3
1 ./LPP/JCP/SOC
1 ./LPP/JCP/SOC
2 ./LPP/JCP/AMBA_Peripherals
3 ./LPP/JCP/general_purpose
General Comments 0
You need to be logged in to leave comments. Login now